1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
26 // runEnums - Print out enum values for all of the registers.
27 void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
28 CodeGenTarget Target(Records);
29 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
31 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
33 EmitSourceFileHeader("Target Register Enum Values", OS);
34 OS << "namespace llvm {\n\n";
36 if (!Namespace.empty())
37 OS << "namespace " << Namespace << " {\n";
38 OS << "enum {\n NoRegister,\n";
40 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
41 OS << " " << Registers[i].getName() << " = " <<
42 Registers[i].EnumValue << ",\n";
43 assert(Registers.size() == Registers[Registers.size()-1].EnumValue &&
44 "Register enum value mismatch!");
45 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
47 if (!Namespace.empty())
50 const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
51 if (!SubRegIndices.empty()) {
52 OS << "\n// Subregister indices\n";
53 Namespace = SubRegIndices[0]->getValueAsString("Namespace");
54 if (!Namespace.empty())
55 OS << "namespace " << Namespace << " {\n";
56 OS << "enum {\n NoSubRegister,\n";
57 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
58 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
59 OS << " NUM_TARGET_SUBREGS = " << SubRegIndices.size()+1 << "\n";
61 if (!Namespace.empty())
64 OS << "} // End llvm namespace \n";
67 void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
68 EmitSourceFileHeader("Register Information Header Fragment", OS);
69 CodeGenTarget Target(Records);
70 const std::string &TargetName = Target.getName();
71 std::string ClassName = TargetName + "GenRegisterInfo";
73 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
74 OS << "#include <string>\n\n";
76 OS << "namespace llvm {\n\n";
78 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
79 << " explicit " << ClassName
80 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
81 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
82 << "unsigned Flavour) const;\n"
83 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
84 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
85 << " { return false; }\n"
86 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
87 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
88 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
91 const std::vector<CodeGenRegisterClass> &RegisterClasses =
92 Target.getRegisterClasses();
94 if (!RegisterClasses.empty()) {
95 OS << "namespace " << RegisterClasses[0].Namespace
96 << " { // Register classes\n";
99 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
101 OS << " " << RegisterClasses[i].getName() << "RegClassID";
106 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
107 const std::string &Name = RegisterClasses[i].getName();
109 // Output the register class definition.
110 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
111 << " " << Name << "Class();\n"
112 << RegisterClasses[i].MethodProtos << " };\n";
114 // Output the extern for the instance.
115 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
116 // Output the extern for the pointer to the instance (should remove).
117 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
118 << Name << "RegClass;\n";
120 OS << "} // end of namespace " << TargetName << "\n\n";
122 OS << "} // End llvm namespace \n";
125 static void addSuperReg(Record *R, Record *S,
126 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
127 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
128 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
130 errs() << "Error: recursive sub-register relationship between"
131 << " register " << getQualifiedName(R)
132 << " and its sub-registers?\n";
135 if (!SuperRegs[R].insert(S).second)
137 SubRegs[S].insert(R);
138 Aliases[R].insert(S);
139 Aliases[S].insert(R);
140 if (SuperRegs.count(S))
141 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
142 E = SuperRegs[S].end(); I != E; ++I)
143 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
146 static void addSubSuperReg(Record *R, Record *S,
147 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
148 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
149 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
151 errs() << "Error: recursive sub-register relationship between"
152 << " register " << getQualifiedName(R)
153 << " and its sub-registers?\n";
157 if (!SubRegs[R].insert(S).second)
159 addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
160 Aliases[R].insert(S);
161 Aliases[S].insert(R);
162 if (SubRegs.count(S))
163 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
164 E = SubRegs[S].end(); I != E; ++I)
165 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
168 struct RegisterMaps {
169 // Map SubRegIndex -> Register
170 typedef std::map<Record*, Record*, LessRecord> SubRegMap;
171 // Map Register -> SubRegMap
172 typedef std::map<Record*, SubRegMap> SubRegMaps;
175 SubRegMap &inferSubRegIndices(Record *Reg);
177 // Composite SubRegIndex instances.
178 // Map (SubRegIndex,SubRegIndex) -> SubRegIndex
179 typedef DenseMap<std::pair<Record*,Record*>,Record*> CompositeMap;
180 CompositeMap Composite;
182 // Compute SubRegIndex compositions after inferSubRegIndices has run on all
184 void computeComposites();
187 // Calculate all subregindices for Reg. Loopy subregs cause infinite recursion.
188 RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg) {
189 SubRegMap &SRM = SubReg[Reg];
192 std::vector<Record*> SubRegs = Reg->getValueAsListOfDefs("SubRegs");
193 std::vector<Record*> Indices = Reg->getValueAsListOfDefs("SubRegIndices");
194 if (SubRegs.size() != Indices.size())
195 throw "Register " + Reg->getName() + " SubRegIndices doesn't match SubRegs";
197 // First insert the direct subregs and make sure they are fully indexed.
198 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
199 if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second)
200 throw "SubRegIndex " + Indices[i]->getName()
201 + " appears twice in Register " + Reg->getName();
202 inferSubRegIndices(SubRegs[i]);
205 // Keep track of inherited subregs and how they can be reached.
206 // Register -> (SubRegIndex, SubRegIndex)
207 typedef std::map<Record*, std::pair<Record*,Record*>, LessRecord> OrphanMap;
210 // Clone inherited subregs. Here the order is important - earlier subregs take
212 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
213 SubRegMap &M = SubReg[SubRegs[i]];
214 for (SubRegMap::iterator si = M.begin(), se = M.end(); si != se; ++si)
215 if (!SRM.insert(*si).second)
216 Orphans[si->second] = std::make_pair(Indices[i], si->first);
219 // Finally process the composites.
220 ListInit *Comps = Reg->getValueAsListInit("CompositeIndices");
221 for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
222 DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
224 throw "Invalid dag '" + Comps->getElement(i)->getAsString()
225 + "' in CompositeIndices";
226 DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
227 if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
228 throw "Invalid SubClassIndex in " + Pat->getAsString();
230 // Resolve list of subreg indices into R2.
232 for (DagInit::const_arg_iterator di = Pat->arg_begin(),
233 de = Pat->arg_end(); di != de; ++di) {
234 DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
235 if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
236 throw "Invalid SubClassIndex in " + Pat->getAsString();
237 SubRegMap::const_iterator ni = SubReg[R2].find(IdxInit->getDef());
238 if (ni == SubReg[R2].end())
239 throw "Composite " + Pat->getAsString() + " refers to bad index in "
244 // Insert composite index. Allow overriding inherited indices etc.
245 SRM[BaseIdxInit->getDef()] = R2;
247 // R2 is now directly addressable, no longer an orphan.
251 // Now, Orphans contains the inherited subregisters without a direct index.
252 if (!Orphans.empty()) {
253 errs() << "Error: Register " << getQualifiedName(Reg)
254 << " inherited subregisters without an index:\n";
255 for (OrphanMap::iterator i = Orphans.begin(), e = Orphans.end(); i != e;
257 errs() << " " << getQualifiedName(i->first)
258 << " = " << i->second.first->getName()
259 << ", " << i->second.second->getName() << "\n";
266 void RegisterMaps::computeComposites() {
267 for (SubRegMaps::const_iterator sri = SubReg.begin(), sre = SubReg.end();
269 Record *Reg1 = sri->first;
270 const SubRegMap &SRM1 = sri->second;
271 for (SubRegMap::const_iterator i1 = SRM1.begin(), e1 = SRM1.end();
273 Record *Idx1 = i1->first;
274 Record *Reg2 = i1->second;
275 // Ignore identity compositions.
278 // If Reg2 has no subregs, Idx1 doesn't compose.
279 if (!SubReg.count(Reg2))
281 const SubRegMap &SRM2 = SubReg[Reg2];
282 // Try composing Idx1 with another SubRegIndex.
283 for (SubRegMap::const_iterator i2 = SRM2.begin(), e2 = SRM2.end();
285 std::pair<Record*,Record*> IdxPair(Idx1, i2->first);
286 Record *Reg3 = i2->second;
287 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
288 for (SubRegMap::const_iterator i1d = SRM1.begin(), e1d = SRM1.end();
290 // Ignore identity compositions.
293 if (i1d->second == Reg3) {
294 std::pair<CompositeMap::iterator,bool> Ins =
295 Composite.insert(std::make_pair(IdxPair, i1d->first));
296 // Conflicting composition?
297 if (!Ins.second && Ins.first->second != i1d->first) {
298 errs() << "Error: SubRegIndex " << getQualifiedName(Idx1)
299 << " and " << getQualifiedName(IdxPair.second)
300 << " compose ambiguously as "
301 << getQualifiedName(Ins.first->second) << " or "
302 << getQualifiedName(i1d->first) << "\n";
311 // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
312 // compositions, so remove any mappings of that form.
313 for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
315 CompositeMap::iterator j = i;
317 if (j->first.second == j->second)
322 class RegisterSorter {
324 std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
327 RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
328 : RegisterSubRegs(RS) {}
330 bool operator()(Record *RegA, Record *RegB) {
331 // B is sub-register of A.
332 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
336 // RegisterInfoEmitter::run - Main register file description emitter.
338 void RegisterInfoEmitter::run(raw_ostream &OS) {
339 CodeGenTarget Target(Records);
340 EmitSourceFileHeader("Register Information Source Fragment", OS);
342 OS << "namespace llvm {\n\n";
344 // Start out by emitting each of the register classes... to do this, we build
345 // a set of registers which belong to a register class, this is to ensure that
346 // each register is only in a single register class.
348 const std::vector<CodeGenRegisterClass> &RegisterClasses =
349 Target.getRegisterClasses();
351 // Loop over all of the register classes... emitting each one.
352 OS << "namespace { // Register classes...\n";
354 // RegClassesBelongedTo - Keep track of which register classes each reg
356 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
358 // Emit the register enum value arrays for each RegisterClass
359 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
360 const CodeGenRegisterClass &RC = RegisterClasses[rc];
362 // Give the register class a legal C name if it's anonymous.
363 std::string Name = RC.TheDef->getName();
365 // Emit the register list now.
366 OS << " // " << Name << " Register Class...\n"
367 << " static const unsigned " << Name
369 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
370 Record *Reg = RC.Elements[i];
371 OS << getQualifiedName(Reg) << ", ";
373 // Keep track of which regclasses this register is in.
374 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
379 // Emit the ValueType arrays for each RegisterClass
380 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
381 const CodeGenRegisterClass &RC = RegisterClasses[rc];
383 // Give the register class a legal C name if it's anonymous.
384 std::string Name = RC.TheDef->getName() + "VTs";
386 // Emit the register list now.
388 << " Register Class Value Types...\n"
389 << " static const EVT " << Name
391 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
392 OS << getEnumName(RC.VTs[i]) << ", ";
393 OS << "MVT::Other\n };\n\n";
395 OS << "} // end anonymous namespace\n\n";
397 // Now that all of the structs have been emitted, emit the instances.
398 if (!RegisterClasses.empty()) {
399 OS << "namespace " << RegisterClasses[0].Namespace
400 << " { // Register class instances\n";
401 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
402 OS << " " << RegisterClasses[i].getName() << "Class\t"
403 << RegisterClasses[i].getName() << "RegClass;\n";
405 std::map<unsigned, std::set<unsigned> > SuperClassMap;
406 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
409 unsigned NumSubRegIndices = Target.getSubRegIndices().size();
411 if (NumSubRegIndices) {
412 // Emit the sub-register classes for each RegisterClass
413 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
414 const CodeGenRegisterClass &RC = RegisterClasses[rc];
415 std::vector<Record*> SRC(NumSubRegIndices);
416 for (DenseMap<Record*,Record*>::const_iterator
417 i = RC.SubRegClasses.begin(),
418 e = RC.SubRegClasses.end(); i != e; ++i) {
420 unsigned idx = Target.getSubRegIndexNo(i->first);
421 SRC.at(idx-1) = i->second;
423 // Find the register class number of i->second for SuperRegClassMap.
424 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
425 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
426 if (RC2.TheDef == i->second) {
427 SuperRegClassMap[rc2].insert(rc);
433 // Give the register class a legal C name if it's anonymous.
434 std::string Name = RC.TheDef->getName();
437 << " Sub-register Classes...\n"
438 << " static const TargetRegisterClass* const "
439 << Name << "SubRegClasses[] = {\n ";
441 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
445 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
452 // Emit the super-register classes for each RegisterClass
453 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
454 const CodeGenRegisterClass &RC = RegisterClasses[rc];
456 // Give the register class a legal C name if it's anonymous.
457 std::string Name = RC.TheDef->getName();
460 << " Super-register Classes...\n"
461 << " static const TargetRegisterClass* const "
462 << Name << "SuperRegClasses[] = {\n ";
465 std::map<unsigned, std::set<unsigned> >::iterator I =
466 SuperRegClassMap.find(rc);
467 if (I != SuperRegClassMap.end()) {
468 for (std::set<unsigned>::iterator II = I->second.begin(),
469 EE = I->second.end(); II != EE; ++II) {
470 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
473 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
478 OS << (!Empty ? ", " : "") << "NULL";
482 // No subregindices in this target
483 OS << " static const TargetRegisterClass* const "
484 << "NullRegClasses[] = { NULL };\n\n";
487 // Emit the sub-classes array for each RegisterClass
488 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
489 const CodeGenRegisterClass &RC = RegisterClasses[rc];
491 // Give the register class a legal C name if it's anonymous.
492 std::string Name = RC.TheDef->getName();
495 << " Register Class sub-classes...\n"
496 << " static const TargetRegisterClass* const "
497 << Name << "Subclasses[] = {\n ";
500 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
501 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
503 // Sub-classes are used to determine if a virtual register can be used
504 // as an instruction operand, or if it must be copied first.
505 if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
507 if (!Empty) OS << ", ";
508 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
511 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
512 SuperClassMap.find(rc2);
513 if (SCMI == SuperClassMap.end()) {
514 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
515 SCMI = SuperClassMap.find(rc2);
517 SCMI->second.insert(rc);
520 OS << (!Empty ? ", " : "") << "NULL";
524 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
525 const CodeGenRegisterClass &RC = RegisterClasses[rc];
527 // Give the register class a legal C name if it's anonymous.
528 std::string Name = RC.TheDef->getName();
531 << " Register Class super-classes...\n"
532 << " static const TargetRegisterClass* const "
533 << Name << "Superclasses[] = {\n ";
536 std::map<unsigned, std::set<unsigned> >::iterator I =
537 SuperClassMap.find(rc);
538 if (I != SuperClassMap.end()) {
539 for (std::set<unsigned>::iterator II = I->second.begin(),
540 EE = I->second.end(); II != EE; ++II) {
541 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
542 if (!Empty) OS << ", ";
543 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
548 OS << (!Empty ? ", " : "") << "NULL";
553 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
554 const CodeGenRegisterClass &RC = RegisterClasses[i];
555 OS << RC.MethodBodies << "\n";
556 OS << RC.getName() << "Class::" << RC.getName()
557 << "Class() : TargetRegisterClass("
558 << RC.getName() + "RegClassID" << ", "
559 << '\"' << RC.getName() << "\", "
560 << RC.getName() + "VTs" << ", "
561 << RC.getName() + "Subclasses" << ", "
562 << RC.getName() + "Superclasses" << ", "
563 << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
565 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
567 << RC.SpillSize/8 << ", "
568 << RC.SpillAlignment/8 << ", "
569 << RC.CopyCost << ", "
570 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
577 OS << "\nnamespace {\n";
578 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
579 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
580 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
584 // Emit register sub-registers / super-registers, aliases...
585 std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
586 std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
587 std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
588 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
589 DwarfRegNumsMapTy DwarfRegNums;
591 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
593 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
594 Record *R = Regs[i].TheDef;
595 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
596 // Add information that R aliases all of the elements in the list... and
597 // that everything in the list aliases R.
598 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
600 if (RegisterAliases[R].count(Reg))
601 errs() << "Warning: register alias between " << getQualifiedName(R)
602 << " and " << getQualifiedName(Reg)
603 << " specified multiple times!\n";
604 RegisterAliases[R].insert(Reg);
606 if (RegisterAliases[Reg].count(R))
607 errs() << "Warning: register alias between " << getQualifiedName(R)
608 << " and " << getQualifiedName(Reg)
609 << " specified multiple times!\n";
610 RegisterAliases[Reg].insert(R);
614 // Process sub-register sets.
615 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
616 Record *R = Regs[i].TheDef;
617 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
618 // Process sub-register set and add aliases information.
619 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
620 Record *SubReg = LI[j];
621 if (RegisterSubRegs[R].count(SubReg))
622 errs() << "Warning: register " << getQualifiedName(SubReg)
623 << " specified as a sub-register of " << getQualifiedName(R)
624 << " multiple times!\n";
625 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
630 // Print the SubregHashTable, a simple quadratically probed
631 // hash table for determining if a register is a subregister
632 // of another register.
633 unsigned NumSubRegs = 0;
634 std::map<Record*, unsigned> RegNo;
635 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
636 RegNo[Regs[i].TheDef] = i;
637 NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size();
640 unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs);
641 unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize];
642 std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U);
644 unsigned hashMisses = 0;
646 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
647 Record* R = Regs[i].TheDef;
648 for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(),
649 E = RegisterSubRegs[R].end(); I != E; ++I) {
651 // We have to increase the indices of both registers by one when
652 // computing the hash because, in the generated code, there
653 // will be an extra empty slot at register 0.
654 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1);
655 unsigned ProbeAmt = 2;
656 while (SubregHashTable[index*2] != ~0U &&
657 SubregHashTable[index*2+1] != ~0U) {
658 index = (index + ProbeAmt) & (SubregHashTableSize-1);
664 SubregHashTable[index*2] = i;
665 SubregHashTable[index*2+1] = RegNo[RJ];
669 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
671 if (SubregHashTableSize) {
672 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
674 OS << " const unsigned SubregHashTable[] = { ";
675 for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) {
677 // Insert spaces for nice formatting.
680 if (SubregHashTable[2*i] != ~0U) {
681 OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", "
682 << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n";
684 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
688 unsigned Idx = SubregHashTableSize*2-2;
689 if (SubregHashTable[Idx] != ~0U) {
691 << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", "
692 << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n";
694 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
697 OS << " const unsigned SubregHashTableSize = "
698 << SubregHashTableSize << ";\n";
700 OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
701 << " const unsigned SubregHashTableSize = 1;\n";
704 delete [] SubregHashTable;
707 // Print the AliasHashTable, a simple quadratically probed
708 // hash table for determining if a register aliases another register.
709 unsigned NumAliases = 0;
711 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
712 RegNo[Regs[i].TheDef] = i;
713 NumAliases += RegisterAliases[Regs[i].TheDef].size();
716 unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases);
717 unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize];
718 std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U);
722 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
723 Record* R = Regs[i].TheDef;
724 for (std::set<Record*>::iterator I = RegisterAliases[R].begin(),
725 E = RegisterAliases[R].end(); I != E; ++I) {
727 // We have to increase the indices of both registers by one when
728 // computing the hash because, in the generated code, there
729 // will be an extra empty slot at register 0.
730 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1);
731 unsigned ProbeAmt = 2;
732 while (AliasesHashTable[index*2] != ~0U &&
733 AliasesHashTable[index*2+1] != ~0U) {
734 index = (index + ProbeAmt) & (AliasesHashTableSize-1);
740 AliasesHashTable[index*2] = i;
741 AliasesHashTable[index*2+1] = RegNo[RJ];
745 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
747 if (AliasesHashTableSize) {
748 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
750 OS << " const unsigned AliasesHashTable[] = { ";
751 for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) {
753 // Insert spaces for nice formatting.
756 if (AliasesHashTable[2*i] != ~0U) {
757 OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", "
758 << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n";
760 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
764 unsigned Idx = AliasesHashTableSize*2-2;
765 if (AliasesHashTable[Idx] != ~0U) {
767 << getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", "
768 << getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n";
770 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
773 OS << " const unsigned AliasesHashTableSize = "
774 << AliasesHashTableSize << ";\n";
776 OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
777 << " const unsigned AliasesHashTableSize = 1;\n";
780 delete [] AliasesHashTable;
782 if (!RegisterAliases.empty())
783 OS << "\n\n // Register Overlap Lists...\n";
785 // Emit an overlap list for all registers.
786 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
787 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
788 OS << " const unsigned " << I->first->getName() << "_Overlaps[] = { "
789 << getQualifiedName(I->first) << ", ";
790 for (std::set<Record*>::iterator ASI = I->second.begin(),
791 E = I->second.end(); ASI != E; ++ASI)
792 OS << getQualifiedName(*ASI) << ", ";
796 if (!RegisterSubRegs.empty())
797 OS << "\n\n // Register Sub-registers Sets...\n";
799 // Emit the empty sub-registers list
800 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
801 // Loop over all of the registers which have sub-registers, emitting the
802 // sub-registers list to memory.
803 for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
804 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
805 if (I->second.empty())
807 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
808 std::vector<Record*> SubRegsVector;
809 for (std::set<Record*>::iterator ASI = I->second.begin(),
810 E = I->second.end(); ASI != E; ++ASI)
811 SubRegsVector.push_back(*ASI);
812 RegisterSorter RS(RegisterSubRegs);
813 std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
814 for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
815 OS << getQualifiedName(SubRegsVector[i]) << ", ";
819 if (!RegisterSuperRegs.empty())
820 OS << "\n\n // Register Super-registers Sets...\n";
822 // Emit the empty super-registers list
823 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
824 // Loop over all of the registers which have super-registers, emitting the
825 // super-registers list to memory.
826 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
827 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
828 if (I->second.empty())
830 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
832 std::vector<Record*> SuperRegsVector;
833 for (std::set<Record*>::iterator ASI = I->second.begin(),
834 E = I->second.end(); ASI != E; ++ASI)
835 SuperRegsVector.push_back(*ASI);
836 RegisterSorter RS(RegisterSubRegs);
837 std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
838 for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
839 OS << getQualifiedName(SuperRegsVector[i]) << ", ";
843 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
844 OS << " { \"NOREG\",\t0,\t0,\t0,\t0 },\n";
846 // Now that register alias and sub-registers sets have been emitted, emit the
847 // register descriptors now.
848 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
849 const CodeGenRegister &Reg = Regs[i];
851 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
852 if (!RegisterSubRegs[Reg.TheDef].empty())
853 OS << Reg.getName() << "_SubRegsSet,\t";
855 OS << "Empty_SubRegsSet,\t";
856 if (!RegisterSuperRegs[Reg.TheDef].empty())
857 OS << Reg.getName() << "_SuperRegsSet,\t";
859 OS << "Empty_SuperRegsSet,\t";
860 OS << Reg.CostPerUse << " },\n";
862 OS << " };\n"; // End of register descriptors...
864 // Emit SubRegIndex names, skipping 0
865 const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
866 OS << "\n const char *const SubRegIndexTable[] = { \"";
867 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
868 OS << SubRegIndices[i]->getName();
873 OS << "}\n\n"; // End of anonymous namespace...
875 std::string ClassName = Target.getName() + "GenRegisterInfo";
877 // Calculate the mapping of subregister+index pairs to physical registers.
878 RegisterMaps RegMaps;
880 // Emit the subregister + index mapping function based on the information
882 OS << "unsigned " << ClassName
883 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
884 << " switch (RegNo) {\n"
885 << " default:\n return 0;\n";
886 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
887 RegisterMaps::SubRegMap &SRM = RegMaps.inferSubRegIndices(Regs[i].TheDef);
890 OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
891 OS << " switch (Index) {\n";
892 OS << " default: return 0;\n";
893 for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
894 ie = SRM.end(); ii != ie; ++ii)
895 OS << " case " << getQualifiedName(ii->first)
896 << ": return " << getQualifiedName(ii->second) << ";\n";
897 OS << " };\n" << " break;\n";
900 OS << " return 0;\n";
903 OS << "unsigned " << ClassName
904 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
905 << " switch (RegNo) {\n"
906 << " default:\n return 0;\n";
907 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
908 RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef];
911 OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
912 for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
913 ie = SRM.end(); ii != ie; ++ii)
914 OS << " if (SubRegNo == " << getQualifiedName(ii->second)
915 << ") return " << getQualifiedName(ii->first) << ";\n";
916 OS << " return 0;\n";
919 OS << " return 0;\n";
922 // Emit composeSubRegIndices
923 RegMaps.computeComposites();
924 OS << "unsigned " << ClassName
925 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
926 << " switch (IdxA) {\n"
927 << " default:\n return IdxB;\n";
928 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
930 for (unsigned j = 0; j != e; ++j) {
931 if (Record *Comp = RegMaps.Composite.lookup(
932 std::make_pair(SubRegIndices[i], SubRegIndices[j]))) {
934 OS << " case " << getQualifiedName(SubRegIndices[i])
935 << ": switch(IdxB) {\n default: return IdxB;\n";
938 OS << " case " << getQualifiedName(SubRegIndices[j])
939 << ": return " << getQualifiedName(Comp) << ";\n";
947 // Emit the constructor of the class...
948 OS << ClassName << "::" << ClassName
949 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
950 << " : TargetRegisterInfo(RegisterDescriptors, " << Regs.size()+1
951 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
952 << " SubRegIndexTable,\n"
953 << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
954 << " SubregHashTable, SubregHashTableSize,\n"
955 << " AliasesHashTable, AliasesHashTableSize) {\n"
958 // Collect all information about dwarf register numbers
960 // First, just pull all provided information to the map
961 unsigned maxLength = 0;
962 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
963 Record *Reg = Regs[i].TheDef;
964 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
965 maxLength = std::max((size_t)maxLength, RegNums.size());
966 if (DwarfRegNums.count(Reg))
967 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
968 << "specified multiple times\n";
969 DwarfRegNums[Reg] = RegNums;
972 // Now we know maximal length of number list. Append -1's, where needed
973 for (DwarfRegNumsMapTy::iterator
974 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
975 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
976 I->second.push_back(-1);
978 // Emit information about the dwarf register numbers.
979 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
980 << "unsigned Flavour) const {\n"
981 << " switch (Flavour) {\n"
983 << " assert(0 && \"Unknown DWARF flavour\");\n"
986 for (unsigned i = 0, e = maxLength; i != e; ++i) {
987 OS << " case " << i << ":\n"
988 << " switch (RegNum) {\n"
990 << " assert(0 && \"Invalid RegNum\");\n"
993 // Sort by name to get a stable order.
996 for (DwarfRegNumsMapTy::iterator
997 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
998 int RegNo = I->second[i];
1000 OS << " case " << getQualifiedName(I->first) << ":\n"
1001 << " return " << RegNo << ";\n";
1003 OS << " case " << getQualifiedName(I->first) << ":\n"
1004 << " assert(0 && \"Invalid register for this mode\");\n"
1012 OS << "} // End llvm namespace \n";