1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
26 // runEnums - Print out enum values for all of the registers.
27 void RegisterInfoEmitter::runEnums(raw_ostream &OS) {
28 CodeGenTarget Target(Records);
29 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
31 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
33 EmitSourceFileHeader("Target Register Enum Values", OS);
34 OS << "namespace llvm {\n\n";
36 if (!Namespace.empty())
37 OS << "namespace " << Namespace << " {\n";
38 OS << "enum {\n NoRegister,\n";
40 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
41 OS << " " << Registers[i].getName() << " = " <<
42 Registers[i].EnumValue << ",\n";
43 assert(Registers.size() == Registers[Registers.size()-1].EnumValue &&
44 "Register enum value mismatch!");
45 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
47 if (!Namespace.empty())
50 const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
51 if (!SubRegIndices.empty()) {
52 OS << "\n// Subregister indices\n";
53 Namespace = SubRegIndices[0]->getValueAsString("Namespace");
54 if (!Namespace.empty())
55 OS << "namespace " << Namespace << " {\n";
56 OS << "enum {\n NoSubRegister,\n";
57 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i)
58 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
59 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
61 if (!Namespace.empty())
64 OS << "} // End llvm namespace \n";
67 void RegisterInfoEmitter::runHeader(raw_ostream &OS) {
68 EmitSourceFileHeader("Register Information Header Fragment", OS);
69 CodeGenTarget Target(Records);
70 const std::string &TargetName = Target.getName();
71 std::string ClassName = TargetName + "GenRegisterInfo";
73 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
74 OS << "#include <string>\n\n";
76 OS << "namespace llvm {\n\n";
78 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
79 << " explicit " << ClassName
80 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
81 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
82 << "unsigned Flavour) const;\n"
83 << " virtual int getLLVMRegNumFull(unsigned DwarfRegNum, "
84 << "unsigned Flavour) const;\n"
85 << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n"
86 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
87 << " { return false; }\n"
88 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
89 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
90 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
93 const std::vector<CodeGenRegisterClass> &RegisterClasses =
94 Target.getRegisterClasses();
96 if (!RegisterClasses.empty()) {
97 OS << "namespace " << RegisterClasses[0].Namespace
98 << " { // Register classes\n";
101 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
103 OS << " " << RegisterClasses[i].getName() << "RegClassID";
108 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
109 const std::string &Name = RegisterClasses[i].getName();
111 // Output the register class definition.
112 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
113 << " " << Name << "Class();\n"
114 << RegisterClasses[i].MethodProtos << " };\n";
116 // Output the extern for the instance.
117 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
118 // Output the extern for the pointer to the instance (should remove).
119 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
120 << Name << "RegClass;\n";
122 OS << "} // end of namespace " << TargetName << "\n\n";
124 OS << "} // End llvm namespace \n";
127 static void addSuperReg(Record *R, Record *S,
128 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
129 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
130 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
132 errs() << "Error: recursive sub-register relationship between"
133 << " register " << getQualifiedName(R)
134 << " and its sub-registers?\n";
137 if (!SuperRegs[R].insert(S).second)
139 SubRegs[S].insert(R);
140 Aliases[R].insert(S);
141 Aliases[S].insert(R);
142 if (SuperRegs.count(S))
143 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
144 E = SuperRegs[S].end(); I != E; ++I)
145 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
148 static void addSubSuperReg(Record *R, Record *S,
149 std::map<Record*, std::set<Record*>, LessRecord> &SubRegs,
150 std::map<Record*, std::set<Record*>, LessRecord> &SuperRegs,
151 std::map<Record*, std::set<Record*>, LessRecord> &Aliases) {
153 errs() << "Error: recursive sub-register relationship between"
154 << " register " << getQualifiedName(R)
155 << " and its sub-registers?\n";
159 if (!SubRegs[R].insert(S).second)
161 addSuperReg(S, R, SubRegs, SuperRegs, Aliases);
162 Aliases[R].insert(S);
163 Aliases[S].insert(R);
164 if (SubRegs.count(S))
165 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
166 E = SubRegs[S].end(); I != E; ++I)
167 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases);
170 struct RegisterMaps {
171 // Map SubRegIndex -> Register
172 typedef std::map<Record*, Record*, LessRecord> SubRegMap;
173 // Map Register -> SubRegMap
174 typedef std::map<Record*, SubRegMap> SubRegMaps;
177 SubRegMap &inferSubRegIndices(Record *Reg, CodeGenTarget &);
179 // Composite SubRegIndex instances.
180 // Map (SubRegIndex,SubRegIndex) -> SubRegIndex
181 typedef DenseMap<std::pair<Record*,Record*>,Record*> CompositeMap;
182 CompositeMap Composite;
184 // Compute SubRegIndex compositions after inferSubRegIndices has run on all
186 void computeComposites();
189 // Calculate all subregindices for Reg. Loopy subregs cause infinite recursion.
190 RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg,
191 CodeGenTarget &Target) {
192 SubRegMap &SRM = SubReg[Reg];
195 std::vector<Record*> SubRegs = Reg->getValueAsListOfDefs("SubRegs");
196 std::vector<Record*> Indices = Reg->getValueAsListOfDefs("SubRegIndices");
197 if (SubRegs.size() != Indices.size())
198 throw "Register " + Reg->getName() + " SubRegIndices doesn't match SubRegs";
200 // First insert the direct subregs and make sure they are fully indexed.
201 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
202 if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second)
203 throw "SubRegIndex " + Indices[i]->getName()
204 + " appears twice in Register " + Reg->getName();
205 inferSubRegIndices(SubRegs[i], Target);
208 // Keep track of inherited subregs and how they can be reached.
209 // Register -> (SubRegIndex, SubRegIndex)
210 typedef std::map<Record*, std::pair<Record*,Record*>, LessRecord> OrphanMap;
213 // Clone inherited subregs. Here the order is important - earlier subregs take
215 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
216 SubRegMap &M = SubReg[SubRegs[i]];
217 for (SubRegMap::iterator si = M.begin(), se = M.end(); si != se; ++si)
218 if (!SRM.insert(*si).second)
219 Orphans[si->second] = std::make_pair(Indices[i], si->first);
222 // Finally process the composites.
223 ListInit *Comps = Reg->getValueAsListInit("CompositeIndices");
224 for (unsigned i = 0, e = Comps->size(); i != e; ++i) {
225 DagInit *Pat = dynamic_cast<DagInit*>(Comps->getElement(i));
227 throw "Invalid dag '" + Comps->getElement(i)->getAsString()
228 + "' in CompositeIndices";
229 DefInit *BaseIdxInit = dynamic_cast<DefInit*>(Pat->getOperator());
230 if (!BaseIdxInit || !BaseIdxInit->getDef()->isSubClassOf("SubRegIndex"))
231 throw "Invalid SubClassIndex in " + Pat->getAsString();
233 // Resolve list of subreg indices into R2.
235 for (DagInit::const_arg_iterator di = Pat->arg_begin(),
236 de = Pat->arg_end(); di != de; ++di) {
237 DefInit *IdxInit = dynamic_cast<DefInit*>(*di);
238 if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex"))
239 throw "Invalid SubClassIndex in " + Pat->getAsString();
240 SubRegMap::const_iterator ni = SubReg[R2].find(IdxInit->getDef());
241 if (ni == SubReg[R2].end())
242 throw "Composite " + Pat->getAsString() + " refers to bad index in "
247 // Insert composite index. Allow overriding inherited indices etc.
248 SRM[BaseIdxInit->getDef()] = R2;
250 // R2 is now directly addressable, no longer an orphan.
254 // Now Orphans contains the inherited subregisters without a direct index.
255 // Create inferred indexes for all missing entries.
256 for (OrphanMap::iterator I = Orphans.begin(), E = Orphans.end(); I != E;
258 Record *&Comp = Composite[I->second];
260 Comp = Target.createSubRegIndex(I->second.first->getName() + "_then_" +
261 I->second.second->getName());
262 SRM[Comp] = I->first;
268 void RegisterMaps::computeComposites() {
269 for (SubRegMaps::const_iterator sri = SubReg.begin(), sre = SubReg.end();
271 Record *Reg1 = sri->first;
272 const SubRegMap &SRM1 = sri->second;
273 for (SubRegMap::const_iterator i1 = SRM1.begin(), e1 = SRM1.end();
275 Record *Idx1 = i1->first;
276 Record *Reg2 = i1->second;
277 // Ignore identity compositions.
280 // If Reg2 has no subregs, Idx1 doesn't compose.
281 if (!SubReg.count(Reg2))
283 const SubRegMap &SRM2 = SubReg[Reg2];
284 // Try composing Idx1 with another SubRegIndex.
285 for (SubRegMap::const_iterator i2 = SRM2.begin(), e2 = SRM2.end();
287 std::pair<Record*,Record*> IdxPair(Idx1, i2->first);
288 Record *Reg3 = i2->second;
289 // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3.
290 for (SubRegMap::const_iterator i1d = SRM1.begin(), e1d = SRM1.end();
292 // Ignore identity compositions.
295 if (i1d->second == Reg3) {
296 std::pair<CompositeMap::iterator,bool> Ins =
297 Composite.insert(std::make_pair(IdxPair, i1d->first));
298 // Conflicting composition? Emit a warning but allow it.
299 if (!Ins.second && Ins.first->second != i1d->first) {
300 errs() << "Warning: SubRegIndex " << getQualifiedName(Idx1)
301 << " and " << getQualifiedName(IdxPair.second)
302 << " compose ambiguously as "
303 << getQualifiedName(Ins.first->second) << " or "
304 << getQualifiedName(i1d->first) << "\n";
312 // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid
313 // compositions, so remove any mappings of that form.
314 for (CompositeMap::iterator i = Composite.begin(), e = Composite.end();
316 CompositeMap::iterator j = i;
318 if (j->first.second == j->second)
323 class RegisterSorter {
325 std::map<Record*, std::set<Record*>, LessRecord> &RegisterSubRegs;
328 RegisterSorter(std::map<Record*, std::set<Record*>, LessRecord> &RS)
329 : RegisterSubRegs(RS) {}
331 bool operator()(Record *RegA, Record *RegB) {
332 // B is sub-register of A.
333 return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB);
337 // RegisterInfoEmitter::run - Main register file description emitter.
339 void RegisterInfoEmitter::run(raw_ostream &OS) {
340 CodeGenTarget Target(Records);
341 EmitSourceFileHeader("Register Information Source Fragment", OS);
343 OS << "namespace llvm {\n\n";
345 // Start out by emitting each of the register classes... to do this, we build
346 // a set of registers which belong to a register class, this is to ensure that
347 // each register is only in a single register class.
349 const std::vector<CodeGenRegisterClass> &RegisterClasses =
350 Target.getRegisterClasses();
352 // Loop over all of the register classes... emitting each one.
353 OS << "namespace { // Register classes...\n";
355 // RegClassesBelongedTo - Keep track of which register classes each reg
357 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
359 // Emit the register enum value arrays for each RegisterClass
360 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
361 const CodeGenRegisterClass &RC = RegisterClasses[rc];
363 // Give the register class a legal C name if it's anonymous.
364 std::string Name = RC.TheDef->getName();
366 // Emit the register list now.
367 OS << " // " << Name << " Register Class...\n"
368 << " static const unsigned " << Name
370 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
371 Record *Reg = RC.Elements[i];
372 OS << getQualifiedName(Reg) << ", ";
374 // Keep track of which regclasses this register is in.
375 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
380 // Emit the ValueType arrays for each RegisterClass
381 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
382 const CodeGenRegisterClass &RC = RegisterClasses[rc];
384 // Give the register class a legal C name if it's anonymous.
385 std::string Name = RC.TheDef->getName() + "VTs";
387 // Emit the register list now.
389 << " Register Class Value Types...\n"
390 << " static const EVT " << Name
392 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
393 OS << getEnumName(RC.VTs[i]) << ", ";
394 OS << "MVT::Other\n };\n\n";
396 OS << "} // end anonymous namespace\n\n";
398 // Now that all of the structs have been emitted, emit the instances.
399 if (!RegisterClasses.empty()) {
400 OS << "namespace " << RegisterClasses[0].Namespace
401 << " { // Register class instances\n";
402 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
403 OS << " " << RegisterClasses[i].getName() << "Class\t"
404 << RegisterClasses[i].getName() << "RegClass;\n";
406 std::map<unsigned, std::set<unsigned> > SuperClassMap;
407 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
410 unsigned NumSubRegIndices = Target.getSubRegIndices().size();
412 if (NumSubRegIndices) {
413 // Emit the sub-register classes for each RegisterClass
414 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
415 const CodeGenRegisterClass &RC = RegisterClasses[rc];
416 std::vector<Record*> SRC(NumSubRegIndices);
417 for (DenseMap<Record*,Record*>::const_iterator
418 i = RC.SubRegClasses.begin(),
419 e = RC.SubRegClasses.end(); i != e; ++i) {
421 unsigned idx = Target.getSubRegIndexNo(i->first);
422 SRC.at(idx-1) = i->second;
424 // Find the register class number of i->second for SuperRegClassMap.
425 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
426 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
427 if (RC2.TheDef == i->second) {
428 SuperRegClassMap[rc2].insert(rc);
434 // Give the register class a legal C name if it's anonymous.
435 std::string Name = RC.TheDef->getName();
438 << " Sub-register Classes...\n"
439 << " static const TargetRegisterClass* const "
440 << Name << "SubRegClasses[] = {\n ";
442 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
446 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
453 // Emit the super-register classes for each RegisterClass
454 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
455 const CodeGenRegisterClass &RC = RegisterClasses[rc];
457 // Give the register class a legal C name if it's anonymous.
458 std::string Name = RC.TheDef->getName();
461 << " Super-register Classes...\n"
462 << " static const TargetRegisterClass* const "
463 << Name << "SuperRegClasses[] = {\n ";
466 std::map<unsigned, std::set<unsigned> >::iterator I =
467 SuperRegClassMap.find(rc);
468 if (I != SuperRegClassMap.end()) {
469 for (std::set<unsigned>::iterator II = I->second.begin(),
470 EE = I->second.end(); II != EE; ++II) {
471 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
474 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
479 OS << (!Empty ? ", " : "") << "NULL";
483 // No subregindices in this target
484 OS << " static const TargetRegisterClass* const "
485 << "NullRegClasses[] = { NULL };\n\n";
488 // Emit the sub-classes array for each RegisterClass
489 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
490 const CodeGenRegisterClass &RC = RegisterClasses[rc];
492 // Give the register class a legal C name if it's anonymous.
493 std::string Name = RC.TheDef->getName();
496 << " Register Class sub-classes...\n"
497 << " static const TargetRegisterClass* const "
498 << Name << "Subclasses[] = {\n ";
501 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
502 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
504 // Sub-classes are used to determine if a virtual register can be used
505 // as an instruction operand, or if it must be copied first.
506 if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
508 if (!Empty) OS << ", ";
509 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
512 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
513 SuperClassMap.find(rc2);
514 if (SCMI == SuperClassMap.end()) {
515 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
516 SCMI = SuperClassMap.find(rc2);
518 SCMI->second.insert(rc);
521 OS << (!Empty ? ", " : "") << "NULL";
525 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
526 const CodeGenRegisterClass &RC = RegisterClasses[rc];
528 // Give the register class a legal C name if it's anonymous.
529 std::string Name = RC.TheDef->getName();
532 << " Register Class super-classes...\n"
533 << " static const TargetRegisterClass* const "
534 << Name << "Superclasses[] = {\n ";
537 std::map<unsigned, std::set<unsigned> >::iterator I =
538 SuperClassMap.find(rc);
539 if (I != SuperClassMap.end()) {
540 for (std::set<unsigned>::iterator II = I->second.begin(),
541 EE = I->second.end(); II != EE; ++II) {
542 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
543 if (!Empty) OS << ", ";
544 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
549 OS << (!Empty ? ", " : "") << "NULL";
554 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
555 const CodeGenRegisterClass &RC = RegisterClasses[i];
556 OS << RC.MethodBodies << "\n";
557 OS << RC.getName() << "Class::" << RC.getName()
558 << "Class() : TargetRegisterClass("
559 << RC.getName() + "RegClassID" << ", "
560 << '\"' << RC.getName() << "\", "
561 << RC.getName() + "VTs" << ", "
562 << RC.getName() + "Subclasses" << ", "
563 << RC.getName() + "Superclasses" << ", "
564 << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
566 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
568 << RC.SpillSize/8 << ", "
569 << RC.SpillAlignment/8 << ", "
570 << RC.CopyCost << ", "
571 << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size()
578 OS << "\nnamespace {\n";
579 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
580 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
581 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
585 // Emit register sub-registers / super-registers, aliases...
586 std::map<Record*, std::set<Record*>, LessRecord> RegisterSubRegs;
587 std::map<Record*, std::set<Record*>, LessRecord> RegisterSuperRegs;
588 std::map<Record*, std::set<Record*>, LessRecord> RegisterAliases;
589 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
590 DwarfRegNumsMapTy DwarfRegNums;
592 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
594 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
595 Record *R = Regs[i].TheDef;
596 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
597 // Add information that R aliases all of the elements in the list... and
598 // that everything in the list aliases R.
599 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
601 if (RegisterAliases[R].count(Reg))
602 errs() << "Warning: register alias between " << getQualifiedName(R)
603 << " and " << getQualifiedName(Reg)
604 << " specified multiple times!\n";
605 RegisterAliases[R].insert(Reg);
607 if (RegisterAliases[Reg].count(R))
608 errs() << "Warning: register alias between " << getQualifiedName(R)
609 << " and " << getQualifiedName(Reg)
610 << " specified multiple times!\n";
611 RegisterAliases[Reg].insert(R);
615 // Process sub-register sets.
616 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
617 Record *R = Regs[i].TheDef;
618 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
619 // Process sub-register set and add aliases information.
620 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
621 Record *SubReg = LI[j];
622 if (RegisterSubRegs[R].count(SubReg))
623 errs() << "Warning: register " << getQualifiedName(SubReg)
624 << " specified as a sub-register of " << getQualifiedName(R)
625 << " multiple times!\n";
626 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
631 // Print the SubregHashTable, a simple quadratically probed
632 // hash table for determining if a register is a subregister
633 // of another register.
634 unsigned NumSubRegs = 0;
635 std::map<Record*, unsigned> RegNo;
636 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
637 RegNo[Regs[i].TheDef] = i;
638 NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size();
641 unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs);
642 unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize];
643 std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U);
645 unsigned hashMisses = 0;
647 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
648 Record* R = Regs[i].TheDef;
649 for (std::set<Record*>::iterator I = RegisterSubRegs[R].begin(),
650 E = RegisterSubRegs[R].end(); I != E; ++I) {
652 // We have to increase the indices of both registers by one when
653 // computing the hash because, in the generated code, there
654 // will be an extra empty slot at register 0.
655 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1);
656 unsigned ProbeAmt = 2;
657 while (SubregHashTable[index*2] != ~0U &&
658 SubregHashTable[index*2+1] != ~0U) {
659 index = (index + ProbeAmt) & (SubregHashTableSize-1);
665 SubregHashTable[index*2] = i;
666 SubregHashTable[index*2+1] = RegNo[RJ];
670 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
672 if (SubregHashTableSize) {
673 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
675 OS << " const unsigned SubregHashTable[] = { ";
676 for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) {
678 // Insert spaces for nice formatting.
681 if (SubregHashTable[2*i] != ~0U) {
682 OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", "
683 << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n";
685 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
689 unsigned Idx = SubregHashTableSize*2-2;
690 if (SubregHashTable[Idx] != ~0U) {
692 << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", "
693 << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n";
695 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
698 OS << " const unsigned SubregHashTableSize = "
699 << SubregHashTableSize << ";\n";
701 OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n"
702 << " const unsigned SubregHashTableSize = 1;\n";
705 delete [] SubregHashTable;
708 // Print the AliasHashTable, a simple quadratically probed
709 // hash table for determining if a register aliases another register.
710 unsigned NumAliases = 0;
712 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
713 RegNo[Regs[i].TheDef] = i;
714 NumAliases += RegisterAliases[Regs[i].TheDef].size();
717 unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases);
718 unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize];
719 std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U);
723 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
724 Record* R = Regs[i].TheDef;
725 for (std::set<Record*>::iterator I = RegisterAliases[R].begin(),
726 E = RegisterAliases[R].end(); I != E; ++I) {
728 // We have to increase the indices of both registers by one when
729 // computing the hash because, in the generated code, there
730 // will be an extra empty slot at register 0.
731 size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (AliasesHashTableSize-1);
732 unsigned ProbeAmt = 2;
733 while (AliasesHashTable[index*2] != ~0U &&
734 AliasesHashTable[index*2+1] != ~0U) {
735 index = (index + ProbeAmt) & (AliasesHashTableSize-1);
741 AliasesHashTable[index*2] = i;
742 AliasesHashTable[index*2+1] = RegNo[RJ];
746 OS << "\n\n // Number of hash collisions: " << hashMisses << "\n";
748 if (AliasesHashTableSize) {
749 std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace");
751 OS << " const unsigned AliasesHashTable[] = { ";
752 for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) {
754 // Insert spaces for nice formatting.
757 if (AliasesHashTable[2*i] != ~0U) {
758 OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", "
759 << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n";
761 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n";
765 unsigned Idx = AliasesHashTableSize*2-2;
766 if (AliasesHashTable[Idx] != ~0U) {
768 << getQualifiedName(Regs[AliasesHashTable[Idx]].TheDef) << ", "
769 << getQualifiedName(Regs[AliasesHashTable[Idx+1]].TheDef) << " };\n";
771 OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n";
774 OS << " const unsigned AliasesHashTableSize = "
775 << AliasesHashTableSize << ";\n";
777 OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n"
778 << " const unsigned AliasesHashTableSize = 1;\n";
781 delete [] AliasesHashTable;
783 if (!RegisterAliases.empty())
784 OS << "\n\n // Register Overlap Lists...\n";
786 // Emit an overlap list for all registers.
787 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
788 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
789 OS << " const unsigned " << I->first->getName() << "_Overlaps[] = { "
790 << getQualifiedName(I->first) << ", ";
791 for (std::set<Record*>::iterator ASI = I->second.begin(),
792 E = I->second.end(); ASI != E; ++ASI)
793 OS << getQualifiedName(*ASI) << ", ";
797 if (!RegisterSubRegs.empty())
798 OS << "\n\n // Register Sub-registers Sets...\n";
800 // Emit the empty sub-registers list
801 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
802 // Loop over all of the registers which have sub-registers, emitting the
803 // sub-registers list to memory.
804 for (std::map<Record*, std::set<Record*>, LessRecord>::iterator
805 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
806 if (I->second.empty())
808 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
809 std::vector<Record*> SubRegsVector;
810 for (std::set<Record*>::iterator ASI = I->second.begin(),
811 E = I->second.end(); ASI != E; ++ASI)
812 SubRegsVector.push_back(*ASI);
813 RegisterSorter RS(RegisterSubRegs);
814 std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS);
815 for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i)
816 OS << getQualifiedName(SubRegsVector[i]) << ", ";
820 if (!RegisterSuperRegs.empty())
821 OS << "\n\n // Register Super-registers Sets...\n";
823 // Emit the empty super-registers list
824 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
825 // Loop over all of the registers which have super-registers, emitting the
826 // super-registers list to memory.
827 for (std::map<Record*, std::set<Record*>, LessRecord >::iterator
828 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
829 if (I->second.empty())
831 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
833 std::vector<Record*> SuperRegsVector;
834 for (std::set<Record*>::iterator ASI = I->second.begin(),
835 E = I->second.end(); ASI != E; ++ASI)
836 SuperRegsVector.push_back(*ASI);
837 RegisterSorter RS(RegisterSubRegs);
838 std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS);
839 for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i)
840 OS << getQualifiedName(SuperRegsVector[i]) << ", ";
844 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
845 OS << " { \"NOREG\",\t0,\t0,\t0,\t0 },\n";
847 // Now that register alias and sub-registers sets have been emitted, emit the
848 // register descriptors now.
849 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
850 const CodeGenRegister &Reg = Regs[i];
852 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
853 if (!RegisterSubRegs[Reg.TheDef].empty())
854 OS << Reg.getName() << "_SubRegsSet,\t";
856 OS << "Empty_SubRegsSet,\t";
857 if (!RegisterSuperRegs[Reg.TheDef].empty())
858 OS << Reg.getName() << "_SuperRegsSet,\t";
860 OS << "Empty_SuperRegsSet,\t";
861 OS << Reg.CostPerUse << " },\n";
863 OS << " };\n"; // End of register descriptors...
865 // Calculate the mapping of subregister+index pairs to physical registers.
866 // This will also create further anonymous indexes.
867 unsigned NamedIndices = Target.getSubRegIndices().size();
868 RegisterMaps RegMaps;
869 for (unsigned i = 0, e = Regs.size(); i != e; ++i)
870 RegMaps.inferSubRegIndices(Regs[i].TheDef, Target);
872 // Emit SubRegIndex names, skipping 0
873 const std::vector<Record*> SubRegIndices = Target.getSubRegIndices();
874 OS << "\n const char *const SubRegIndexTable[] = { \"";
875 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
876 OS << SubRegIndices[i]->getName();
882 // Emit names of the anonymus subreg indexes.
883 if (SubRegIndices.size() > NamedIndices) {
885 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
886 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
892 OS << "}\n\n"; // End of anonymous namespace...
894 std::string ClassName = Target.getName() + "GenRegisterInfo";
896 // Emit the subregister + index mapping function based on the information
898 OS << "unsigned " << ClassName
899 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
900 << " switch (RegNo) {\n"
901 << " default:\n return 0;\n";
902 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
903 RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef];
906 OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
907 OS << " switch (Index) {\n";
908 OS << " default: return 0;\n";
909 for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
910 ie = SRM.end(); ii != ie; ++ii)
911 OS << " case " << getQualifiedName(ii->first)
912 << ": return " << getQualifiedName(ii->second) << ";\n";
913 OS << " };\n" << " break;\n";
916 OS << " return 0;\n";
919 OS << "unsigned " << ClassName
920 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
921 << " switch (RegNo) {\n"
922 << " default:\n return 0;\n";
923 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
924 RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef];
927 OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n";
928 for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(),
929 ie = SRM.end(); ii != ie; ++ii)
930 OS << " if (SubRegNo == " << getQualifiedName(ii->second)
931 << ") return " << getQualifiedName(ii->first) << ";\n";
932 OS << " return 0;\n";
935 OS << " return 0;\n";
938 // Emit composeSubRegIndices
939 RegMaps.computeComposites();
940 OS << "unsigned " << ClassName
941 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
942 << " switch (IdxA) {\n"
943 << " default:\n return IdxB;\n";
944 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
946 for (unsigned j = 0; j != e; ++j) {
947 if (Record *Comp = RegMaps.Composite.lookup(
948 std::make_pair(SubRegIndices[i], SubRegIndices[j]))) {
950 OS << " case " << getQualifiedName(SubRegIndices[i])
951 << ": switch(IdxB) {\n default: return IdxB;\n";
954 OS << " case " << getQualifiedName(SubRegIndices[j])
955 << ": return " << getQualifiedName(Comp) << ";\n";
963 // Emit the constructor of the class...
964 OS << ClassName << "::" << ClassName
965 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
966 << " : TargetRegisterInfo(RegisterDescriptors, " << Regs.size()+1
967 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
968 << " SubRegIndexTable,\n"
969 << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n"
970 << " SubregHashTable, SubregHashTableSize,\n"
971 << " AliasesHashTable, AliasesHashTableSize) {\n"
974 // Collect all information about dwarf register numbers
976 // First, just pull all provided information to the map
977 unsigned maxLength = 0;
978 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
979 Record *Reg = Regs[i].TheDef;
980 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
981 maxLength = std::max((size_t)maxLength, RegNums.size());
982 if (DwarfRegNums.count(Reg))
983 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
984 << "specified multiple times\n";
985 DwarfRegNums[Reg] = RegNums;
988 // Now we know maximal length of number list. Append -1's, where needed
989 for (DwarfRegNumsMapTy::iterator
990 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
991 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
992 I->second.push_back(-1);
994 // Emit reverse information about the dwarf register numbers.
995 OS << "int " << ClassName << "::getLLVMRegNumFull(unsigned DwarfRegNum, "
996 << "unsigned Flavour) const {\n"
997 << " switch (Flavour) {\n"
999 << " assert(0 && \"Unknown DWARF flavour\");\n"
1002 for (unsigned i = 0, e = maxLength; i != e; ++i) {
1003 OS << " case " << i << ":\n"
1004 << " switch (DwarfRegNum) {\n"
1006 << " assert(0 && \"Invalid DwarfRegNum\");\n"
1009 for (DwarfRegNumsMapTy::iterator
1010 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
1011 int DwarfRegNo = I->second[i];
1012 if (DwarfRegNo >= 0)
1013 OS << " case " << DwarfRegNo << ":\n"
1014 << " return " << getQualifiedName(I->first) << ";\n";
1021 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
1022 Record *Reg = Regs[i].TheDef;
1023 const RecordVal *V = Reg->getValue("DwarfAlias");
1024 if (!V || !V->getValue())
1027 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
1028 Record *Alias = DI->getDef();
1029 DwarfRegNums[Reg] = DwarfRegNums[Alias];
1032 // Emit information about the dwarf register numbers.
1033 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
1034 << "unsigned Flavour) const {\n"
1035 << " switch (Flavour) {\n"
1037 << " assert(0 && \"Unknown DWARF flavour\");\n"
1040 for (unsigned i = 0, e = maxLength; i != e; ++i) {
1041 OS << " case " << i << ":\n"
1042 << " switch (RegNum) {\n"
1044 << " assert(0 && \"Invalid RegNum\");\n"
1047 // Sort by name to get a stable order.
1050 for (DwarfRegNumsMapTy::iterator
1051 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
1052 int RegNo = I->second[i];
1053 OS << " case " << getQualifiedName(I->first) << ":\n"
1054 << " return " << RegNo << ";\n";
1061 OS << "} // End llvm namespace \n";