1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Streams.h"
26 // runEnums - Print out enum values for all of the registers.
27 void RegisterInfoEmitter::runEnums(std::ostream &OS) {
29 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
31 std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace");
33 EmitSourceFileHeader("Target Register Enum Values", OS);
34 OS << "namespace llvm {\n\n";
36 if (!Namespace.empty())
37 OS << "namespace " << Namespace << " {\n";
38 OS << " enum {\n NoRegister,\n";
40 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
41 OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n";
42 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
44 if (!Namespace.empty())
46 OS << "} // End llvm namespace \n";
49 void RegisterInfoEmitter::runHeader(std::ostream &OS) {
50 EmitSourceFileHeader("Register Information Header Fragment", OS);
52 const std::string &TargetName = Target.getName();
53 std::string ClassName = TargetName + "GenRegisterInfo";
55 OS << "#include \"llvm/Target/MRegisterInfo.h\"\n";
56 OS << "#include <string>\n\n";
58 OS << "namespace llvm {\n\n";
60 OS << "struct " << ClassName << " : public MRegisterInfo {\n"
62 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
63 << " int getDwarfRegNum(unsigned RegNum) const;\n"
64 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
67 const std::vector<CodeGenRegisterClass> &RegisterClasses =
68 Target.getRegisterClasses();
70 if (!RegisterClasses.empty()) {
71 OS << "namespace " << RegisterClasses[0].Namespace
72 << " { // Register classes\n";
75 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
77 OS << " " << RegisterClasses[i].getName() << "RegClassID";
82 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
83 const std::string &Name = RegisterClasses[i].getName();
85 // Output the register class definition.
86 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
87 << " " << Name << "Class();\n"
88 << RegisterClasses[i].MethodProtos << " };\n";
90 // Output the extern for the instance.
91 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
92 // Output the extern for the pointer to the instance (should remove).
93 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
94 << Name << "RegClass;\n";
96 OS << "} // end of namespace " << TargetName << "\n\n";
98 OS << "} // End llvm namespace \n";
101 bool isSubRegisterClass(const CodeGenRegisterClass &RC,
102 std::set<Record*> &RegSet) {
103 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
104 Record *Reg = RC.Elements[i];
105 if (!RegSet.count(Reg))
111 static void addSuperReg(Record *R, Record *S,
112 std::map<Record*, std::set<Record*> > &SubRegs,
113 std::map<Record*, std::set<Record*> > &SuperRegs,
114 std::map<Record*, std::set<Record*> > &Aliases,
115 RegisterInfoEmitter &RIE) {
117 cerr << "Error: recursive sub-register relationship between"
118 << " register " << RIE.getQualifiedName(R)
119 << " and its sub-registers?\n";
122 if (!SuperRegs[R].insert(S).second)
124 SubRegs[S].insert(R);
125 Aliases[R].insert(S);
126 Aliases[S].insert(R);
127 if (SuperRegs.count(S))
128 for (std::set<Record*>::iterator I = SuperRegs[S].begin(),
129 E = SuperRegs[S].end(); I != E; ++I)
130 addSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE);
133 static void addSubSuperReg(Record *R, Record *S,
134 std::map<Record*, std::set<Record*> > &SubRegs,
135 std::map<Record*, std::set<Record*> > &SuperRegs,
136 std::map<Record*, std::set<Record*> > &Aliases,
137 RegisterInfoEmitter &RIE) {
139 cerr << "Error: recursive sub-register relationship between"
140 << " register " << RIE.getQualifiedName(R)
141 << " and its sub-registers?\n";
145 if (!SubRegs[R].insert(S).second)
147 addSuperReg(S, R, SubRegs, SuperRegs, Aliases, RIE);
148 Aliases[R].insert(S);
149 Aliases[S].insert(R);
150 if (SubRegs.count(S))
151 for (std::set<Record*>::iterator I = SubRegs[S].begin(),
152 E = SubRegs[S].end(); I != E; ++I)
153 addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE);
156 // RegisterInfoEmitter::run - Main register file description emitter.
158 void RegisterInfoEmitter::run(std::ostream &OS) {
159 CodeGenTarget Target;
160 EmitSourceFileHeader("Register Information Source Fragment", OS);
162 OS << "namespace llvm {\n\n";
164 // Start out by emitting each of the register classes... to do this, we build
165 // a set of registers which belong to a register class, this is to ensure that
166 // each register is only in a single register class.
168 const std::vector<CodeGenRegisterClass> &RegisterClasses =
169 Target.getRegisterClasses();
171 // Loop over all of the register classes... emitting each one.
172 OS << "namespace { // Register classes...\n";
174 // RegClassesBelongedTo - Keep track of which register classes each reg
176 std::multimap<Record*, const CodeGenRegisterClass*> RegClassesBelongedTo;
178 // Emit the register enum value arrays for each RegisterClass
179 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
180 const CodeGenRegisterClass &RC = RegisterClasses[rc];
182 // Give the register class a legal C name if it's anonymous.
183 std::string Name = RC.TheDef->getName();
185 // Emit the register list now.
186 OS << " // " << Name << " Register Class...\n"
187 << " static const unsigned " << Name
189 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
190 Record *Reg = RC.Elements[i];
191 OS << getQualifiedName(Reg) << ", ";
193 // Keep track of which regclasses this register is in.
194 RegClassesBelongedTo.insert(std::make_pair(Reg, &RC));
199 // Emit the ValueType arrays for each RegisterClass
200 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
201 const CodeGenRegisterClass &RC = RegisterClasses[rc];
203 // Give the register class a legal C name if it's anonymous.
204 std::string Name = RC.TheDef->getName() + "VTs";
206 // Emit the register list now.
208 << " Register Class Value Types...\n"
209 << " static const MVT::ValueType " << Name
211 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
212 OS << RC.VTs[i] << ", ";
213 OS << "MVT::Other\n };\n\n";
215 OS << "} // end anonymous namespace\n\n";
217 // Now that all of the structs have been emitted, emit the instances.
218 if (!RegisterClasses.empty()) {
219 OS << "namespace " << RegisterClasses[0].Namespace
220 << " { // Register class instances\n";
221 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
222 OS << " " << RegisterClasses[i].getName() << "Class\t"
223 << RegisterClasses[i].getName() << "RegClass;\n";
225 std::map<unsigned, std::set<unsigned> > SuperClassMap;
227 // Emit the sub-classes array for each RegisterClass
228 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
229 const CodeGenRegisterClass &RC = RegisterClasses[rc];
231 // Give the register class a legal C name if it's anonymous.
232 std::string Name = RC.TheDef->getName();
234 std::set<Record*> RegSet;
235 for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
236 Record *Reg = RC.Elements[i];
241 << " Register Class sub-classes...\n"
242 << " static const TargetRegisterClass* const "
243 << Name << "Subclasses [] = {\n ";
246 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
247 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
248 if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
249 RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
252 if (!Empty) OS << ", ";
253 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
256 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
257 SuperClassMap.find(rc2);
258 if (SCMI == SuperClassMap.end()) {
259 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
260 SCMI = SuperClassMap.find(rc2);
262 SCMI->second.insert(rc);
265 OS << (!Empty ? ", " : "") << "NULL";
269 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
270 const CodeGenRegisterClass &RC = RegisterClasses[rc];
272 // Give the register class a legal C name if it's anonymous.
273 std::string Name = RC.TheDef->getName();
276 << " Register Class super-classes...\n"
277 << " static const TargetRegisterClass* const "
278 << Name << "Superclasses [] = {\n ";
281 std::map<unsigned, std::set<unsigned> >::iterator I =
282 SuperClassMap.find(rc);
283 if (I != SuperClassMap.end()) {
284 for (std::set<unsigned>::iterator II = I->second.begin(),
285 EE = I->second.end(); II != EE; ++II) {
286 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
287 if (!Empty) OS << ", ";
288 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
293 OS << (!Empty ? ", " : "") << "NULL";
298 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
299 const CodeGenRegisterClass &RC = RegisterClasses[i];
300 OS << RC.MethodBodies << "\n";
301 OS << RC.getName() << "Class::" << RC.getName()
302 << "Class() : TargetRegisterClass("
303 << RC.getName() + "RegClassID" << ", "
304 << RC.getName() + "VTs" << ", "
305 << RC.getName() + "Subclasses" << ", "
306 << RC.getName() + "Superclasses" << ", "
307 << RC.SpillSize/8 << ", "
308 << RC.SpillAlignment/8 << ", " << RC.getName() << ", "
309 << RC.getName() << " + " << RC.Elements.size() << ") {}\n";
315 OS << "\nnamespace {\n";
316 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
317 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
318 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
322 // Emit register sub-registers / super-registers, aliases...
323 std::map<Record*, std::set<Record*> > RegisterSubRegs;
324 std::map<Record*, std::set<Record*> > RegisterSuperRegs;
325 std::map<Record*, std::set<Record*> > RegisterAliases;
326 std::map<Record*, std::vector<std::pair<int, Record*> > > SubRegVectors;
327 const std::vector<CodeGenRegister> &Regs = Target.getRegisters();
329 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
330 Record *R = Regs[i].TheDef;
331 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("Aliases");
332 // Add information that R aliases all of the elements in the list... and
333 // that everything in the list aliases R.
334 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
336 if (RegisterAliases[R].count(Reg))
337 cerr << "Warning: register alias between " << getQualifiedName(R)
338 << " and " << getQualifiedName(Reg)
339 << " specified multiple times!\n";
340 RegisterAliases[R].insert(Reg);
342 if (RegisterAliases[Reg].count(R))
343 cerr << "Warning: register alias between " << getQualifiedName(R)
344 << " and " << getQualifiedName(Reg)
345 << " specified multiple times!\n";
346 RegisterAliases[Reg].insert(R);
350 // Process sub-register sets.
351 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
352 Record *R = Regs[i].TheDef;
353 std::vector<Record*> LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
354 // Process sub-register set and add aliases information.
355 for (unsigned j = 0, e = LI.size(); j != e; ++j) {
356 Record *SubReg = LI[j];
357 if (RegisterSubRegs[R].count(SubReg))
358 cerr << "Warning: register " << getQualifiedName(SubReg)
359 << " specified as a sub-register of " << getQualifiedName(R)
360 << " multiple times!\n";
361 addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
362 RegisterAliases, *this);
366 if (!RegisterAliases.empty())
367 OS << "\n\n // Register Alias Sets...\n";
369 // Emit the empty alias list
370 OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
371 // Loop over all of the registers which have aliases, emitting the alias list
373 for (std::map<Record*, std::set<Record*> >::iterator
374 I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) {
375 OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { ";
376 for (std::set<Record*>::iterator ASI = I->second.begin(),
377 E = I->second.end(); ASI != E; ++ASI)
378 OS << getQualifiedName(*ASI) << ", ";
382 if (!RegisterSubRegs.empty())
383 OS << "\n\n // Register Sub-registers Sets...\n";
385 // Emit the empty sub-registers list
386 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
387 // Loop over all of the registers which have sub-registers, emitting the
388 // sub-registers list to memory.
389 for (std::map<Record*, std::set<Record*> >::iterator
390 I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
391 OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
392 for (std::set<Record*>::iterator ASI = I->second.begin(),
393 E = I->second.end(); ASI != E; ++ASI)
394 OS << getQualifiedName(*ASI) << ", ";
398 if (!RegisterSuperRegs.empty())
399 OS << "\n\n // Register Super-registers Sets...\n";
401 // Emit the empty super-registers list
402 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
403 // Loop over all of the registers which have super-registers, emitting the
404 // super-registers list to memory.
405 for (std::map<Record*, std::set<Record*> >::iterator
406 I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) {
407 OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
408 for (std::set<Record*>::iterator ASI = I->second.begin(),
409 E = I->second.end(); ASI != E; ++ASI)
410 OS << getQualifiedName(*ASI) << ", ";
414 OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n";
415 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
417 // Now that register alias and sub-registers sets have been emitted, emit the
418 // register descriptors now.
419 const std::vector<CodeGenRegister> &Registers = Target.getRegisters();
420 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
421 const CodeGenRegister &Reg = Registers[i];
423 if (!Reg.TheDef->getValueAsString("Name").empty())
424 OS << Reg.TheDef->getValueAsString("Name");
428 if (RegisterAliases.count(Reg.TheDef))
429 OS << Reg.getName() << "_AliasSet,\t";
431 OS << "Empty_AliasSet,\t";
432 if (RegisterSubRegs.count(Reg.TheDef))
433 OS << Reg.getName() << "_SubRegsSet,\t";
435 OS << "Empty_SubRegsSet,\t";
436 if (RegisterSuperRegs.count(Reg.TheDef))
437 OS << Reg.getName() << "_SuperRegsSet },\n";
439 OS << "Empty_SuperRegsSet },\n";
441 OS << " };\n"; // End of register descriptors...
442 OS << "}\n\n"; // End of anonymous namespace...
444 std::string ClassName = Target.getName() + "GenRegisterInfo";
446 // Calculate the mapping of subregister+index pairs to physical registers.
447 std::vector<Record*> SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
448 for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
449 int subRegIndex = SubRegs[i]->getValueAsInt("index");
450 std::vector<Record*> From = SubRegs[i]->getValueAsListOfDefs("From");
451 std::vector<Record*> To = SubRegs[i]->getValueAsListOfDefs("To");
453 assert((From.size() == To.size()) &&
454 "SubRegSet has mismatched from/to size");
456 // For each entry in from/to vectors, insert the to register at index
457 for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
458 SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
461 // Emit the subregister + index mapping function based on the information
463 OS << "unsigned " << ClassName
464 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
465 << " switch (RegNo) {\n"
466 << " default: abort(); break;\n";
467 for (std::map<Record*, std::vector<std::pair<int, Record*> > >::iterator
468 I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
469 OS << " case " << getQualifiedName(I->first) << ":\n";
470 OS << " switch (Index) {\n";
471 OS << " default: abort(); break;\n";
472 for (unsigned i = 0, e = I->second.size(); i != e; ++i)
473 OS << " case " << (I->second)[i].first << ": return "
474 << getQualifiedName((I->second)[i].second) << ";\n";
475 OS << " }; break;\n";
480 // Emit the constructor of the class...
481 OS << ClassName << "::" << ClassName
482 << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
483 << " : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1
484 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
485 << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
487 // Emit information about the dwarf register numbers.
488 OS << "int " << ClassName << "::getDwarfRegNum(unsigned RegNum) const {\n";
489 OS << " static const int DwarfRegNums[] = { -1, // NoRegister";
490 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
491 if (!(i % 16)) OS << "\n ";
492 const CodeGenRegister &Reg = Registers[i];
493 int DwarfRegNum = Reg.TheDef->getValueAsInt("DwarfNumber");
495 if ((i + 1) != e) OS << ", ";
498 OS << " assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) &&\n";
499 OS << " \"RegNum exceeds number of registers\");\n";
500 OS << " return DwarfRegNums[RegNum];\n";
503 OS << "} // End llvm namespace \n";