1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
19 #include "SequenceToOffsetTable.h"
20 #include "llvm/TableGen/Record.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/StringExtras.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/Support/Format.h"
29 // runEnums - Print out enum values for all of the registers.
31 RegisterInfoEmitter::runEnums(raw_ostream &OS,
32 CodeGenTarget &Target, CodeGenRegBank &Bank) {
33 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
35 // Register enums are stored as uint16_t in the tables. Make sure we'll fit
36 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables");
38 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
40 EmitSourceFileHeader("Target Register Enum Values", OS);
42 OS << "\n#ifdef GET_REGINFO_ENUM\n";
43 OS << "#undef GET_REGINFO_ENUM\n";
45 OS << "namespace llvm {\n\n";
47 OS << "class MCRegisterClass;\n"
48 << "extern const MCRegisterClass " << Namespace
49 << "MCRegisterClasses[];\n\n";
51 if (!Namespace.empty())
52 OS << "namespace " << Namespace << " {\n";
53 OS << "enum {\n NoRegister,\n";
55 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
56 OS << " " << Registers[i]->getName() << " = " <<
57 Registers[i]->EnumValue << ",\n";
58 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
59 "Register enum value mismatch!");
60 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
62 if (!Namespace.empty())
65 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
66 if (!RegisterClasses.empty()) {
68 // RegisterClass enums are stored as uint16_t in the tables.
69 assert(RegisterClasses.size() <= 0xffff &&
70 "Too many register classes to fit in tables");
72 OS << "\n// Register classes\n";
73 if (!Namespace.empty())
74 OS << "namespace " << Namespace << " {\n";
76 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
78 OS << " " << RegisterClasses[i]->getName() << "RegClassID";
82 if (!Namespace.empty())
86 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
87 // If the only definition is the default NoRegAltName, we don't need to
89 if (RegAltNameIndices.size() > 1) {
90 OS << "\n// Register alternate name indices\n";
91 if (!Namespace.empty())
92 OS << "namespace " << Namespace << " {\n";
94 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
95 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
96 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
98 if (!Namespace.empty())
102 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = Bank.getSubRegIndices();
103 if (!SubRegIndices.empty()) {
104 OS << "\n// Subregister indices\n";
105 std::string Namespace =
106 SubRegIndices[0]->getNamespace();
107 if (!Namespace.empty())
108 OS << "namespace " << Namespace << " {\n";
109 OS << "enum {\n NoSubRegister,\n";
110 for (unsigned i = 0, e = Bank.getNumNamedIndices(); i != e; ++i)
111 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
112 OS << " NUM_TARGET_NAMED_SUBREGS\n};\n";
113 if (!Namespace.empty())
117 OS << "} // End llvm namespace \n";
118 OS << "#endif // GET_REGINFO_ENUM\n\n";
123 RegisterInfoEmitter::EmitRegMappingTables(raw_ostream &OS,
124 const std::vector<CodeGenRegister*> &Regs,
126 // Collect all information about dwarf register numbers
127 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
128 DwarfRegNumsMapTy DwarfRegNums;
130 // First, just pull all provided information to the map
131 unsigned maxLength = 0;
132 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
133 Record *Reg = Regs[i]->TheDef;
134 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
135 maxLength = std::max((size_t)maxLength, RegNums.size());
136 if (DwarfRegNums.count(Reg))
137 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
138 << "specified multiple times\n";
139 DwarfRegNums[Reg] = RegNums;
145 // Now we know maximal length of number list. Append -1's, where needed
146 for (DwarfRegNumsMapTy::iterator
147 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
148 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
149 I->second.push_back(-1);
151 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
153 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n";
155 // Emit reverse information about the dwarf register numbers.
156 for (unsigned j = 0; j < 2; ++j) {
157 for (unsigned i = 0, e = maxLength; i != e; ++i) {
158 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
159 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
160 OS << i << "Dwarf2L[]";
165 // Store the mapping sorted by the LLVM reg num so lookup can be done
166 // with a binary search.
167 std::map<uint64_t, Record*> Dwarf2LMap;
168 for (DwarfRegNumsMapTy::iterator
169 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
170 int DwarfRegNo = I->second[i];
173 Dwarf2LMap[DwarfRegNo] = I->first;
176 for (std::map<uint64_t, Record*>::iterator
177 I = Dwarf2LMap.begin(), E = Dwarf2LMap.end(); I != E; ++I)
178 OS << " { " << I->first << "U, " << getQualifiedName(I->second)
186 // We have to store the size in a const global, it's used in multiple
188 OS << "extern const unsigned " << Namespace
189 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "Dwarf2LSize";
191 OS << " = sizeof(" << Namespace
192 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
193 << "Dwarf2L)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
199 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
200 Record *Reg = Regs[i]->TheDef;
201 const RecordVal *V = Reg->getValue("DwarfAlias");
202 if (!V || !V->getValue())
205 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
206 Record *Alias = DI->getDef();
207 DwarfRegNums[Reg] = DwarfRegNums[Alias];
210 // Emit information about the dwarf register numbers.
211 for (unsigned j = 0; j < 2; ++j) {
212 for (unsigned i = 0, e = maxLength; i != e; ++i) {
213 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace;
214 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour");
215 OS << i << "L2Dwarf[]";
218 // Store the mapping sorted by the Dwarf reg num so lookup can be done
219 // with a binary search.
220 for (DwarfRegNumsMapTy::iterator
221 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
222 int RegNo = I->second[i];
223 if (RegNo == -1) // -1 is the default value, don't emit a mapping.
226 OS << " { " << getQualifiedName(I->first) << ", " << RegNo
234 // We have to store the size in a const global, it's used in multiple
236 OS << "extern const unsigned " << Namespace
237 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize";
239 OS << " = sizeof(" << Namespace
240 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
241 << "L2Dwarf)/sizeof(MCRegisterInfo::DwarfLLVMRegPair);\n\n";
249 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
250 const std::vector<CodeGenRegister*> &Regs,
252 // Emit the initializer so the tables from EmitRegMappingTables get wired up
253 // to the MCRegisterInfo object.
254 unsigned maxLength = 0;
255 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
256 Record *Reg = Regs[i]->TheDef;
257 maxLength = std::max((size_t)maxLength,
258 Reg->getValueAsListOfInts("DwarfNumbers").size());
264 std::string Namespace = Regs[0]->TheDef->getValueAsString("Namespace");
266 // Emit reverse information about the dwarf register numbers.
267 for (unsigned j = 0; j < 2; ++j) {
270 OS << "DwarfFlavour";
275 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
277 for (unsigned i = 0, e = maxLength; i != e; ++i) {
278 OS << " case " << i << ":\n";
283 raw_string_ostream(Tmp) << Namespace
284 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
286 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, ";
297 // Emit information about the dwarf register numbers.
298 for (unsigned j = 0; j < 2; ++j) {
301 OS << "DwarfFlavour";
306 << " llvm_unreachable(\"Unknown DWARF flavour\");\n";
308 for (unsigned i = 0, e = maxLength; i != e; ++i) {
309 OS << " case " << i << ":\n";
314 raw_string_ostream(Tmp) << Namespace
315 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i
317 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, ";
329 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
330 // Width is the number of bits per hex number.
331 static void printBitVectorAsHex(raw_ostream &OS,
332 const BitVector &Bits,
334 assert(Width <= 32 && "Width too large");
335 unsigned Digits = (Width + 3) / 4;
336 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
338 for (unsigned j = 0; j != Width && i + j != e; ++j)
339 Value |= Bits.test(i + j) << j;
340 OS << format("0x%0*x, ", Digits, Value);
344 // Helper to emit a set of bits into a constant byte array.
345 class BitVectorEmitter {
348 void add(unsigned v) {
349 if (v >= Values.size())
350 Values.resize(((v/8)+1)*8); // Round up to the next byte.
354 void print(raw_ostream &OS) {
355 printBitVectorAsHex(OS, Values, 8);
359 static void printRegister(raw_ostream &OS, const CodeGenRegister *Reg) {
360 OS << getQualifiedName(Reg->TheDef);
363 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) {
364 OS << getEnumName(VT);
368 // runMCDesc - Print out MC register descriptions.
371 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
372 CodeGenRegBank &RegBank) {
373 EmitSourceFileHeader("MC Register Information", OS);
375 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
376 OS << "#undef GET_REGINFO_MC_DESC\n";
378 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
379 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
380 RegBank.computeOverlaps(Overlaps);
382 // The lists of sub-registers, super-registers, and overlaps all go in the
383 // same array. That allows us to share suffixes.
384 typedef std::vector<const CodeGenRegister*> RegVec;
385 SmallVector<RegVec, 4> SubRegLists(Regs.size());
386 SmallVector<RegVec, 4> OverlapLists(Regs.size());
387 SequenceToOffsetTable<RegVec, CodeGenRegister::Less> RegSeqs;
389 // Precompute register lists for the SequenceToOffsetTable.
390 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
391 const CodeGenRegister *Reg = Regs[i];
393 // Compute the ordered sub-register list.
394 SetVector<const CodeGenRegister*> SR;
395 Reg->addSubRegsPreOrder(SR, RegBank);
396 RegVec &SubRegList = SubRegLists[i];
397 SubRegList.assign(SR.begin(), SR.end());
398 RegSeqs.add(SubRegList);
400 // Super-registers are already computed.
401 const RegVec &SuperRegList = Reg->getSuperRegs();
402 RegSeqs.add(SuperRegList);
404 // The list of overlaps doesn't need to have any particular order, except
405 // Reg itself must be the first element. Pick an ordering that has one of
406 // the other lists as a suffix.
407 RegVec &OverlapList = OverlapLists[i];
408 const RegVec &Suffix = SubRegList.size() > SuperRegList.size() ?
409 SubRegList : SuperRegList;
410 CodeGenRegister::Set Omit(Suffix.begin(), Suffix.end());
412 // First element is Reg itself.
413 OverlapList.push_back(Reg);
416 // Any elements not in Suffix.
417 const CodeGenRegister::Set &OSet = Overlaps[Reg];
418 std::set_difference(OSet.begin(), OSet.end(),
419 Omit.begin(), Omit.end(),
420 std::back_inserter(OverlapList),
421 CodeGenRegister::Less());
423 // Finally, Suffix itself.
424 OverlapList.insert(OverlapList.end(), Suffix.begin(), Suffix.end());
425 RegSeqs.add(OverlapList);
428 // Compute the final layout of the sequence table.
431 OS << "namespace llvm {\n\n";
433 const std::string &TargetName = Target.getName();
435 // Emit the shared table of register lists.
436 OS << "extern const uint16_t " << TargetName << "RegLists[] = {\n";
437 RegSeqs.emit(OS, printRegister);
440 OS << "extern const MCRegisterDesc " << TargetName
441 << "RegDesc[] = { // Descriptors\n";
442 OS << " { \"NOREG\", 0, 0, 0 },\n";
444 // Emit the register descriptors now.
445 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
446 const CodeGenRegister *Reg = Regs[i];
447 OS << " { \"" << Reg->getName() << "\", "
448 << RegSeqs.get(OverlapLists[i]) << ", "
449 << RegSeqs.get(SubRegLists[i]) << ", "
450 << RegSeqs.get(Reg->getSuperRegs()) << " },\n";
452 OS << "};\n\n"; // End of register descriptors...
454 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
456 // Loop over all of the register classes... emitting each one.
457 OS << "namespace { // Register classes...\n";
459 // Emit the register enum value arrays for each RegisterClass
460 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
461 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
462 ArrayRef<Record*> Order = RC.getOrder();
464 // Give the register class a legal C name if it's anonymous.
465 std::string Name = RC.getName();
467 // Emit the register list now.
468 OS << " // " << Name << " Register Class...\n"
469 << " const uint16_t " << Name
471 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
472 Record *Reg = Order[i];
473 OS << getQualifiedName(Reg) << ", ";
477 OS << " // " << Name << " Bit set.\n"
478 << " const uint8_t " << Name
480 BitVectorEmitter BVE;
481 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
482 Record *Reg = Order[i];
483 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
491 OS << "extern const MCRegisterClass " << TargetName
492 << "MCRegisterClasses[] = {\n";
494 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
495 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
497 // Asserts to make sure values will fit in table assuming types from
499 assert((RC.SpillSize/8) <= 0xffff && "SpillSize too large.");
500 assert((RC.SpillAlignment/8) <= 0xffff && "SpillAlignment too large.");
501 assert(RC.CopyCost >= -128 && RC.CopyCost <= 127 && "Copy cost too large.");
503 OS << " { " << '\"' << RC.getName() << "\", "
504 << RC.getName() << ", " << RC.getName() << "Bits, "
505 << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
506 << RC.getQualifiedName() + "RegClassID" << ", "
507 << RC.SpillSize/8 << ", "
508 << RC.SpillAlignment/8 << ", "
509 << RC.CopyCost << ", "
510 << RC.Allocatable << " },\n";
515 // Emit the data table for getSubReg().
516 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
517 if (SubRegIndices.size()) {
518 OS << "const uint16_t " << TargetName << "SubRegTable[]["
519 << SubRegIndices.size() << "] = {\n";
520 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
521 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
522 OS << " /* " << Regs[i]->TheDef->getName() << " */\n";
528 for (unsigned j = 0, je = SubRegIndices.size(); j != je; ++j) {
529 // FIXME: We really should keep this to 80 columns...
530 CodeGenRegister::SubRegMap::const_iterator SubReg =
531 SRM.find(SubRegIndices[j]);
532 if (SubReg != SRM.end())
533 OS << getQualifiedName(SubReg->second->TheDef);
539 OS << "}" << (i != e ? "," : "") << "\n";
542 OS << "const uint16_t *get" << TargetName
543 << "SubRegTable() {\n return (const uint16_t *)" << TargetName
544 << "SubRegTable;\n}\n\n";
547 EmitRegMappingTables(OS, Regs, false);
549 // MCRegisterInfo initialization routine.
550 OS << "static inline void Init" << TargetName
551 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
552 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
553 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
554 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
555 << RegisterClasses.size() << ", " << TargetName << "RegLists, ";
556 if (SubRegIndices.size() != 0)
557 OS << "(uint16_t*)" << TargetName << "SubRegTable, "
558 << SubRegIndices.size() << ");\n\n";
560 OS << "NULL, 0);\n\n";
562 EmitRegMapping(OS, Regs, false);
566 OS << "} // End llvm namespace \n";
567 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
571 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
572 CodeGenRegBank &RegBank) {
573 EmitSourceFileHeader("Register Information Header Fragment", OS);
575 OS << "\n#ifdef GET_REGINFO_HEADER\n";
576 OS << "#undef GET_REGINFO_HEADER\n";
578 const std::string &TargetName = Target.getName();
579 std::string ClassName = TargetName + "GenRegisterInfo";
581 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n\n";
583 OS << "namespace llvm {\n\n";
585 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
586 << " explicit " << ClassName
587 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
588 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
589 << " { return false; }\n"
590 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
591 << " const TargetRegisterClass *"
592 "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n"
593 << " const TargetRegisterClass *getMatchingSuperRegClass("
594 "const TargetRegisterClass*, const TargetRegisterClass*, "
598 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
600 if (!RegisterClasses.empty()) {
601 OS << "namespace " << RegisterClasses[0]->Namespace
602 << " { // Register classes\n";
604 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
605 const CodeGenRegisterClass &RC = *RegisterClasses[i];
606 const std::string &Name = RC.getName();
608 // Output the extern for the instance.
609 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n";
610 // Output the extern for the pointer to the instance (should remove).
611 OS << " static const TargetRegisterClass * const " << Name
612 << "RegisterClass = &" << Name << "RegClass;\n";
614 OS << "} // end of namespace " << TargetName << "\n\n";
616 OS << "} // End llvm namespace \n";
617 OS << "#endif // GET_REGINFO_HEADER\n\n";
621 // runTargetDesc - Output the target register and register file descriptions.
624 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
625 CodeGenRegBank &RegBank){
626 EmitSourceFileHeader("Target Register and Register Classes Information", OS);
628 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
629 OS << "#undef GET_REGINFO_TARGET_DESC\n";
631 OS << "namespace llvm {\n\n";
633 // Get access to MCRegisterClass data.
634 OS << "extern const MCRegisterClass " << Target.getName()
635 << "MCRegisterClasses[];\n";
637 // Start out by emitting each of the register classes.
638 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
640 // Collect all registers belonging to any allocatable class.
641 std::set<Record*> AllocatableRegs;
643 // Collect allocatable registers.
644 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
645 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
646 ArrayRef<Record*> Order = RC.getOrder();
649 AllocatableRegs.insert(Order.begin(), Order.end());
652 // Build a shared array of value types.
653 SequenceToOffsetTable<std::vector<MVT::SimpleValueType> > VTSeqs;
654 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc)
655 VTSeqs.add(RegisterClasses[rc]->VTs);
657 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n";
658 VTSeqs.emit(OS, printSimpleValueType, "MVT::Other");
661 // Now that all of the structs have been emitted, emit the instances.
662 if (!RegisterClasses.empty()) {
663 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
665 OS << "\nstatic const TargetRegisterClass *const "
666 << "NullRegClasses[] = { NULL };\n\n";
668 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
670 if (NumSubRegIndices) {
671 // Compute the super-register classes for each RegisterClass
672 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
673 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
674 for (DenseMap<Record*,Record*>::const_iterator
675 i = RC.SubRegClasses.begin(),
676 e = RC.SubRegClasses.end(); i != e; ++i) {
677 // Find the register class number of i->second for SuperRegClassMap.
678 const CodeGenRegisterClass *RC2 = RegBank.getRegClass(i->second);
679 assert(RC2 && "Invalid register class in SubRegClasses");
680 SuperRegClassMap[RC2->EnumValue].insert(rc);
684 // Emit the super-register classes for each RegisterClass
685 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
686 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
688 // Give the register class a legal C name if it's anonymous.
689 std::string Name = RC.getName();
692 << " Super-register Classes...\n"
693 << "static const TargetRegisterClass *const "
694 << Name << "SuperRegClasses[] = {\n ";
697 std::map<unsigned, std::set<unsigned> >::iterator I =
698 SuperRegClassMap.find(rc);
699 if (I != SuperRegClassMap.end()) {
700 for (std::set<unsigned>::iterator II = I->second.begin(),
701 EE = I->second.end(); II != EE; ++II) {
702 const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
705 OS << "&" << RC2.getQualifiedName() << "RegClass";
710 OS << (!Empty ? ", " : "") << "NULL";
715 // Emit the sub-classes array for each RegisterClass
716 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
717 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
719 // Give the register class a legal C name if it's anonymous.
720 std::string Name = RC.getName();
722 OS << "static const uint32_t " << Name << "SubclassMask[] = {\n ";
723 printBitVectorAsHex(OS, RC.getSubClasses(), 32);
727 // Emit NULL terminated super-class lists.
728 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
729 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
730 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
732 // Skip classes without supers. We can reuse NullRegClasses.
736 OS << "static const TargetRegisterClass *const "
737 << RC.getName() << "Superclasses[] = {\n";
738 for (unsigned i = 0; i != Supers.size(); ++i)
739 OS << " &" << Supers[i]->getQualifiedName() << "RegClass,\n";
740 OS << " NULL\n};\n\n";
744 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
745 const CodeGenRegisterClass &RC = *RegisterClasses[i];
746 if (!RC.AltOrderSelect.empty()) {
747 OS << "\nstatic inline unsigned " << RC.getName()
748 << "AltOrderSelect(const MachineFunction &MF) {"
749 << RC.AltOrderSelect << "}\n\n"
750 << "static ArrayRef<uint16_t> " << RC.getName()
751 << "GetRawAllocationOrder(const MachineFunction &MF) {\n";
752 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
753 ArrayRef<Record*> Elems = RC.getOrder(oi);
754 if (!Elems.empty()) {
755 OS << " static const uint16_t AltOrder" << oi << "[] = {";
756 for (unsigned elem = 0; elem != Elems.size(); ++elem)
757 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
761 OS << " const MCRegisterClass &MCR = " << Target.getName()
762 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n"
763 << " const ArrayRef<uint16_t> Order[] = {\n"
764 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
765 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
766 if (RC.getOrder(oi).empty())
767 OS << "),\n ArrayRef<uint16_t>(";
769 OS << "),\n makeArrayRef(AltOrder" << oi;
770 OS << ")\n };\n const unsigned Select = " << RC.getName()
771 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
772 << ");\n return Order[Select];\n}\n";
776 // Now emit the actual value-initialized register class instances.
777 OS << "namespace " << RegisterClasses[0]->Namespace
778 << " { // Register class instances\n";
780 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
781 const CodeGenRegisterClass &RC = *RegisterClasses[i];
782 OS << " extern const TargetRegisterClass "
783 << RegisterClasses[i]->getName() << "RegClass = {\n "
784 << '&' << Target.getName() << "MCRegisterClasses[" << RC.getName()
786 << "VTLists + " << VTSeqs.get(RC.VTs) << ",\n "
787 << RC.getName() << "SubclassMask,\n ";
788 if (RC.getSuperClasses().empty())
789 OS << "NullRegClasses,\n ";
791 OS << RC.getName() << "Superclasses,\n ";
792 OS << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
794 if (RC.AltOrderSelect.empty())
797 OS << RC.getName() << "GetRawAllocationOrder\n";
804 OS << "\nnamespace {\n";
805 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
806 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
807 OS << " &" << RegisterClasses[i]->getQualifiedName()
810 OS << "}\n"; // End of anonymous namespace...
812 // Emit extra information about registers.
813 const std::string &TargetName = Target.getName();
814 OS << "\nstatic const TargetRegisterInfoDesc "
815 << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
816 OS << " { 0, 0 },\n";
818 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
819 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
820 const CodeGenRegister &Reg = *Regs[i];
822 OS << Reg.CostPerUse << ", "
823 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
825 OS << "};\n"; // End of register descriptors...
828 // Calculate the mapping of subregister+index pairs to physical registers.
829 // This will also create further anonymous indices.
830 unsigned NamedIndices = RegBank.getNumNamedIndices();
832 // Emit SubRegIndex names, skipping 0
833 ArrayRef<CodeGenSubRegIndex*> SubRegIndices = RegBank.getSubRegIndices();
834 OS << "\nstatic const char *const " << TargetName
835 << "SubRegIndexTable[] = { \"";
836 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
837 OS << SubRegIndices[i]->getName();
843 // Emit names of the anonymous subreg indices.
844 if (SubRegIndices.size() > NamedIndices) {
846 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
847 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
855 std::string ClassName = Target.getName() + "GenRegisterInfo";
857 // Emit composeSubRegIndices
858 OS << "unsigned " << ClassName
859 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
860 << " switch (IdxA) {\n"
861 << " default:\n return IdxB;\n";
862 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
864 for (unsigned j = 0; j != e; ++j) {
865 if (CodeGenSubRegIndex *Comp =
866 SubRegIndices[i]->compose(SubRegIndices[j])) {
868 OS << " case " << SubRegIndices[i]->getQualifiedName()
869 << ": switch(IdxB) {\n default: return IdxB;\n";
872 OS << " case " << SubRegIndices[j]->getQualifiedName()
873 << ": return " << Comp->getQualifiedName() << ";\n";
881 // Emit getSubClassWithSubReg.
882 OS << "const TargetRegisterClass *" << ClassName
883 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
885 if (SubRegIndices.empty()) {
886 OS << " assert(Idx == 0 && \"Target has no sub-registers\");\n"
889 // Use the smallest type that can hold a regclass ID with room for a
891 if (RegisterClasses.size() < UINT8_MAX)
892 OS << " static const uint8_t Table[";
893 else if (RegisterClasses.size() < UINT16_MAX)
894 OS << " static const uint16_t Table[";
896 throw "Too many register classes.";
897 OS << RegisterClasses.size() << "][" << SubRegIndices.size() << "] = {\n";
898 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
899 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
900 OS << " {\t// " << RC.getName() << "\n";
901 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
902 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
903 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(Idx))
904 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx->getName()
905 << " -> " << SRC->getName() << "\n";
907 OS << " 0,\t// " << Idx->getName() << "\n";
911 OS << " };\n assert(RC && \"Missing regclass\");\n"
912 << " if (!Idx) return RC;\n --Idx;\n"
913 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
914 << " unsigned TV = Table[RC->getID()][Idx];\n"
915 << " return TV ? getRegClass(TV - 1) : 0;\n";
919 // Emit getMatchingSuperRegClass.
920 OS << "const TargetRegisterClass *" << ClassName
921 << "::getMatchingSuperRegClass(const TargetRegisterClass *A,"
922 " const TargetRegisterClass *B, unsigned Idx) const {\n";
923 if (SubRegIndices.empty()) {
924 OS << " llvm_unreachable(\"Target has no sub-registers\");\n";
926 // We need to find the largest sub-class of A such that every register has
927 // an Idx sub-register in B. Map (B, Idx) to a bit-vector of
928 // super-register classes that map into B. Then compute the largest common
929 // sub-class with A by taking advantage of the register class ordering,
930 // like getCommonSubClass().
932 // Bitvector table is NumRCs x NumSubIndexes x BVWords, where BVWords is
933 // the number of 32-bit words required to represent all register classes.
934 const unsigned BVWords = (RegisterClasses.size()+31)/32;
935 BitVector BV(RegisterClasses.size());
937 OS << " static const uint32_t Table[" << RegisterClasses.size()
938 << "][" << SubRegIndices.size() << "][" << BVWords << "] = {\n";
939 for (unsigned rci = 0, rce = RegisterClasses.size(); rci != rce; ++rci) {
940 const CodeGenRegisterClass &RC = *RegisterClasses[rci];
941 OS << " {\t// " << RC.getName() << "\n";
942 for (unsigned sri = 0, sre = SubRegIndices.size(); sri != sre; ++sri) {
943 CodeGenSubRegIndex *Idx = SubRegIndices[sri];
945 RC.getSuperRegClasses(Idx, BV);
947 printBitVectorAsHex(OS, BV, 32);
948 OS << "},\t// " << Idx->getName() << '\n';
952 OS << " };\n assert(A && B && \"Missing regclass\");\n"
954 << " assert(Idx < " << SubRegIndices.size() << " && \"Bad subreg\");\n"
955 << " const uint32_t *TV = Table[B->getID()][Idx];\n"
956 << " const uint32_t *SC = A->getSubClassMask();\n"
957 << " for (unsigned i = 0; i != " << BVWords << "; ++i)\n"
958 << " if (unsigned Common = TV[i] & SC[i])\n"
959 << " return getRegClass(32*i + CountTrailingZeros_32(Common));\n"
964 // Emit the constructor of the class...
965 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
966 OS << "extern const uint16_t " << TargetName << "RegLists[];\n";
967 if (SubRegIndices.size() != 0)
968 OS << "extern const uint16_t *get" << TargetName
969 << "SubRegTable();\n";
971 EmitRegMappingTables(OS, Regs, true);
973 OS << ClassName << "::\n" << ClassName
974 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
975 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
976 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
977 << " " << TargetName << "SubRegIndexTable) {\n"
978 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
979 << Regs.size()+1 << ", RA,\n " << TargetName
980 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
981 << " " << TargetName << "RegLists,\n"
983 if (SubRegIndices.size() != 0)
984 OS << "get" << TargetName << "SubRegTable(), "
985 << SubRegIndices.size() << ");\n\n";
987 OS << "NULL, 0);\n\n";
989 EmitRegMapping(OS, Regs, true);
994 // Emit CalleeSavedRegs information.
995 std::vector<Record*> CSRSets =
996 Records.getAllDerivedDefinitions("CalleeSavedRegs");
997 for (unsigned i = 0, e = CSRSets.size(); i != e; ++i) {
998 Record *CSRSet = CSRSets[i];
999 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet);
1000 assert(Regs && "Cannot expand CalleeSavedRegs instance");
1002 // Emit the *_SaveList list of callee-saved registers.
1003 OS << "static const uint16_t " << CSRSet->getName()
1004 << "_SaveList[] = { ";
1005 for (unsigned r = 0, re = Regs->size(); r != re; ++r)
1006 OS << getQualifiedName((*Regs)[r]) << ", ";
1009 // Emit the *_RegMask bit mask of call-preserved registers.
1010 OS << "static const uint32_t " << CSRSet->getName()
1011 << "_RegMask[] = { ";
1012 printBitVectorAsHex(OS, RegBank.computeCoveredRegisters(*Regs), 32);
1017 OS << "} // End llvm namespace \n";
1018 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
1021 void RegisterInfoEmitter::run(raw_ostream &OS) {
1022 CodeGenTarget Target(Records);
1023 CodeGenRegBank &RegBank = Target.getRegBank();
1024 RegBank.computeDerivedInfo();
1026 runEnums(OS, Target, RegBank);
1027 runMCDesc(OS, Target, RegBank);
1028 runTargetHeader(OS, Target, RegBank);
1029 runTargetDesc(OS, Target, RegBank);