1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/BitVector.h"
21 #include "llvm/ADT/StringExtras.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/Support/Format.h"
28 // runEnums - Print out enum values for all of the registers.
30 RegisterInfoEmitter::runEnums(raw_ostream &OS,
31 CodeGenTarget &Target, CodeGenRegBank &Bank) {
32 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
34 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
36 EmitSourceFileHeader("Target Register Enum Values", OS);
38 OS << "\n#ifdef GET_REGINFO_ENUM\n";
39 OS << "#undef GET_REGINFO_ENUM\n";
41 OS << "namespace llvm {\n\n";
43 OS << "class MCRegisterClass;\n"
44 << "extern MCRegisterClass " << Namespace << "MCRegisterClasses[];\n\n";
46 if (!Namespace.empty())
47 OS << "namespace " << Namespace << " {\n";
48 OS << "enum {\n NoRegister,\n";
50 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
51 OS << " " << Registers[i]->getName() << " = " <<
52 Registers[i]->EnumValue << ",\n";
53 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
54 "Register enum value mismatch!");
55 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
57 if (!Namespace.empty())
60 ArrayRef<CodeGenRegisterClass*> RegisterClasses = Bank.getRegClasses();
61 if (!RegisterClasses.empty()) {
62 OS << "\n// Register classes\n";
63 if (!Namespace.empty())
64 OS << "namespace " << Namespace << " {\n";
66 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
68 OS << " " << RegisterClasses[i]->getName() << "RegClassID";
72 if (!Namespace.empty())
76 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
77 // If the only definition is the default NoRegAltName, we don't need to
79 if (RegAltNameIndices.size() > 1) {
80 OS << "\n// Register alternate name indices\n";
81 if (!Namespace.empty())
82 OS << "namespace " << Namespace << " {\n";
84 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
85 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
86 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
88 if (!Namespace.empty())
93 OS << "} // End llvm namespace \n";
94 OS << "#endif // GET_REGINFO_ENUM\n\n";
98 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
99 const std::vector<CodeGenRegister*> &Regs,
102 // Collect all information about dwarf register numbers
103 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
104 DwarfRegNumsMapTy DwarfRegNums;
106 // First, just pull all provided information to the map
107 unsigned maxLength = 0;
108 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
109 Record *Reg = Regs[i]->TheDef;
110 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
111 maxLength = std::max((size_t)maxLength, RegNums.size());
112 if (DwarfRegNums.count(Reg))
113 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
114 << "specified multiple times\n";
115 DwarfRegNums[Reg] = RegNums;
121 // Now we know maximal length of number list. Append -1's, where needed
122 for (DwarfRegNumsMapTy::iterator
123 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
124 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
125 I->second.push_back(-1);
127 // Emit reverse information about the dwarf register numbers.
128 for (unsigned j = 0; j < 2; ++j) {
131 OS << "DwarfFlavour";
136 << " assert(0 && \"Unknown DWARF flavour\");\n"
139 for (unsigned i = 0, e = maxLength; i != e; ++i) {
140 OS << " case " << i << ":\n";
141 for (DwarfRegNumsMapTy::iterator
142 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
143 int DwarfRegNo = I->second[i];
149 OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", "
150 << getQualifiedName(I->first) << ", ";
162 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
163 Record *Reg = Regs[i]->TheDef;
164 const RecordVal *V = Reg->getValue("DwarfAlias");
165 if (!V || !V->getValue())
168 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
169 Record *Alias = DI->getDef();
170 DwarfRegNums[Reg] = DwarfRegNums[Alias];
173 // Emit information about the dwarf register numbers.
174 for (unsigned j = 0; j < 2; ++j) {
177 OS << "DwarfFlavour";
182 << " assert(0 && \"Unknown DWARF flavour\");\n"
185 for (unsigned i = 0, e = maxLength; i != e; ++i) {
186 OS << " case " << i << ":\n";
187 // Sort by name to get a stable order.
188 for (DwarfRegNumsMapTy::iterator
189 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
190 int RegNo = I->second[i];
194 OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", "
208 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
209 // Width is the number of bits per hex number.
210 static void printBitVectorAsHex(raw_ostream &OS,
211 const BitVector &Bits,
213 assert(Width <= 32 && "Width too large");
214 unsigned Digits = (Width + 3) / 4;
215 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) {
217 for (unsigned j = 0; j != Width && i + j != e; ++j)
218 Value |= Bits.test(i + j) << j;
219 OS << format("0x%0*x, ", Digits, Value);
223 // Helper to emit a set of bits into a constant byte array.
224 class BitVectorEmitter {
227 void add(unsigned v) {
228 if (v >= Values.size())
229 Values.resize(((v/8)+1)*8); // Round up to the next byte.
233 void print(raw_ostream &OS) {
234 printBitVectorAsHex(OS, Values, 8);
239 // runMCDesc - Print out MC register descriptions.
242 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
243 CodeGenRegBank &RegBank) {
244 EmitSourceFileHeader("MC Register Information", OS);
246 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
247 OS << "#undef GET_REGINFO_MC_DESC\n";
249 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
250 RegBank.computeOverlaps(Overlaps);
252 OS << "namespace llvm {\n\n";
254 const std::string &TargetName = Target.getName();
255 std::string ClassName = TargetName + "GenMCRegisterInfo";
256 OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
257 << " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
260 OS << "\nnamespace {\n";
262 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
264 // Emit an overlap list for all registers.
265 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
266 const CodeGenRegister *Reg = Regs[i];
267 const CodeGenRegister::Set &O = Overlaps[Reg];
268 // Move Reg to the front so TRI::getAliasSet can share the list.
269 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
270 << getQualifiedName(Reg->TheDef) << ", ";
271 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
274 OS << getQualifiedName((*I)->TheDef) << ", ";
278 // Emit the empty sub-registers list
279 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
280 // Loop over all of the registers which have sub-registers, emitting the
281 // sub-registers list to memory.
282 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
283 const CodeGenRegister &Reg = *Regs[i];
284 if (Reg.getSubRegs().empty())
286 // getSubRegs() orders by SubRegIndex. We want a topological order.
287 SetVector<CodeGenRegister*> SR;
288 Reg.addSubRegsPreOrder(SR);
289 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
290 for (unsigned j = 0, je = SR.size(); j != je; ++j)
291 OS << getQualifiedName(SR[j]->TheDef) << ", ";
295 // Emit the empty super-registers list
296 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
297 // Loop over all of the registers which have super-registers, emitting the
298 // super-registers list to memory.
299 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
300 const CodeGenRegister &Reg = *Regs[i];
301 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
304 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
305 for (unsigned j = 0, je = SR.size(); j != je; ++j)
306 OS << getQualifiedName(SR[j]->TheDef) << ", ";
309 OS << "}\n"; // End of anonymous namespace...
311 OS << "\nMCRegisterDesc " << TargetName
312 << "RegDesc[] = { // Descriptors\n";
313 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
315 // Now that register alias and sub-registers sets have been emitted, emit the
316 // register descriptors now.
317 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
318 const CodeGenRegister &Reg = *Regs[i];
320 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
321 if (!Reg.getSubRegs().empty())
322 OS << Reg.getName() << "_SubRegsSet,\t";
324 OS << "Empty_SubRegsSet,\t";
325 if (!Reg.getSuperRegs().empty())
326 OS << Reg.getName() << "_SuperRegsSet";
328 OS << "Empty_SuperRegsSet";
331 OS << "};\n\n"; // End of register descriptors...
333 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
335 // Loop over all of the register classes... emitting each one.
336 OS << "namespace { // Register classes...\n";
338 // Emit the register enum value arrays for each RegisterClass
339 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
340 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
341 ArrayRef<Record*> Order = RC.getOrder();
343 // Give the register class a legal C name if it's anonymous.
344 std::string Name = RC.getName();
346 // Emit the register list now.
347 OS << " // " << Name << " Register Class...\n"
348 << " static const unsigned " << Name
350 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
351 Record *Reg = Order[i];
352 OS << getQualifiedName(Reg) << ", ";
356 OS << " // " << Name << " Bit set.\n"
357 << " static const unsigned char " << Name
359 BitVectorEmitter BVE;
360 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
361 Record *Reg = Order[i];
362 BVE.add(Target.getRegBank().getReg(Reg)->EnumValue);
370 OS << "MCRegisterClass " << TargetName << "MCRegisterClasses[] = {\n";
372 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
373 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
374 OS << " MCRegisterClass(";
375 if (!RC.Namespace.empty())
376 OS << RC.Namespace << "::";
377 OS << RC.getName() + "RegClassID" << ", "
378 << '\"' << RC.getName() << "\", "
379 << RC.SpillSize/8 << ", "
380 << RC.SpillAlignment/8 << ", "
381 << RC.CopyCost << ", "
382 << RC.Allocatable << ", "
383 << RC.getName() << ", " << RC.getName() << " + "
384 << RC.getOrder().size() << ", "
385 << RC.getName() << "Bits, sizeof(" << RC.getName() << "Bits)"
391 // MCRegisterInfo initialization routine.
392 OS << "static inline void Init" << TargetName
393 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
394 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
395 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
396 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
397 << RegisterClasses.size() << ");\n\n";
399 EmitRegMapping(OS, Regs, false);
404 OS << "} // End llvm namespace \n";
405 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
409 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
410 CodeGenRegBank &RegBank) {
411 EmitSourceFileHeader("Register Information Header Fragment", OS);
413 OS << "\n#ifdef GET_REGINFO_HEADER\n";
414 OS << "#undef GET_REGINFO_HEADER\n";
416 const std::string &TargetName = Target.getName();
417 std::string ClassName = TargetName + "GenRegisterInfo";
419 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
420 OS << "#include <string>\n\n";
422 OS << "namespace llvm {\n\n";
424 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
425 << " explicit " << ClassName
426 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
427 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
428 << " { return false; }\n"
429 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
430 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
431 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
434 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
435 if (!SubRegIndices.empty()) {
436 OS << "\n// Subregister indices\n";
437 std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace");
438 if (!Namespace.empty())
439 OS << "namespace " << Namespace << " {\n";
440 OS << "enum {\n NoSubRegister,\n";
441 for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i)
442 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
443 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
445 if (!Namespace.empty())
449 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
451 if (!RegisterClasses.empty()) {
452 OS << "namespace " << RegisterClasses[0]->Namespace
453 << " { // Register classes\n";
455 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
456 const CodeGenRegisterClass &RC = *RegisterClasses[i];
457 const std::string &Name = RC.getName();
459 // Output the register class definition.
460 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
461 << " " << Name << "Class();\n";
462 if (!RC.AltOrderSelect.empty())
463 OS << " ArrayRef<unsigned> "
464 "getRawAllocationOrder(const MachineFunction&) const;\n";
467 // Output the extern for the instance.
468 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
469 // Output the extern for the pointer to the instance (should remove).
470 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
471 << Name << "RegClass;\n";
473 OS << "} // end of namespace " << TargetName << "\n\n";
475 OS << "} // End llvm namespace \n";
476 OS << "#endif // GET_REGINFO_HEADER\n\n";
480 // runTargetDesc - Output the target register and register file descriptions.
483 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
484 CodeGenRegBank &RegBank){
485 EmitSourceFileHeader("Target Register and Register Classes Information", OS);
487 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
488 OS << "#undef GET_REGINFO_TARGET_DESC\n";
490 OS << "namespace llvm {\n\n";
492 // Get access to MCRegisterClass data.
493 OS << "extern MCRegisterClass " << Target.getName()
494 << "MCRegisterClasses[];\n";
496 // Start out by emitting each of the register classes.
497 ArrayRef<CodeGenRegisterClass*> RegisterClasses = RegBank.getRegClasses();
499 // Collect all registers belonging to any allocatable class.
500 std::set<Record*> AllocatableRegs;
502 // Collect allocatable registers.
503 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
504 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
505 ArrayRef<Record*> Order = RC.getOrder();
508 AllocatableRegs.insert(Order.begin(), Order.end());
511 OS << "namespace { // Register classes...\n";
513 // Emit the ValueType arrays for each RegisterClass
514 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
515 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
517 // Give the register class a legal C name if it's anonymous.
518 std::string Name = RC.getName() + "VTs";
520 // Emit the register list now.
522 << " Register Class Value Types...\n"
523 << " static const EVT " << Name
525 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
526 OS << getEnumName(RC.VTs[i]) << ", ";
527 OS << "MVT::Other\n };\n\n";
529 OS << "} // end anonymous namespace\n\n";
531 // Now that all of the structs have been emitted, emit the instances.
532 if (!RegisterClasses.empty()) {
533 OS << "namespace " << RegisterClasses[0]->Namespace
534 << " { // Register class instances\n";
535 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
536 OS << " " << RegisterClasses[i]->getName() << "Class\t"
537 << RegisterClasses[i]->getName() << "RegClass;\n";
539 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
541 OS << "\n static const TargetRegisterClass* const "
542 << "NullRegClasses[] = { NULL };\n\n";
544 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
546 if (NumSubRegIndices) {
547 // Emit the sub-register classes for each RegisterClass
548 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
549 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
550 std::vector<Record*> SRC(NumSubRegIndices);
551 for (DenseMap<Record*,Record*>::const_iterator
552 i = RC.SubRegClasses.begin(),
553 e = RC.SubRegClasses.end(); i != e; ++i) {
555 unsigned idx = RegBank.getSubRegIndexNo(i->first);
556 SRC.at(idx-1) = i->second;
558 // Find the register class number of i->second for SuperRegClassMap.
559 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
560 const CodeGenRegisterClass &RC2 = *RegisterClasses[rc2];
561 if (RC2.TheDef == i->second) {
562 SuperRegClassMap[rc2].insert(rc);
568 // Give the register class a legal C name if it's anonymous.
569 std::string Name = RC.TheDef->getName();
572 << " Sub-register Classes...\n"
573 << " static const TargetRegisterClass* const "
574 << Name << "SubRegClasses[] = {\n ";
576 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
580 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
587 // Emit the super-register classes for each RegisterClass
588 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
589 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
591 // Give the register class a legal C name if it's anonymous.
592 std::string Name = RC.TheDef->getName();
595 << " Super-register Classes...\n"
596 << " static const TargetRegisterClass* const "
597 << Name << "SuperRegClasses[] = {\n ";
600 std::map<unsigned, std::set<unsigned> >::iterator I =
601 SuperRegClassMap.find(rc);
602 if (I != SuperRegClassMap.end()) {
603 for (std::set<unsigned>::iterator II = I->second.begin(),
604 EE = I->second.end(); II != EE; ++II) {
605 const CodeGenRegisterClass &RC2 = *RegisterClasses[*II];
608 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
613 OS << (!Empty ? ", " : "") << "NULL";
618 // Emit the sub-classes array for each RegisterClass
619 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
620 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
622 // Give the register class a legal C name if it's anonymous.
623 std::string Name = RC.TheDef->getName();
626 << " Register Class sub-classes...\n"
627 << " static const TargetRegisterClass* const "
628 << Name << "Subclasses[] = {\n ";
631 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
632 const CodeGenRegisterClass &RC2 = *RegisterClasses[rc2];
634 // Sub-classes are used to determine if a virtual register can be used
635 // as an instruction operand, or if it must be copied first.
636 if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
638 if (!Empty) OS << ", ";
639 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
643 OS << (!Empty ? ", " : "") << "NULL";
647 // Emit NULL terminated super-class lists.
648 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
649 const CodeGenRegisterClass &RC = *RegisterClasses[rc];
650 ArrayRef<CodeGenRegisterClass*> Supers = RC.getSuperClasses();
652 // Skip classes without supers. We can reuse NullRegClasses.
656 OS << " static const TargetRegisterClass* const "
657 << RC.getName() << "Superclasses[] = {\n";
658 for (unsigned i = 0; i != Supers.size(); ++i)
659 OS << " &" << getQualifiedName(Supers[i]->TheDef) << "RegClass,\n";
660 OS << " NULL\n };\n\n";
664 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
665 const CodeGenRegisterClass &RC = *RegisterClasses[i];
666 OS << RC.getName() << "Class::" << RC.getName()
667 << "Class() : TargetRegisterClass(&"
668 << Target.getName() << "MCRegisterClasses["
669 << RC.getName() + "RegClassID" << "], "
670 << RC.getName() + "VTs" << ", "
671 << RC.getName() + "Subclasses" << ", ";
672 if (RC.getSuperClasses().empty())
673 OS << "NullRegClasses, ";
675 OS << RC.getName() + "Superclasses, ";
676 OS << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
678 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
681 if (!RC.AltOrderSelect.empty()) {
682 OS << "\nstatic inline unsigned " << RC.getName()
683 << "AltOrderSelect(const MachineFunction &MF) {"
684 << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> "
685 << RC.getName() << "Class::"
686 << "getRawAllocationOrder(const MachineFunction &MF) const {\n";
687 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
688 ArrayRef<Record*> Elems = RC.getOrder(oi);
689 OS << " static const unsigned AltOrder" << oi << "[] = {";
690 for (unsigned elem = 0; elem != Elems.size(); ++elem)
691 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
694 OS << " const MCRegisterClass &MCR = " << Target.getName()
695 << "MCRegisterClasses[";
696 if (!RC.Namespace.empty())
697 OS << RC.Namespace << "::";
698 OS << RC.getName() + "RegClassID];"
699 << " static const ArrayRef<unsigned> Order[] = {\n"
700 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
701 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
702 OS << "),\n makeArrayRef(AltOrder" << oi;
703 OS << ")\n };\n const unsigned Select = " << RC.getName()
704 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
705 << ");\n return Order[Select];\n}\n";
712 OS << "\nnamespace {\n";
713 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
714 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
715 OS << " &" << getQualifiedName(RegisterClasses[i]->TheDef)
718 OS << "}\n"; // End of anonymous namespace...
720 // Emit extra information about registers.
721 const std::string &TargetName = Target.getName();
722 OS << "\n static const TargetRegisterInfoDesc "
723 << TargetName << "RegInfoDesc[] = "
724 << "{ // Extra Descriptors\n";
725 OS << " { 0, 0 },\n";
727 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
728 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
729 const CodeGenRegister &Reg = *Regs[i];
731 OS << Reg.CostPerUse << ", "
732 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
734 OS << " };\n"; // End of register descriptors...
737 // Calculate the mapping of subregister+index pairs to physical registers.
738 // This will also create further anonymous indexes.
739 unsigned NamedIndices = RegBank.getNumNamedIndices();
741 // Emit SubRegIndex names, skipping 0
742 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
743 OS << "\n static const char *const " << TargetName
744 << "SubRegIndexTable[] = { \"";
745 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
746 OS << SubRegIndices[i]->getName();
752 // Emit names of the anonymus subreg indexes.
753 if (SubRegIndices.size() > NamedIndices) {
755 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
756 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
764 std::string ClassName = Target.getName() + "GenRegisterInfo";
766 // Emit the subregister + index mapping function based on the information
768 OS << "unsigned " << ClassName
769 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
770 << " switch (RegNo) {\n"
771 << " default:\n return 0;\n";
772 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
773 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
776 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
777 OS << " switch (Index) {\n";
778 OS << " default: return 0;\n";
779 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
780 ie = SRM.end(); ii != ie; ++ii)
781 OS << " case " << getQualifiedName(ii->first)
782 << ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
783 OS << " };\n" << " break;\n";
786 OS << " return 0;\n";
789 OS << "unsigned " << ClassName
790 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
791 << " switch (RegNo) {\n"
792 << " default:\n return 0;\n";
793 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
794 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
797 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
798 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
799 ie = SRM.end(); ii != ie; ++ii)
800 OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
801 << ") return " << getQualifiedName(ii->first) << ";\n";
802 OS << " return 0;\n";
805 OS << " return 0;\n";
808 // Emit composeSubRegIndices
809 OS << "unsigned " << ClassName
810 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
811 << " switch (IdxA) {\n"
812 << " default:\n return IdxB;\n";
813 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
815 for (unsigned j = 0; j != e; ++j) {
816 if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i],
819 OS << " case " << getQualifiedName(SubRegIndices[i])
820 << ": switch(IdxB) {\n default: return IdxB;\n";
823 OS << " case " << getQualifiedName(SubRegIndices[j])
824 << ": return " << getQualifiedName(Comp) << ";\n";
832 // Emit the constructor of the class...
833 OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n";
835 OS << ClassName << "::" << ClassName
836 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
837 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
838 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
839 << " " << TargetName << "SubRegIndexTable) {\n"
840 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
841 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
842 << RegisterClasses.size() << ");\n\n";
844 EmitRegMapping(OS, Regs, true);
848 OS << "} // End llvm namespace \n";
849 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
852 void RegisterInfoEmitter::run(raw_ostream &OS) {
853 CodeGenTarget Target(Records);
854 CodeGenRegBank &RegBank = Target.getRegBank();
855 RegBank.computeDerivedInfo();
857 runEnums(OS, Target, RegBank);
858 runMCDesc(OS, Target, RegBank);
859 runTargetHeader(OS, Target, RegBank);
860 runTargetDesc(OS, Target, RegBank);