1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend is responsible for emitting a description of a target
11 // register file for a code generator. It uses instances of the Register,
12 // RegisterAliases, and RegisterClass classes to gather this information.
14 //===----------------------------------------------------------------------===//
16 #include "RegisterInfoEmitter.h"
17 #include "CodeGenTarget.h"
18 #include "CodeGenRegisters.h"
20 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/Format.h"
27 // runEnums - Print out enum values for all of the registers.
29 RegisterInfoEmitter::runEnums(raw_ostream &OS,
30 CodeGenTarget &Target, CodeGenRegBank &Bank) {
31 const std::vector<CodeGenRegister*> &Registers = Bank.getRegisters();
33 std::string Namespace = Registers[0]->TheDef->getValueAsString("Namespace");
35 EmitSourceFileHeader("Target Register Enum Values", OS);
37 OS << "\n#ifdef GET_REGINFO_ENUM\n";
38 OS << "#undef GET_REGINFO_ENUM\n";
40 OS << "namespace llvm {\n\n";
42 if (!Namespace.empty())
43 OS << "namespace " << Namespace << " {\n";
44 OS << "enum {\n NoRegister,\n";
46 for (unsigned i = 0, e = Registers.size(); i != e; ++i)
47 OS << " " << Registers[i]->getName() << " = " <<
48 Registers[i]->EnumValue << ",\n";
49 assert(Registers.size() == Registers[Registers.size()-1]->EnumValue &&
50 "Register enum value mismatch!");
51 OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
53 if (!Namespace.empty())
56 const std::vector<CodeGenRegisterClass> &RegisterClasses =
57 Target.getRegisterClasses();
58 if (!RegisterClasses.empty()) {
59 OS << "\n// Register classes\n";
60 if (!Namespace.empty())
61 OS << "namespace " << Namespace << " {\n";
63 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
65 OS << " " << RegisterClasses[i].getName() << "RegClassID";
69 if (!Namespace.empty())
73 const std::vector<Record*> RegAltNameIndices = Target.getRegAltNameIndices();
74 // If the only definition is the default NoRegAltName, we don't need to
76 if (RegAltNameIndices.size() > 1) {
77 OS << "\n// Register alternate name indices\n";
78 if (!Namespace.empty())
79 OS << "namespace " << Namespace << " {\n";
81 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i)
82 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n";
83 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n";
85 if (!Namespace.empty())
90 OS << "} // End llvm namespace \n";
91 OS << "#endif // GET_REGINFO_ENUM\n\n";
95 RegisterInfoEmitter::EmitRegMapping(raw_ostream &OS,
96 const std::vector<CodeGenRegister*> &Regs,
99 // Collect all information about dwarf register numbers
100 typedef std::map<Record*, std::vector<int64_t>, LessRecord> DwarfRegNumsMapTy;
101 DwarfRegNumsMapTy DwarfRegNums;
103 // First, just pull all provided information to the map
104 unsigned maxLength = 0;
105 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
106 Record *Reg = Regs[i]->TheDef;
107 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
108 maxLength = std::max((size_t)maxLength, RegNums.size());
109 if (DwarfRegNums.count(Reg))
110 errs() << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
111 << "specified multiple times\n";
112 DwarfRegNums[Reg] = RegNums;
118 // Now we know maximal length of number list. Append -1's, where needed
119 for (DwarfRegNumsMapTy::iterator
120 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
121 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
122 I->second.push_back(-1);
124 // Emit reverse information about the dwarf register numbers.
125 for (unsigned j = 0; j < 2; ++j) {
128 OS << "DwarfFlavour";
133 << " assert(0 && \"Unknown DWARF flavour\");\n"
136 for (unsigned i = 0, e = maxLength; i != e; ++i) {
137 OS << " case " << i << ":\n";
138 for (DwarfRegNumsMapTy::iterator
139 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
140 int DwarfRegNo = I->second[i];
146 OS << "mapDwarfRegToLLVMReg(" << DwarfRegNo << ", "
147 << getQualifiedName(I->first) << ", ";
159 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
160 Record *Reg = Regs[i]->TheDef;
161 const RecordVal *V = Reg->getValue("DwarfAlias");
162 if (!V || !V->getValue())
165 DefInit *DI = dynamic_cast<DefInit*>(V->getValue());
166 Record *Alias = DI->getDef();
167 DwarfRegNums[Reg] = DwarfRegNums[Alias];
170 // Emit information about the dwarf register numbers.
171 for (unsigned j = 0; j < 2; ++j) {
174 OS << "DwarfFlavour";
179 << " assert(0 && \"Unknown DWARF flavour\");\n"
182 for (unsigned i = 0, e = maxLength; i != e; ++i) {
183 OS << " case " << i << ":\n";
184 // Sort by name to get a stable order.
185 for (DwarfRegNumsMapTy::iterator
186 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
187 int RegNo = I->second[i];
191 OS << "mapLLVMRegToDwarfReg(" << getQualifiedName(I->first) << ", "
206 // runMCDesc - Print out MC register descriptions.
209 RegisterInfoEmitter::runMCDesc(raw_ostream &OS, CodeGenTarget &Target,
210 CodeGenRegBank &RegBank) {
211 EmitSourceFileHeader("MC Register Information", OS);
213 OS << "\n#ifdef GET_REGINFO_MC_DESC\n";
214 OS << "#undef GET_REGINFO_MC_DESC\n";
216 std::map<const CodeGenRegister*, CodeGenRegister::Set> Overlaps;
217 RegBank.computeOverlaps(Overlaps);
219 OS << "namespace llvm {\n\n";
221 const std::string &TargetName = Target.getName();
222 std::string ClassName = TargetName + "GenMCRegisterInfo";
223 OS << "struct " << ClassName << " : public MCRegisterInfo {\n"
224 << " explicit " << ClassName << "(const MCRegisterDesc *D);\n";
227 OS << "\nnamespace {\n";
229 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
231 // Emit an overlap list for all registers.
232 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
233 const CodeGenRegister *Reg = Regs[i];
234 const CodeGenRegister::Set &O = Overlaps[Reg];
235 // Move Reg to the front so TRI::getAliasSet can share the list.
236 OS << " const unsigned " << Reg->getName() << "_Overlaps[] = { "
237 << getQualifiedName(Reg->TheDef) << ", ";
238 for (CodeGenRegister::Set::const_iterator I = O.begin(), E = O.end();
241 OS << getQualifiedName((*I)->TheDef) << ", ";
245 // Emit the empty sub-registers list
246 OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
247 // Loop over all of the registers which have sub-registers, emitting the
248 // sub-registers list to memory.
249 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
250 const CodeGenRegister &Reg = *Regs[i];
251 if (Reg.getSubRegs().empty())
253 // getSubRegs() orders by SubRegIndex. We want a topological order.
254 SetVector<CodeGenRegister*> SR;
255 Reg.addSubRegsPreOrder(SR);
256 OS << " const unsigned " << Reg.getName() << "_SubRegsSet[] = { ";
257 for (unsigned j = 0, je = SR.size(); j != je; ++j)
258 OS << getQualifiedName(SR[j]->TheDef) << ", ";
262 // Emit the empty super-registers list
263 OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
264 // Loop over all of the registers which have super-registers, emitting the
265 // super-registers list to memory.
266 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
267 const CodeGenRegister &Reg = *Regs[i];
268 const CodeGenRegister::SuperRegList &SR = Reg.getSuperRegs();
271 OS << " const unsigned " << Reg.getName() << "_SuperRegsSet[] = { ";
272 for (unsigned j = 0, je = SR.size(); j != je; ++j)
273 OS << getQualifiedName(SR[j]->TheDef) << ", ";
276 OS << "}\n"; // End of anonymous namespace...
278 OS << "\nMCRegisterDesc " << TargetName
279 << "RegDesc[] = { // Descriptors\n";
280 OS << " { \"NOREG\",\t0,\t0,\t0 },\n";
282 // Now that register alias and sub-registers sets have been emitted, emit the
283 // register descriptors now.
284 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
285 const CodeGenRegister &Reg = *Regs[i];
287 OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t";
288 if (!Reg.getSubRegs().empty())
289 OS << Reg.getName() << "_SubRegsSet,\t";
291 OS << "Empty_SubRegsSet,\t";
292 if (!Reg.getSuperRegs().empty())
293 OS << Reg.getName() << "_SuperRegsSet";
295 OS << "Empty_SuperRegsSet";
298 OS << "};\n\n"; // End of register descriptors...
300 const std::vector<CodeGenRegisterClass> &RegisterClasses =
301 Target.getRegisterClasses();
303 // Loop over all of the register classes... emitting each one.
304 OS << "namespace { // Register classes...\n";
306 // Emit the register enum value arrays for each RegisterClass
307 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
308 const CodeGenRegisterClass &RC = RegisterClasses[rc];
309 ArrayRef<Record*> Order = RC.getOrder();
311 // Give the register class a legal C name if it's anonymous.
312 std::string Name = RC.getName();
314 // Emit the register list now.
315 OS << " // " << Name << " Register Class...\n"
316 << " static const unsigned " << Name
318 for (unsigned i = 0, e = Order.size(); i != e; ++i) {
319 Record *Reg = Order[i];
320 OS << getQualifiedName(Reg) << ", ";
326 OS << "MCRegisterClass " << TargetName << "MCRegisterClasses[] = {\n";
328 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
329 const CodeGenRegisterClass &RC = RegisterClasses[rc];
330 OS << " MCRegisterClass(";
331 if (!RC.Namespace.empty())
332 OS << RC.Namespace << "::";
333 OS << RC.getName() + "RegClassID" << ", "
334 << '\"' << RC.getName() << "\", "
335 << RC.SpillSize/8 << ", "
336 << RC.SpillAlignment/8 << ", "
337 << RC.CopyCost << ", "
338 << RC.Allocatable << ", "
339 << RC.getName() << ", " << RC.getName() << " + "
340 << RC.getOrder().size()
346 // MCRegisterInfo initialization routine.
347 OS << "static inline void Init" << TargetName
348 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
349 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n";
350 OS << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
351 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
352 << RegisterClasses.size() << ");\n\n";
354 EmitRegMapping(OS, Regs, false);
359 OS << "} // End llvm namespace \n";
360 OS << "#endif // GET_REGINFO_MC_DESC\n\n";
364 RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
365 CodeGenRegBank &RegBank) {
366 EmitSourceFileHeader("Register Information Header Fragment", OS);
368 OS << "\n#ifdef GET_REGINFO_HEADER\n";
369 OS << "#undef GET_REGINFO_HEADER\n";
371 const std::string &TargetName = Target.getName();
372 std::string ClassName = TargetName + "GenRegisterInfo";
374 OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n";
375 OS << "#include <string>\n\n";
377 OS << "namespace llvm {\n\n";
379 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
380 << " explicit " << ClassName
381 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
382 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
383 << " { return false; }\n"
384 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
385 << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n"
386 << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n"
389 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
390 if (!SubRegIndices.empty()) {
391 OS << "\n// Subregister indices\n";
392 std::string Namespace = SubRegIndices[0]->getValueAsString("Namespace");
393 if (!Namespace.empty())
394 OS << "namespace " << Namespace << " {\n";
395 OS << "enum {\n NoSubRegister,\n";
396 for (unsigned i = 0, e = RegBank.getNumNamedIndices(); i != e; ++i)
397 OS << " " << SubRegIndices[i]->getName() << ",\t// " << i+1 << "\n";
398 OS << " NUM_TARGET_NAMED_SUBREGS = " << SubRegIndices.size()+1 << "\n";
400 if (!Namespace.empty())
404 const std::vector<CodeGenRegisterClass> &RegisterClasses =
405 Target.getRegisterClasses();
407 if (!RegisterClasses.empty()) {
408 OS << "namespace " << RegisterClasses[0].Namespace
409 << " { // Register classes\n";
411 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
412 const CodeGenRegisterClass &RC = RegisterClasses[i];
413 const std::string &Name = RC.getName();
415 // Output the register class definition.
416 OS << " struct " << Name << "Class : public TargetRegisterClass {\n"
417 << " " << Name << "Class();\n";
418 if (!RC.AltOrderSelect.empty())
419 OS << " ArrayRef<unsigned> "
420 "getRawAllocationOrder(const MachineFunction&) const;\n";
423 // Output the extern for the instance.
424 OS << " extern " << Name << "Class\t" << Name << "RegClass;\n";
425 // Output the extern for the pointer to the instance (should remove).
426 OS << " static TargetRegisterClass * const "<< Name <<"RegisterClass = &"
427 << Name << "RegClass;\n";
429 OS << "} // end of namespace " << TargetName << "\n\n";
431 OS << "} // End llvm namespace \n";
432 OS << "#endif // GET_REGINFO_HEADER\n\n";
436 // runTargetDesc - Output the target register and register file descriptions.
439 RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
440 CodeGenRegBank &RegBank){
441 EmitSourceFileHeader("Target Register and Register Classes Information", OS);
443 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n";
444 OS << "#undef GET_REGINFO_TARGET_DESC\n";
446 OS << "namespace llvm {\n\n";
448 // Get access to MCRegisterClass data.
449 OS << "extern MCRegisterClass " << Target.getName()
450 << "MCRegisterClasses[];\n";
452 // Start out by emitting each of the register classes.
453 const std::vector<CodeGenRegisterClass> &RegisterClasses =
454 Target.getRegisterClasses();
456 // Collect all registers belonging to any allocatable class.
457 std::set<Record*> AllocatableRegs;
459 // Collect allocatable registers.
460 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
461 const CodeGenRegisterClass &RC = RegisterClasses[rc];
462 ArrayRef<Record*> Order = RC.getOrder();
465 AllocatableRegs.insert(Order.begin(), Order.end());
468 OS << "namespace { // Register classes...\n";
470 // Emit the ValueType arrays for each RegisterClass
471 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
472 const CodeGenRegisterClass &RC = RegisterClasses[rc];
474 // Give the register class a legal C name if it's anonymous.
475 std::string Name = RC.getName() + "VTs";
477 // Emit the register list now.
479 << " Register Class Value Types...\n"
480 << " static const EVT " << Name
482 for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
483 OS << getEnumName(RC.VTs[i]) << ", ";
484 OS << "MVT::Other\n };\n\n";
486 OS << "} // end anonymous namespace\n\n";
488 // Now that all of the structs have been emitted, emit the instances.
489 if (!RegisterClasses.empty()) {
490 OS << "namespace " << RegisterClasses[0].Namespace
491 << " { // Register class instances\n";
492 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
493 OS << " " << RegisterClasses[i].getName() << "Class\t"
494 << RegisterClasses[i].getName() << "RegClass;\n";
496 std::map<unsigned, std::set<unsigned> > SuperClassMap;
497 std::map<unsigned, std::set<unsigned> > SuperRegClassMap;
500 unsigned NumSubRegIndices = RegBank.getSubRegIndices().size();
502 if (NumSubRegIndices) {
503 // Emit the sub-register classes for each RegisterClass
504 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
505 const CodeGenRegisterClass &RC = RegisterClasses[rc];
506 std::vector<Record*> SRC(NumSubRegIndices);
507 for (DenseMap<Record*,Record*>::const_iterator
508 i = RC.SubRegClasses.begin(),
509 e = RC.SubRegClasses.end(); i != e; ++i) {
511 unsigned idx = RegBank.getSubRegIndexNo(i->first);
512 SRC.at(idx-1) = i->second;
514 // Find the register class number of i->second for SuperRegClassMap.
515 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
516 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
517 if (RC2.TheDef == i->second) {
518 SuperRegClassMap[rc2].insert(rc);
524 // Give the register class a legal C name if it's anonymous.
525 std::string Name = RC.TheDef->getName();
528 << " Sub-register Classes...\n"
529 << " static const TargetRegisterClass* const "
530 << Name << "SubRegClasses[] = {\n ";
532 for (unsigned idx = 0; idx != NumSubRegIndices; ++idx) {
536 OS << "&" << getQualifiedName(SRC[idx]) << "RegClass";
543 // Emit the super-register classes for each RegisterClass
544 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
545 const CodeGenRegisterClass &RC = RegisterClasses[rc];
547 // Give the register class a legal C name if it's anonymous.
548 std::string Name = RC.TheDef->getName();
551 << " Super-register Classes...\n"
552 << " static const TargetRegisterClass* const "
553 << Name << "SuperRegClasses[] = {\n ";
556 std::map<unsigned, std::set<unsigned> >::iterator I =
557 SuperRegClassMap.find(rc);
558 if (I != SuperRegClassMap.end()) {
559 for (std::set<unsigned>::iterator II = I->second.begin(),
560 EE = I->second.end(); II != EE; ++II) {
561 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
564 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
569 OS << (!Empty ? ", " : "") << "NULL";
573 // No subregindices in this target
574 OS << " static const TargetRegisterClass* const "
575 << "NullRegClasses[] = { NULL };\n\n";
578 // Emit the sub-classes array for each RegisterClass
579 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
580 const CodeGenRegisterClass &RC = RegisterClasses[rc];
582 // Give the register class a legal C name if it's anonymous.
583 std::string Name = RC.TheDef->getName();
586 << " Register Class sub-classes...\n"
587 << " static const TargetRegisterClass* const "
588 << Name << "Subclasses[] = {\n ";
591 for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
592 const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
594 // Sub-classes are used to determine if a virtual register can be used
595 // as an instruction operand, or if it must be copied first.
596 if (rc == rc2 || !RC.hasSubClass(&RC2)) continue;
598 if (!Empty) OS << ", ";
599 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
602 std::map<unsigned, std::set<unsigned> >::iterator SCMI =
603 SuperClassMap.find(rc2);
604 if (SCMI == SuperClassMap.end()) {
605 SuperClassMap.insert(std::make_pair(rc2, std::set<unsigned>()));
606 SCMI = SuperClassMap.find(rc2);
608 SCMI->second.insert(rc);
611 OS << (!Empty ? ", " : "") << "NULL";
615 for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
616 const CodeGenRegisterClass &RC = RegisterClasses[rc];
618 // Give the register class a legal C name if it's anonymous.
619 std::string Name = RC.TheDef->getName();
622 << " Register Class super-classes...\n"
623 << " static const TargetRegisterClass* const "
624 << Name << "Superclasses[] = {\n ";
627 std::map<unsigned, std::set<unsigned> >::iterator I =
628 SuperClassMap.find(rc);
629 if (I != SuperClassMap.end()) {
630 for (std::set<unsigned>::iterator II = I->second.begin(),
631 EE = I->second.end(); II != EE; ++II) {
632 const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
633 if (!Empty) OS << ", ";
634 OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
639 OS << (!Empty ? ", " : "") << "NULL";
644 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
645 const CodeGenRegisterClass &RC = RegisterClasses[i];
646 OS << RC.getName() << "Class::" << RC.getName()
647 << "Class() : TargetRegisterClass(&"
648 << Target.getName() << "MCRegisterClasses["
649 << RC.getName() + "RegClassID" << "], "
650 << RC.getName() + "VTs" << ", "
651 << RC.getName() + "Subclasses" << ", "
652 << RC.getName() + "Superclasses" << ", "
653 << (NumSubRegIndices ? RC.getName() + "Sub" : std::string("Null"))
655 << (NumSubRegIndices ? RC.getName() + "Super" : std::string("Null"))
658 if (!RC.AltOrderSelect.empty()) {
659 OS << "\nstatic inline unsigned " << RC.getName()
660 << "AltOrderSelect(const MachineFunction &MF) {"
661 << RC.AltOrderSelect << "}\n\nArrayRef<unsigned> "
662 << RC.getName() << "Class::"
663 << "getRawAllocationOrder(const MachineFunction &MF) const {\n";
664 for (unsigned oi = 1 , oe = RC.getNumOrders(); oi != oe; ++oi) {
665 ArrayRef<Record*> Elems = RC.getOrder(oi);
666 OS << " static const unsigned AltOrder" << oi << "[] = {";
667 for (unsigned elem = 0; elem != Elems.size(); ++elem)
668 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]);
671 OS << " const MCRegisterClass &MCR = " << Target.getName()
672 << "MCRegisterClasses[";
673 if (!RC.Namespace.empty())
674 OS << RC.Namespace << "::";
675 OS << RC.getName() + "RegClassID];"
676 << " static const ArrayRef<unsigned> Order[] = {\n"
677 << " makeArrayRef(MCR.begin(), MCR.getNumRegs()";
678 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi)
679 OS << "),\n makeArrayRef(AltOrder" << oi;
680 OS << ")\n };\n const unsigned Select = " << RC.getName()
681 << "AltOrderSelect(MF);\n assert(Select < " << RC.getNumOrders()
682 << ");\n return Order[Select];\n}\n";
689 OS << "\nnamespace {\n";
690 OS << " const TargetRegisterClass* const RegisterClasses[] = {\n";
691 for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
692 OS << " &" << getQualifiedName(RegisterClasses[i].TheDef)
695 OS << "}\n"; // End of anonymous namespace...
697 // Emit extra information about registers.
698 const std::string &TargetName = Target.getName();
699 OS << "\n static const TargetRegisterInfoDesc "
700 << TargetName << "RegInfoDesc[] = "
701 << "{ // Extra Descriptors\n";
702 OS << " { 0, 0 },\n";
704 const std::vector<CodeGenRegister*> &Regs = RegBank.getRegisters();
705 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
706 const CodeGenRegister &Reg = *Regs[i];
708 OS << Reg.CostPerUse << ", "
709 << int(AllocatableRegs.count(Reg.TheDef)) << " },\n";
711 OS << " };\n"; // End of register descriptors...
714 // Calculate the mapping of subregister+index pairs to physical registers.
715 // This will also create further anonymous indexes.
716 unsigned NamedIndices = RegBank.getNumNamedIndices();
718 // Emit SubRegIndex names, skipping 0
719 const std::vector<Record*> &SubRegIndices = RegBank.getSubRegIndices();
720 OS << "\n static const char *const " << TargetName
721 << "SubRegIndexTable[] = { \"";
722 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
723 OS << SubRegIndices[i]->getName();
729 // Emit names of the anonymus subreg indexes.
730 if (SubRegIndices.size() > NamedIndices) {
732 for (unsigned i = NamedIndices, e = SubRegIndices.size(); i != e; ++i) {
733 OS << "\n " << SubRegIndices[i]->getName() << " = " << i+1;
741 std::string ClassName = Target.getName() + "GenRegisterInfo";
743 // Emit the subregister + index mapping function based on the information
745 OS << "unsigned " << ClassName
746 << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
747 << " switch (RegNo) {\n"
748 << " default:\n return 0;\n";
749 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
750 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
753 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
754 OS << " switch (Index) {\n";
755 OS << " default: return 0;\n";
756 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
757 ie = SRM.end(); ii != ie; ++ii)
758 OS << " case " << getQualifiedName(ii->first)
759 << ": return " << getQualifiedName(ii->second->TheDef) << ";\n";
760 OS << " };\n" << " break;\n";
763 OS << " return 0;\n";
766 OS << "unsigned " << ClassName
767 << "::getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const {\n"
768 << " switch (RegNo) {\n"
769 << " default:\n return 0;\n";
770 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
771 const CodeGenRegister::SubRegMap &SRM = Regs[i]->getSubRegs();
774 OS << " case " << getQualifiedName(Regs[i]->TheDef) << ":\n";
775 for (CodeGenRegister::SubRegMap::const_iterator ii = SRM.begin(),
776 ie = SRM.end(); ii != ie; ++ii)
777 OS << " if (SubRegNo == " << getQualifiedName(ii->second->TheDef)
778 << ") return " << getQualifiedName(ii->first) << ";\n";
779 OS << " return 0;\n";
782 OS << " return 0;\n";
785 // Emit composeSubRegIndices
786 OS << "unsigned " << ClassName
787 << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n"
788 << " switch (IdxA) {\n"
789 << " default:\n return IdxB;\n";
790 for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) {
792 for (unsigned j = 0; j != e; ++j) {
793 if (Record *Comp = RegBank.getCompositeSubRegIndex(SubRegIndices[i],
796 OS << " case " << getQualifiedName(SubRegIndices[i])
797 << ": switch(IdxB) {\n default: return IdxB;\n";
800 OS << " case " << getQualifiedName(SubRegIndices[j])
801 << ": return " << getQualifiedName(Comp) << ";\n";
809 // Emit the constructor of the class...
810 OS << "extern MCRegisterDesc " << TargetName << "RegDesc[];\n";
812 OS << ClassName << "::" << ClassName
813 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
814 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
815 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
816 << " " << TargetName << "SubRegIndexTable) {\n"
817 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
818 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
819 << RegisterClasses.size() << ");\n\n";
821 EmitRegMapping(OS, Regs, true);
825 OS << "} // End llvm namespace \n";
826 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n";
829 void RegisterInfoEmitter::run(raw_ostream &OS) {
830 CodeGenTarget Target(Records);
831 CodeGenRegBank &RegBank = Target.getRegBank();
832 RegBank.computeDerivedInfo();
834 runEnums(OS, Target, RegBank);
835 runMCDesc(OS, Target, RegBank);
836 runTargetHeader(OS, Target, RegBank);
837 runTargetDesc(OS, Target, RegBank);