1 //===- SubtargetEmitter.cpp - Generate subtarget enumerations -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This tablegen backend emits subtarget enumerations.
12 //===----------------------------------------------------------------------===//
14 #include "CodeGenTarget.h"
15 #include "CodeGenSchedule.h"
16 #include "llvm/ADT/StringExtras.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/MC/MCInstrItineraries.h"
19 #include "llvm/TableGen/Error.h"
20 #include "llvm/TableGen/Record.h"
21 #include "llvm/TableGen/TableGenBackend.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/Format.h"
31 class SubtargetEmitter {
32 // Each processor has a SchedClassDesc table with an entry for each SchedClass.
33 // The SchedClassDesc table indexes into a global write resource table, write
34 // latency table, and read advance table.
35 struct SchedClassTables {
36 std::vector<std::vector<MCSchedClassDesc> > ProcSchedClasses;
37 std::vector<MCWriteProcResEntry> WriteProcResources;
38 std::vector<MCWriteLatencyEntry> WriteLatencies;
39 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
41 // Reserve an invalid entry at index 0
43 ProcSchedClasses.resize(1);
44 WriteProcResources.resize(1);
45 WriteLatencies.resize(1);
46 ReadAdvanceEntries.resize(1);
50 struct LessWriteProcResources {
51 bool operator()(const MCWriteProcResEntry &LHS,
52 const MCWriteProcResEntry &RHS) {
53 return LHS.ProcResourceIdx < RHS.ProcResourceIdx;
57 RecordKeeper &Records;
58 CodeGenSchedModels &SchedModels;
61 void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits);
62 unsigned FeatureKeyValues(raw_ostream &OS);
63 unsigned CPUKeyValues(raw_ostream &OS);
64 void FormItineraryStageString(const std::string &Names,
65 Record *ItinData, std::string &ItinString,
67 void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString,
68 unsigned &NOperandCycles);
69 void FormItineraryBypassString(const std::string &Names,
71 std::string &ItinString, unsigned NOperandCycles);
72 void EmitStageAndOperandCycleData(raw_ostream &OS,
73 std::vector<std::vector<InstrItinerary> >
75 void EmitItineraries(raw_ostream &OS,
76 std::vector<std::vector<InstrItinerary> >
78 void EmitProcessorProp(raw_ostream &OS, const Record *R, const char *Name,
80 void EmitProcessorResources(const CodeGenProcModel &ProcModel,
82 Record *FindWriteResources(Record *WriteDef,
83 const CodeGenProcModel &ProcModel);
84 Record *FindReadAdvance(Record *ReadDef, const CodeGenProcModel &ProcModel);
85 void GenSchedClassTables(const CodeGenProcModel &ProcModel,
86 SchedClassTables &SchedTables);
87 void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
88 void EmitProcessorModels(raw_ostream &OS);
89 void EmitProcessorLookup(raw_ostream &OS);
90 void EmitSchedModel(raw_ostream &OS);
91 void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
95 SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT):
96 Records(R), SchedModels(TGT.getSchedModels()), Target(TGT.getName()) {}
98 void run(raw_ostream &o);
101 } // End anonymous namespace
104 // Enumeration - Emit the specified class as an enumeration.
106 void SubtargetEmitter::Enumeration(raw_ostream &OS,
107 const char *ClassName,
109 // Get all records of class and sort
110 std::vector<Record*> DefList = Records.getAllDerivedDefinitions(ClassName);
111 std::sort(DefList.begin(), DefList.end(), LessRecord());
113 unsigned N = DefList.size();
117 errs() << "Too many (> 64) subtarget features!\n";
121 OS << "namespace " << Target << " {\n";
123 // For bit flag enumerations with more than 32 items, emit constants.
124 // Emit an enum for everything else.
125 if (isBits && N > 32) {
127 for (unsigned i = 0; i < N; i++) {
129 Record *Def = DefList[i];
131 // Get and emit name and expression (1 << i)
132 OS << " const uint64_t " << Def->getName() << " = 1ULL << " << i << ";\n";
139 for (unsigned i = 0; i < N;) {
141 Record *Def = DefList[i];
144 OS << " " << Def->getName();
146 // If bit flags then emit expression (1 << i)
147 if (isBits) OS << " = " << " 1ULL << " << i;
149 // Depending on 'if more in the list' emit comma
150 if (++i < N) OS << ",";
163 // FeatureKeyValues - Emit data of all the subtarget features. Used by the
166 unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) {
167 // Gather and sort all the features
168 std::vector<Record*> FeatureList =
169 Records.getAllDerivedDefinitions("SubtargetFeature");
171 if (FeatureList.empty())
174 std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName());
176 // Begin feature table
177 OS << "// Sorted (by key) array of values for CPU features.\n"
178 << "extern const llvm::SubtargetFeatureKV " << Target
179 << "FeatureKV[] = {\n";
182 unsigned NumFeatures = 0;
183 for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) {
185 Record *Feature = FeatureList[i];
187 const std::string &Name = Feature->getName();
188 const std::string &CommandLineName = Feature->getValueAsString("Name");
189 const std::string &Desc = Feature->getValueAsString("Desc");
191 if (CommandLineName.empty()) continue;
193 // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in }
195 << "\"" << CommandLineName << "\", "
196 << "\"" << Desc << "\", "
197 << Target << "::" << Name << ", ";
199 const std::vector<Record*> &ImpliesList =
200 Feature->getValueAsListOfDefs("Implies");
202 if (ImpliesList.empty()) {
205 for (unsigned j = 0, M = ImpliesList.size(); j < M;) {
206 OS << Target << "::" << ImpliesList[j]->getName();
207 if (++j < M) OS << " | ";
214 // Depending on 'if more in the list' emit comma
215 if ((i + 1) < N) OS << ",";
227 // CPUKeyValues - Emit data of all the subtarget processors. Used by command
230 unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) {
231 // Gather and sort processor information
232 std::vector<Record*> ProcessorList =
233 Records.getAllDerivedDefinitions("Processor");
234 std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
236 // Begin processor table
237 OS << "// Sorted (by key) array of values for CPU subtype.\n"
238 << "extern const llvm::SubtargetFeatureKV " << Target
239 << "SubTypeKV[] = {\n";
241 // For each processor
242 for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
244 Record *Processor = ProcessorList[i];
246 const std::string &Name = Processor->getValueAsString("Name");
247 const std::vector<Record*> &FeatureList =
248 Processor->getValueAsListOfDefs("Features");
250 // Emit as { "cpu", "description", f1 | f2 | ... fn },
252 << "\"" << Name << "\", "
253 << "\"Select the " << Name << " processor\", ";
255 if (FeatureList.empty()) {
258 for (unsigned j = 0, M = FeatureList.size(); j < M;) {
259 OS << Target << "::" << FeatureList[j]->getName();
260 if (++j < M) OS << " | ";
264 // The "0" is for the "implies" section of this data structure.
267 // Depending on 'if more in the list' emit comma
268 if (++i < N) OS << ",";
273 // End processor table
276 return ProcessorList.size();
280 // FormItineraryStageString - Compose a string containing the stage
281 // data initialization for the specified itinerary. N is the number
284 void SubtargetEmitter::FormItineraryStageString(const std::string &Name,
286 std::string &ItinString,
289 const std::vector<Record*> &StageList =
290 ItinData->getValueAsListOfDefs("Stages");
293 unsigned N = NStages = StageList.size();
294 for (unsigned i = 0; i < N;) {
296 const Record *Stage = StageList[i];
298 // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind }
299 int Cycles = Stage->getValueAsInt("Cycles");
300 ItinString += " { " + itostr(Cycles) + ", ";
303 const std::vector<Record*> &UnitList = Stage->getValueAsListOfDefs("Units");
306 for (unsigned j = 0, M = UnitList.size(); j < M;) {
307 // Add name and bitwise or
308 ItinString += Name + "FU::" + UnitList[j]->getName();
309 if (++j < M) ItinString += " | ";
312 int TimeInc = Stage->getValueAsInt("TimeInc");
313 ItinString += ", " + itostr(TimeInc);
315 int Kind = Stage->getValueAsInt("Kind");
316 ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(Kind);
320 if (++i < N) ItinString += ", ";
325 // FormItineraryOperandCycleString - Compose a string containing the
326 // operand cycle initialization for the specified itinerary. N is the
327 // number of operands that has cycles specified.
329 void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData,
330 std::string &ItinString, unsigned &NOperandCycles) {
331 // Get operand cycle list
332 const std::vector<int64_t> &OperandCycleList =
333 ItinData->getValueAsListOfInts("OperandCycles");
335 // For each operand cycle
336 unsigned N = NOperandCycles = OperandCycleList.size();
337 for (unsigned i = 0; i < N;) {
338 // Next operand cycle
339 const int OCycle = OperandCycleList[i];
341 ItinString += " " + itostr(OCycle);
342 if (++i < N) ItinString += ", ";
346 void SubtargetEmitter::FormItineraryBypassString(const std::string &Name,
348 std::string &ItinString,
349 unsigned NOperandCycles) {
350 const std::vector<Record*> &BypassList =
351 ItinData->getValueAsListOfDefs("Bypasses");
352 unsigned N = BypassList.size();
355 ItinString += Name + "Bypass::" + BypassList[i]->getName();
356 if (++i < NOperandCycles) ItinString += ", ";
358 for (; i < NOperandCycles;) {
360 if (++i < NOperandCycles) ItinString += ", ";
365 // EmitStageAndOperandCycleData - Generate unique itinerary stages and operand
366 // cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed
367 // by CodeGenSchedClass::Index.
369 void SubtargetEmitter::
370 EmitStageAndOperandCycleData(raw_ostream &OS,
371 std::vector<std::vector<InstrItinerary> >
374 // Multiple processor models may share an itinerary record. Emit it once.
375 SmallPtrSet<Record*, 8> ItinsDefSet;
377 // Emit functional units for all the itineraries.
378 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
379 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
381 if (!ItinsDefSet.insert(PI->ItinsDef))
384 std::vector<Record*> FUs = PI->ItinsDef->getValueAsListOfDefs("FU");
388 const std::string &Name = PI->ItinsDef->getName();
389 OS << "\n// Functional units for \"" << Name << "\"\n"
390 << "namespace " << Name << "FU {\n";
392 for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j)
393 OS << " const unsigned " << FUs[j]->getName()
394 << " = 1 << " << j << ";\n";
398 std::vector<Record*> BPs = PI->ItinsDef->getValueAsListOfDefs("BP");
400 OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name
401 << "\"\n" << "namespace " << Name << "Bypass {\n";
403 OS << " const unsigned NoBypass = 0;\n";
404 for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j)
405 OS << " const unsigned " << BPs[j]->getName()
406 << " = 1 << " << j << ";\n";
412 // Begin stages table
413 std::string StageTable = "\nextern const llvm::InstrStage " + Target +
415 StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n";
417 // Begin operand cycle table
418 std::string OperandCycleTable = "extern const unsigned " + Target +
419 "OperandCycles[] = {\n";
420 OperandCycleTable += " 0, // No itinerary\n";
422 // Begin pipeline bypass table
423 std::string BypassTable = "extern const unsigned " + Target +
424 "ForwardingPaths[] = {\n";
425 BypassTable += " 0, // No itinerary\n";
427 // For each Itinerary across all processors, add a unique entry to the stages,
428 // operand cycles, and pipepine bypess tables. Then add the new Itinerary
429 // object with computed offsets to the ProcItinLists result.
430 unsigned StageCount = 1, OperandCycleCount = 1;
431 std::map<std::string, unsigned> ItinStageMap, ItinOperandMap;
432 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
433 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
434 const CodeGenProcModel &ProcModel = *PI;
436 // Add process itinerary to the list.
437 ProcItinLists.resize(ProcItinLists.size()+1);
439 // If this processor defines no itineraries, then leave the itinerary list
441 std::vector<InstrItinerary> &ItinList = ProcItinLists.back();
442 if (ProcModel.ItinDefList.empty())
445 // Reserve index==0 for NoItinerary.
446 ItinList.resize(SchedModels.numItineraryClasses()+1);
448 const std::string &Name = ProcModel.ItinsDef->getName();
450 // For each itinerary data
451 for (unsigned SchedClassIdx = 0,
452 SchedClassEnd = ProcModel.ItinDefList.size();
453 SchedClassIdx < SchedClassEnd; ++SchedClassIdx) {
455 // Next itinerary data
456 Record *ItinData = ProcModel.ItinDefList[SchedClassIdx];
458 // Get string and stage count
459 std::string ItinStageString;
460 unsigned NStages = 0;
462 FormItineraryStageString(Name, ItinData, ItinStageString, NStages);
464 // Get string and operand cycle count
465 std::string ItinOperandCycleString;
466 unsigned NOperandCycles = 0;
467 std::string ItinBypassString;
469 FormItineraryOperandCycleString(ItinData, ItinOperandCycleString,
472 FormItineraryBypassString(Name, ItinData, ItinBypassString,
476 // Check to see if stage already exists and create if it doesn't
477 unsigned FindStage = 0;
479 FindStage = ItinStageMap[ItinStageString];
480 if (FindStage == 0) {
481 // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices
482 StageTable += ItinStageString + ", // " + itostr(StageCount);
484 StageTable += "-" + itostr(StageCount + NStages - 1);
486 // Record Itin class number.
487 ItinStageMap[ItinStageString] = FindStage = StageCount;
488 StageCount += NStages;
492 // Check to see if operand cycle already exists and create if it doesn't
493 unsigned FindOperandCycle = 0;
494 if (NOperandCycles > 0) {
495 std::string ItinOperandString = ItinOperandCycleString+ItinBypassString;
496 FindOperandCycle = ItinOperandMap[ItinOperandString];
497 if (FindOperandCycle == 0) {
498 // Emit as cycle, // index
499 OperandCycleTable += ItinOperandCycleString + ", // ";
500 std::string OperandIdxComment = itostr(OperandCycleCount);
501 if (NOperandCycles > 1)
502 OperandIdxComment += "-"
503 + itostr(OperandCycleCount + NOperandCycles - 1);
504 OperandCycleTable += OperandIdxComment + "\n";
505 // Record Itin class number.
506 ItinOperandMap[ItinOperandCycleString] =
507 FindOperandCycle = OperandCycleCount;
508 // Emit as bypass, // index
509 BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n";
510 OperandCycleCount += NOperandCycles;
514 // Set up itinerary as location and location + stage count
515 int NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0;
516 InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages,
518 FindOperandCycle + NOperandCycles};
520 // Inject - empty slots will be 0, 0
521 ItinList[SchedClassIdx] = Intinerary;
526 StageTable += " { 0, 0, 0, llvm::InstrStage::Required } // End stages\n";
527 StageTable += "};\n";
529 // Closing operand cycles
530 OperandCycleTable += " 0 // End operand cycles\n";
531 OperandCycleTable += "};\n";
533 BypassTable += " 0 // End bypass tables\n";
534 BypassTable += "};\n";
538 OS << OperandCycleTable;
543 // EmitProcessorData - Generate data for processor itineraries that were
544 // computed during EmitStageAndOperandCycleData(). ProcItinLists lists all
545 // Itineraries for each processor. The Itinerary lists are indexed on
546 // CodeGenSchedClass::Index.
548 void SubtargetEmitter::
549 EmitItineraries(raw_ostream &OS,
550 std::vector<std::vector<InstrItinerary> > &ProcItinLists) {
552 // Multiple processor models may share an itinerary record. Emit it once.
553 SmallPtrSet<Record*, 8> ItinsDefSet;
555 // For each processor's machine model
556 std::vector<std::vector<InstrItinerary> >::iterator
557 ProcItinListsIter = ProcItinLists.begin();
558 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
559 PE = SchedModels.procModelEnd(); PI != PE; ++PI, ++ProcItinListsIter) {
561 Record *ItinsDef = PI->ItinsDef;
562 if (!ItinsDefSet.insert(ItinsDef))
565 // Get processor itinerary name
566 const std::string &Name = ItinsDef->getName();
568 // Get the itinerary list for the processor.
569 assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator");
570 std::vector<InstrItinerary> &ItinList = *ProcItinListsIter;
573 OS << "static const llvm::InstrItinerary ";
574 if (ItinList.empty()) {
575 OS << '*' << Name << " = 0;\n";
579 // Begin processor itinerary table
580 OS << Name << "[] = {\n";
582 // For each itinerary class in CodeGenSchedClass::Index order.
583 for (unsigned j = 0, M = ItinList.size(); j < M; ++j) {
584 InstrItinerary &Intinerary = ItinList[j];
586 // Emit Itinerary in the form of
587 // { firstStage, lastStage, firstCycle, lastCycle } // index
589 Intinerary.NumMicroOps << ", " <<
590 Intinerary.FirstStage << ", " <<
591 Intinerary.LastStage << ", " <<
592 Intinerary.FirstOperandCycle << ", " <<
593 Intinerary.LastOperandCycle << " }" <<
594 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n";
596 // End processor itinerary table
597 OS << " { 0, ~0U, ~0U, ~0U, ~0U } // end marker\n";
602 // Emit either the value defined in the TableGen Record, or the default
603 // value defined in the C++ header. The Record is null if the processor does not
605 void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R,
606 const char *Name, char Separator) {
608 int V = R ? R->getValueAsInt(Name) : -1;
610 OS << V << Separator << " // " << Name;
612 OS << "MCSchedModel::Default" << Name << Separator;
616 void SubtargetEmitter::EmitProcessorResources(const CodeGenProcModel &ProcModel,
618 char Sep = ProcModel.ProcResourceDefs.empty() ? ' ' : ',';
620 OS << "\n// {Name, NumUnits, SuperIdx}\n";
621 OS << "static const llvm::MCProcResourceDesc "
622 << ProcModel.ModelName << "ProcResources" << "[] = {\n"
623 << " {DBGFIELD(\"InvalidUnit\") 0, 0}" << Sep << "\n";
625 for (unsigned i = 0, e = ProcModel.ProcResourceDefs.size(); i < e; ++i) {
626 Record *PRDef = ProcModel.ProcResourceDefs[i];
629 unsigned SuperIdx = 0;
630 Record *SuperDef = 0;
631 if (PRDef->getValueInit("Super")->isComplete()) {
633 SchedModels.findProcResUnits(PRDef->getValueAsDef("Super"), ProcModel);
634 SuperIdx = ProcModel.getProcResourceIdx(SuperDef);
636 // Emit the ProcResourceDesc
639 OS << " {DBGFIELD(\"" << PRDef->getName() << "\") ";
640 if (PRDef->getName().size() < 15)
641 OS.indent(15 - PRDef->getName().size());
642 OS << PRDef->getValueAsInt("NumUnits") << ", " << SuperIdx
643 << "}" << Sep << " // #" << i+1;
645 OS << ", Super=" << SuperDef->getName();
651 // Find the WriteRes Record that defines processor resources for this
653 Record *SubtargetEmitter::FindWriteResources(
654 Record *WriteDef, const CodeGenProcModel &ProcModel) {
656 // Check if the SchedWrite is already subtarget-specific and directly
657 // specifies a set of processor resources.
658 if (WriteDef->isSubClassOf("SchedWriteRes"))
661 // Check this processor's list of write resources.
662 for (RecIter WRI = ProcModel.WriteResDefs.begin(),
663 WRE = ProcModel.WriteResDefs.end(); WRI != WRE; ++WRI) {
664 if (!(*WRI)->isSubClassOf("WriteRes"))
666 if (WriteDef == (*WRI)->getValueAsDef("WriteType"))
669 throw TGError(ProcModel.ModelDef->getLoc(),
670 std::string("Processor does not define resources for ")
671 + WriteDef->getName());
674 /// Find the ReadAdvance record for the given SchedRead on this processor or
676 Record *SubtargetEmitter::FindReadAdvance(Record *ReadDef,
677 const CodeGenProcModel &ProcModel) {
678 // Check for SchedReads that directly specify a ReadAdvance.
679 if (ReadDef->isSubClassOf("SchedReadAdvance"))
682 // Check this processor's ReadAdvanceList.
683 for (RecIter RAI = ProcModel.ReadAdvanceDefs.begin(),
684 RAE = ProcModel.ReadAdvanceDefs.end(); RAI != RAE; ++RAI) {
685 if (!(*RAI)->isSubClassOf("ReadAdvance"))
687 if (ReadDef == (*RAI)->getValueAsDef("ReadType"))
690 if (ReadDef->getName() != "ReadDefault") {
691 throw TGError(ProcModel.ModelDef->getLoc(),
692 std::string("Processor does not define resources for ")
693 + ReadDef->getName());
698 // Generate the SchedClass table for this processor and update global
699 // tables. Must be called for each processor in order.
700 void SubtargetEmitter::GenSchedClassTables(const CodeGenProcModel &ProcModel,
701 SchedClassTables &SchedTables) {
702 SchedTables.ProcSchedClasses.resize(SchedTables.ProcSchedClasses.size() + 1);
703 if (!ProcModel.hasInstrSchedModel())
706 std::vector<MCSchedClassDesc> &SCTab = SchedTables.ProcSchedClasses.back();
707 for (CodeGenSchedModels::SchedClassIter SCI = SchedModels.schedClassBegin(),
708 SCE = SchedModels.schedClassEnd(); SCI != SCE; ++SCI) {
709 SCTab.resize(SCTab.size() + 1);
710 MCSchedClassDesc &SCDesc = SCTab.back();
711 SCDesc.NumMicroOps = 0;
712 SCDesc.BeginGroup = false;
713 SCDesc.EndGroup = false;
714 SCDesc.WriteProcResIdx = 0;
715 SCDesc.WriteLatencyIdx = 0;
716 SCDesc.ReadAdvanceIdx = 0;
718 // A Variant SchedClass has no resources of its own.
719 if (!SCI->Transitions.empty()) {
720 SCDesc.NumMicroOps = MCSchedClassDesc::VariantNumMicroOps;
724 // Determine if the SchedClass is actually reachable on this processor. If
725 // not don't try to locate the processor resources, it will fail.
726 // If ProcIndices contains 0, this class applies to all processors.
727 assert(!SCI->ProcIndices.empty() && "expect at least one procidx");
728 if (SCI->ProcIndices[0] != 0) {
729 IdxIter PIPos = std::find(SCI->ProcIndices.begin(),
730 SCI->ProcIndices.end(), ProcModel.Index);
731 if (PIPos == SCI->ProcIndices.end())
734 IdxVec Writes = SCI->Writes;
735 IdxVec Reads = SCI->Reads;
736 if (SCI->ItinClassDef) {
737 assert(SCI->InstRWs.empty() && "ItinClass should not have InstRWs");
738 // Check this processor's itinerary class resources.
739 for (RecIter II = ProcModel.ItinRWDefs.begin(),
740 IE = ProcModel.ItinRWDefs.end(); II != IE; ++II) {
741 RecVec Matched = (*II)->getValueAsListOfDefs("MatchedItinClasses");
742 if (std::find(Matched.begin(), Matched.end(), SCI->ItinClassDef)
744 SchedModels.findRWs((*II)->getValueAsListOfDefs("OperandReadWrites"),
749 if (Writes.empty()) {
750 DEBUG(dbgs() << ProcModel.ItinsDef->getName()
751 << " does not have resources for itinerary class "
752 << SCI->ItinClassDef->getName() << '\n');
755 else if (!SCI->InstRWs.empty()) {
756 assert(SCI->Writes.empty() && SCI->Reads.empty() &&
757 "InstRW class should not have its own ReadWrites");
759 for (RecIter RWI = SCI->InstRWs.begin(), RWE = SCI->InstRWs.end();
761 Record *RWModelDef = (*RWI)->getValueAsDef("SchedModel");
762 if (&ProcModel == &SchedModels.getProcModel(RWModelDef)) {
768 SchedModels.findRWs(RWDef->getValueAsListOfDefs("OperandReadWrites"),
772 // Sum resources across all operand writes.
773 std::vector<MCWriteProcResEntry> WriteProcResources;
774 std::vector<MCWriteLatencyEntry> WriteLatencies;
775 std::vector<MCReadAdvanceEntry> ReadAdvanceEntries;
776 for (IdxIter WI = Writes.begin(), WE = Writes.end(); WI != WE; ++WI) {
778 SchedModels.expandRWSequence(*WI, WriteSeq, /*IsRead=*/false);
780 // For each operand, create a latency entry.
781 MCWriteLatencyEntry WLEntry;
783 WLEntry.WriteResourceID = WriteSeq.back();
785 for (IdxIter WSI = WriteSeq.begin(), WSE = WriteSeq.end();
788 Record *WriteDef = SchedModels.getSchedWrite(*WSI).TheDef;
789 Record *WriteRes = FindWriteResources(WriteDef, ProcModel);
791 // Mark the parent class as invalid for unsupported write types.
792 if (WriteRes->getValueAsBit("Unsupported")) {
793 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
796 WLEntry.Cycles += WriteRes->getValueAsInt("Latency");
797 SCDesc.NumMicroOps += WriteRes->getValueAsInt("NumMicroOps");
798 SCDesc.BeginGroup |= WriteRes->getValueAsBit("BeginGroup");
799 SCDesc.EndGroup |= WriteRes->getValueAsBit("EndGroup");
801 // Create an entry for each ProcResource listed in WriteRes.
802 RecVec PRVec = WriteRes->getValueAsListOfDefs("ProcResources");
803 std::vector<int64_t> Cycles =
804 WriteRes->getValueAsListOfInts("ResourceCycles");
805 for (unsigned PRIdx = 0, PREnd = PRVec.size();
806 PRIdx != PREnd; ++PRIdx) {
807 MCWriteProcResEntry WPREntry;
808 WPREntry.ProcResourceIdx = ProcModel.getProcResourceIdx(PRVec[PRIdx]);
809 assert(WPREntry.ProcResourceIdx && "Bad ProcResourceIdx");
810 if (Cycles.size() > PRIdx)
811 WPREntry.Cycles = Cycles[PRIdx];
814 WriteProcResources.push_back(WPREntry);
817 WriteLatencies.push_back(WLEntry);
819 // Create an entry for each operand Read in this SchedClass.
820 // Entries must be sorted first by UseIdx then by WriteResourceID.
821 for (unsigned UseIdx = 0, EndIdx = Reads.size();
822 UseIdx != EndIdx; ++UseIdx) {
823 Record *ReadDef = SchedModels.getSchedRead(Reads[UseIdx]).TheDef;
824 Record *ReadAdvance = FindReadAdvance(ReadDef, ProcModel);
828 // Mark the parent class as invalid for unsupported write types.
829 if (ReadAdvance->getValueAsBit("Unsupported")) {
830 SCDesc.NumMicroOps = MCSchedClassDesc::InvalidNumMicroOps;
833 RecVec ValidWrites = ReadAdvance->getValueAsListOfDefs("ValidWrites");
835 if (ValidWrites.empty())
836 WriteIDs.push_back(0);
838 for (RecIter VWI = ValidWrites.begin(), VWE = ValidWrites.end();
840 WriteIDs.push_back(SchedModels.getSchedRWIdx(*VWI, /*IsRead=*/false));
843 std::sort(WriteIDs.begin(), WriteIDs.end());
844 for(IdxIter WI = WriteIDs.begin(), WE = WriteIDs.end(); WI != WE; ++WI) {
845 MCReadAdvanceEntry RAEntry;
846 RAEntry.UseIdx = UseIdx;
847 RAEntry.WriteResourceID = *WI;
848 RAEntry.Cycles = ReadAdvance->getValueAsInt("Cycles");
849 ReadAdvanceEntries.push_back(RAEntry);
852 if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) {
853 WriteProcResources.clear();
854 WriteLatencies.clear();
855 ReadAdvanceEntries.clear();
857 // Add the information for this SchedClass to the global tables using basic
860 // WritePrecRes entries are sorted by ProcResIdx.
861 std::sort(WriteProcResources.begin(), WriteProcResources.end(),
862 LessWriteProcResources());
864 SCDesc.NumWriteProcResEntries = WriteProcResources.size();
865 std::vector<MCWriteProcResEntry>::iterator WPRPos =
866 std::search(SchedTables.WriteProcResources.begin(),
867 SchedTables.WriteProcResources.end(),
868 WriteProcResources.begin(), WriteProcResources.end());
869 if (WPRPos != SchedTables.WriteProcResources.end())
870 SCDesc.WriteProcResIdx = WPRPos - SchedTables.WriteProcResources.begin();
872 SCDesc.WriteProcResIdx = SchedTables.WriteProcResources.size();
873 SchedTables.WriteProcResources.insert(WPRPos, WriteProcResources.begin(),
874 WriteProcResources.end());
876 // Latency entries must remain in operand order.
877 SCDesc.NumWriteLatencyEntries = WriteLatencies.size();
878 std::vector<MCWriteLatencyEntry>::iterator WLPos =
879 std::search(SchedTables.WriteLatencies.begin(),
880 SchedTables.WriteLatencies.end(),
881 WriteLatencies.begin(), WriteLatencies.end());
882 if (WLPos != SchedTables.WriteLatencies.end())
883 SCDesc.WriteLatencyIdx = WLPos - SchedTables.WriteLatencies.begin();
885 SCDesc.WriteLatencyIdx = SchedTables.WriteLatencies.size();
886 SchedTables.WriteLatencies.insert(WLPos, WriteLatencies.begin(),
887 WriteLatencies.end());
889 // ReadAdvanceEntries must remain in operand order.
890 SCDesc.NumReadAdvanceEntries = ReadAdvanceEntries.size();
891 std::vector<MCReadAdvanceEntry>::iterator RAPos =
892 std::search(SchedTables.ReadAdvanceEntries.begin(),
893 SchedTables.ReadAdvanceEntries.end(),
894 ReadAdvanceEntries.begin(), ReadAdvanceEntries.end());
895 if (RAPos != SchedTables.ReadAdvanceEntries.end())
896 SCDesc.ReadAdvanceIdx = RAPos - SchedTables.ReadAdvanceEntries.begin();
898 SCDesc.ReadAdvanceIdx = SchedTables.ReadAdvanceEntries.size();
899 SchedTables.ReadAdvanceEntries.insert(RAPos, ReadAdvanceEntries.begin(),
900 ReadAdvanceEntries.end());
905 // Emit SchedClass tables for all processors and associated global tables.
906 void SubtargetEmitter::EmitSchedClassTables(SchedClassTables &SchedTables,
908 // Emit global WriteProcResTable.
909 OS << "\n// {ProcResourceIdx, Cycles}\n"
910 << "extern const llvm::MCWriteProcResEntry "
911 << Target << "WriteProcResTable[] = {\n"
912 << " { 0, 0}, // Invalid\n";
913 for (unsigned WPRIdx = 1, WPREnd = SchedTables.WriteProcResources.size();
914 WPRIdx != WPREnd; ++WPRIdx) {
915 MCWriteProcResEntry &WPREntry = SchedTables.WriteProcResources[WPRIdx];
916 OS << " {" << format("%2d", WPREntry.ProcResourceIdx) << ", "
917 << format("%2d", WPREntry.Cycles) << "}";
918 if (WPRIdx + 1 < WPREnd)
920 OS << " // #" << WPRIdx << '\n';
922 OS << "}; // " << Target << "WriteProcResTable\n";
924 // Emit global WriteLatencyTable.
925 OS << "\n// {Cycles, WriteResourceID}\n"
926 << "extern const llvm::MCWriteLatencyEntry "
927 << Target << "WriteLatencyTable[] = {\n"
928 << " { 0, 0}, // Invalid\n";
929 for (unsigned WLIdx = 1, WLEnd = SchedTables.WriteLatencies.size();
930 WLIdx != WLEnd; ++WLIdx) {
931 MCWriteLatencyEntry &WLEntry = SchedTables.WriteLatencies[WLIdx];
932 OS << " {" << format("%2d", WLEntry.Cycles) << ", "
933 << format("%2d", WLEntry.WriteResourceID) << "}";
934 if (WLIdx + 1 < WLEnd)
936 OS << " // #" << WLIdx << " "
937 << SchedModels.getSchedWrite(WLEntry.WriteResourceID).Name << '\n';
939 OS << "}; // " << Target << "WriteLatencyTable\n";
941 // Emit global ReadAdvanceTable.
942 OS << "\n// {UseIdx, WriteResourceID, Cycles}\n"
943 << "extern const llvm::MCReadAdvanceEntry "
944 << Target << "ReadAdvanceTable[] = {\n"
945 << " {0, 0, 0}, // Invalid\n";
946 for (unsigned RAIdx = 1, RAEnd = SchedTables.ReadAdvanceEntries.size();
947 RAIdx != RAEnd; ++RAIdx) {
948 MCReadAdvanceEntry &RAEntry = SchedTables.ReadAdvanceEntries[RAIdx];
949 OS << " {" << RAEntry.UseIdx << ", "
950 << format("%2d", RAEntry.WriteResourceID) << ", "
951 << format("%2d", RAEntry.Cycles) << "}";
952 if (RAIdx + 1 < RAEnd)
954 OS << " // #" << RAIdx << '\n';
956 OS << "}; // " << Target << "ReadAdvanceTable\n";
958 // Emit a SchedClass table for each processor.
959 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
960 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
961 if (!PI->hasInstrSchedModel())
964 std::vector<MCSchedClassDesc> &SCTab =
965 SchedTables.ProcSchedClasses[1 + PI - SchedModels.procModelBegin()];
967 OS << "\n// {Name, NumMicroOps, BeginGroup, EndGroup,"
968 << " WriteProcResIdx,#, WriteLatencyIdx,#, ReadAdvanceIdx,#}\n";
969 OS << "static const llvm::MCSchedClassDesc "
970 << PI->ModelName << "SchedClasses[] = {\n";
972 // The first class is always invalid. We no way to distinguish it except by
973 // name and position.
974 assert(SchedClass.Name == "NoItinerary"
975 && "invalid class not first");
976 OS << " {DBGFIELD(\"InvalidSchedClass\") "
977 << MCSchedClassDesc::InvalidNumMicroOps
978 << ", 0, 0, 0, 0, 0, 0, 0, 0},\n";
980 for (unsigned SCIdx = 1, SCEnd = SCTab.size(); SCIdx != SCEnd; ++SCIdx) {
981 MCSchedClassDesc &MCDesc = SCTab[SCIdx];
982 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx);
983 OS << " {DBGFIELD(\"" << SchedClass.Name << "\") ";
984 if (SchedClass.Name.size() < 18)
985 OS.indent(18 - SchedClass.Name.size());
986 OS << MCDesc.NumMicroOps
987 << ", " << MCDesc.BeginGroup << ", " << MCDesc.EndGroup
988 << ", " << format("%2d", MCDesc.WriteProcResIdx)
989 << ", " << MCDesc.NumWriteProcResEntries
990 << ", " << format("%2d", MCDesc.WriteLatencyIdx)
991 << ", " << MCDesc.NumWriteLatencyEntries
992 << ", " << format("%2d", MCDesc.ReadAdvanceIdx)
993 << ", " << MCDesc.NumReadAdvanceEntries << "}";
994 if (SCIdx + 1 < SCEnd)
996 OS << " // #" << SCIdx << '\n';
998 OS << "}; // " << PI->ModelName << "SchedClasses\n";
1002 void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) {
1003 // For each processor model.
1004 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
1005 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
1006 // Emit processor resource table.
1007 if (PI->hasInstrSchedModel())
1008 EmitProcessorResources(*PI, OS);
1009 else if(!PI->ProcResourceDefs.empty())
1010 throw TGError(PI->ModelDef->getLoc(), "SchedMachineModel defines "
1011 "ProcResources without defining WriteRes SchedWriteRes");
1013 // Begin processor itinerary properties
1015 OS << "static const llvm::MCSchedModel " << PI->ModelName << "(\n";
1016 EmitProcessorProp(OS, PI->ModelDef, "IssueWidth", ',');
1017 EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ',');
1018 EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ',');
1019 EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ',');
1020 EmitProcessorProp(OS, PI->ModelDef, "MispredictPenalty", ',');
1021 if (SchedModels.hasItineraryClasses())
1022 OS << " " << PI->ItinsDef->getName() << ");\n";
1024 OS << " 0); // No Itinerary\n";
1029 // EmitProcessorLookup - generate cpu name to itinerary lookup table.
1031 void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) {
1032 // Gather and sort processor information
1033 std::vector<Record*> ProcessorList =
1034 Records.getAllDerivedDefinitions("Processor");
1035 std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName());
1037 // Begin processor table
1039 OS << "// Sorted (by key) array of itineraries for CPU subtype.\n"
1040 << "extern const llvm::SubtargetInfoKV "
1041 << Target << "ProcSchedKV[] = {\n";
1043 // For each processor
1044 for (unsigned i = 0, N = ProcessorList.size(); i < N;) {
1046 Record *Processor = ProcessorList[i];
1048 const std::string &Name = Processor->getValueAsString("Name");
1049 const std::string &ProcModelName =
1050 SchedModels.getModelForProc(Processor).ModelName;
1052 // Emit as { "cpu", procinit },
1053 OS << " { \"" << Name << "\", (const void *)&" << ProcModelName << " }";
1055 // Depending on ''if more in the list'' emit comma
1056 if (++i < N) OS << ",";
1061 // End processor table
1066 // EmitSchedModel - Emits all scheduling model tables, folding common patterns.
1068 void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) {
1069 OS << "#ifdef DBGFIELD\n"
1070 << "#error \"<target>GenSubtargetInfo.inc requires a DBGFIELD macro\"\n"
1072 << "#ifndef NDEBUG\n"
1073 << "#define DBGFIELD(x) x,\n"
1075 << "#define DBGFIELD(x)\n"
1078 if (SchedModels.hasItineraryClasses()) {
1079 std::vector<std::vector<InstrItinerary> > ProcItinLists;
1080 // Emit the stage data
1081 EmitStageAndOperandCycleData(OS, ProcItinLists);
1082 EmitItineraries(OS, ProcItinLists);
1084 OS << "\n// ===============================================================\n"
1085 << "// Data tables for the new per-operand machine model.\n";
1087 SchedClassTables SchedTables;
1088 for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(),
1089 PE = SchedModels.procModelEnd(); PI != PE; ++PI) {
1090 GenSchedClassTables(*PI, SchedTables);
1092 EmitSchedClassTables(SchedTables, OS);
1094 // Emit the processor machine model
1095 EmitProcessorModels(OS);
1096 // Emit the processor lookup data
1097 EmitProcessorLookup(OS);
1099 OS << "#undef DBGFIELD";
1103 // ParseFeaturesFunction - Produces a subtarget specific function for parsing
1104 // the subtarget features string.
1106 void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
1107 unsigned NumFeatures,
1108 unsigned NumProcs) {
1109 std::vector<Record*> Features =
1110 Records.getAllDerivedDefinitions("SubtargetFeature");
1111 std::sort(Features.begin(), Features.end(), LessRecord());
1113 OS << "// ParseSubtargetFeatures - Parses features string setting specified\n"
1114 << "// subtarget options.\n"
1117 OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n"
1118 << " DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n"
1119 << " DEBUG(dbgs() << \"\\nCPU:\" << CPU << \"\\n\\n\");\n";
1121 if (Features.empty()) {
1126 OS << " uint64_t Bits = ReInitMCSubtargetInfo(CPU, FS);\n";
1128 for (unsigned i = 0; i < Features.size(); i++) {
1130 Record *R = Features[i];
1131 const std::string &Instance = R->getName();
1132 const std::string &Value = R->getValueAsString("Value");
1133 const std::string &Attribute = R->getValueAsString("Attribute");
1135 if (Value=="true" || Value=="false")
1136 OS << " if ((Bits & " << Target << "::"
1137 << Instance << ") != 0) "
1138 << Attribute << " = " << Value << ";\n";
1140 OS << " if ((Bits & " << Target << "::"
1141 << Instance << ") != 0 && "
1142 << Attribute << " < " << Value << ") "
1143 << Attribute << " = " << Value << ";\n";
1150 // SubtargetEmitter::run - Main subtarget enumeration emitter.
1152 void SubtargetEmitter::run(raw_ostream &OS) {
1153 emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS);
1155 OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n";
1156 OS << "#undef GET_SUBTARGETINFO_ENUM\n";
1158 OS << "namespace llvm {\n";
1159 Enumeration(OS, "SubtargetFeature", true);
1160 OS << "} // End llvm namespace \n";
1161 OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n";
1163 OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n";
1164 OS << "#undef GET_SUBTARGETINFO_MC_DESC\n";
1166 OS << "namespace llvm {\n";
1168 OS << "namespace {\n";
1170 unsigned NumFeatures = FeatureKeyValues(OS);
1172 unsigned NumProcs = CPUKeyValues(OS);
1180 // MCInstrInfo initialization routine.
1181 OS << "static inline void Init" << Target
1182 << "MCSubtargetInfo(MCSubtargetInfo *II, "
1183 << "StringRef TT, StringRef CPU, StringRef FS) {\n";
1184 OS << " II->InitMCSubtargetInfo(TT, CPU, FS, ";
1186 OS << Target << "FeatureKV, ";
1190 OS << Target << "SubTypeKV, ";
1193 OS << '\n'; OS.indent(22);
1194 if (SchedModels.hasItineraryClasses()) {
1195 OS << Target << "ProcSchedKV, "
1196 << Target << "Stages, "
1197 << Target << "OperandCycles, "
1198 << Target << "ForwardingPaths, ";
1200 OS << "0, 0, 0, 0, ";
1201 OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
1203 OS << "} // End llvm namespace \n";
1205 OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n";
1207 OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n";
1208 OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n";
1210 OS << "#include \"llvm/Support/Debug.h\"\n";
1211 OS << "#include \"llvm/Support/raw_ostream.h\"\n";
1212 ParseFeaturesFunction(OS, NumFeatures, NumProcs);
1214 OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n";
1216 // Create a TargetSubtargetInfo subclass to hide the MC layer initialization.
1217 OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n";
1218 OS << "#undef GET_SUBTARGETINFO_HEADER\n";
1220 std::string ClassName = Target + "GenSubtargetInfo";
1221 OS << "namespace llvm {\n";
1222 OS << "class DFAPacketizer;\n";
1223 OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
1224 << " explicit " << ClassName << "(StringRef TT, StringRef CPU, "
1225 << "StringRef FS);\n"
1227 << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
1230 OS << "} // End llvm namespace \n";
1232 OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
1234 OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
1235 OS << "#undef GET_SUBTARGETINFO_CTOR\n";
1237 OS << "namespace llvm {\n";
1238 OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n";
1239 OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n";
1240 OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n";
1241 OS << "extern const llvm::MCWriteProcResEntry "
1242 << Target << "WriteProcResTable[];\n";
1243 OS << "extern const llvm::MCWriteLatencyEntry "
1244 << Target << "WriteLatencyTable[];\n";
1245 OS << "extern const llvm::MCReadAdvanceEntry "
1246 << Target << "ReadAdvanceTable[];\n";
1248 if (SchedModels.hasItineraryClasses()) {
1249 OS << "extern const llvm::InstrStage " << Target << "Stages[];\n";
1250 OS << "extern const unsigned " << Target << "OperandCycles[];\n";
1251 OS << "extern const unsigned " << Target << "ForwardingPaths[];\n";
1254 OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, "
1255 << "StringRef FS)\n"
1256 << " : TargetSubtargetInfo() {\n"
1257 << " InitMCSubtargetInfo(TT, CPU, FS, ";
1259 OS << Target << "FeatureKV, ";
1263 OS << Target << "SubTypeKV, ";
1266 if (SchedModels.hasItineraryClasses()) {
1267 OS << Target << "ProcSchedKV, "
1268 << Target << "Stages, "
1269 << Target << "OperandCycles, "
1270 << Target << "ForwardingPaths, ";
1272 OS << "0, 0, 0, 0, ";
1273 OS << NumFeatures << ", " << NumProcs << ");\n}\n\n";
1275 OS << "} // End llvm namespace \n";
1277 OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
1282 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) {
1283 CodeGenTarget CGTarget(RK);
1284 SubtargetEmitter(RK, CGTarget).run(OS);
1287 } // End llvm namespace