utils/TableGen/TableGen.cpp

   1 //===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the main function for LLVM's TableGen.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #include "AsmMatcherEmitter.h"
  15 #include "AsmWriterEmitter.h"
  16 #include "CallingConvEmitter.h"
  17 #include "CodeEmitterGen.h"
  18 #include "DAGISelEmitter.h"
  19 #include "DisassemblerEmitter.h"
  20 #include "EDEmitter.h"
  21 #include "FastISelEmitter.h"
  22 #include "InstrInfoEmitter.h"
  23 #include "IntrinsicEmitter.h"
  24 #include "PseudoLoweringEmitter.h"
  25 #include "RegisterInfoEmitter.h"
  26 #include "SubtargetEmitter.h"
  27 #include "SetTheory.h"
  28
  29 #include "llvm/Support/CommandLine.h"
  30 #include "llvm/Support/PrettyStackTrace.h"
  31 #include "llvm/Support/Signals.h"
  32 #include "llvm/TableGen/Error.h"
  33 #include "llvm/TableGen/Main.h"
  34 #include "llvm/TableGen/Record.h"
  35 #include "llvm/TableGen/TableGenAction.h"
  36
  37 using namespace llvm;
  38
  39 enum ActionType {
  40   PrintRecords,
  41   GenEmitter,
  42   GenRegisterInfo,
  43   GenInstrInfo,
  44   GenAsmWriter,
  45   GenAsmMatcher,
  46   GenDisassembler,
  47   GenPseudoLowering,
  48   GenCallingConv,
  49   GenDAGISel,
  50   GenFastISel,
  51   GenSubtarget,
  52   GenIntrinsic,
  53   GenTgtIntrinsic,
  54   GenEDInfo,
  55   PrintEnums,
  56   PrintSets
  57 };
  58
  59 namespace {
  60   cl::opt<ActionType>
  61   Action(cl::desc("Action to perform:"),
  62          cl::values(clEnumValN(PrintRecords, "print-records",
  63                                "Print all records to stdout (default)"),
  64                     clEnumValN(GenEmitter, "gen-emitter",
  65                                "Generate machine code emitter"),
  66                     clEnumValN(GenRegisterInfo, "gen-register-info",
  67                                "Generate registers and register classes info"),
  68                     clEnumValN(GenInstrInfo, "gen-instr-info",
  69                                "Generate instruction descriptions"),
  70                     clEnumValN(GenCallingConv, "gen-callingconv",
  71                                "Generate calling convention descriptions"),
  72                     clEnumValN(GenAsmWriter, "gen-asm-writer",
  73                                "Generate assembly writer"),
  74                     clEnumValN(GenDisassembler, "gen-disassembler",
  75                                "Generate disassembler"),
  76                     clEnumValN(GenPseudoLowering, "gen-pseudo-lowering",
  77                                "Generate pseudo instruction lowering"),
  78                     clEnumValN(GenAsmMatcher, "gen-asm-matcher",
  79                                "Generate assembly instruction matcher"),
  80                     clEnumValN(GenDAGISel, "gen-dag-isel",
  81                                "Generate a DAG instruction selector"),
  82                     clEnumValN(GenFastISel, "gen-fast-isel",
  83                                "Generate a \"fast\" instruction selector"),
  84                     clEnumValN(GenSubtarget, "gen-subtarget",
  85                                "Generate subtarget enumerations"),
  86                     clEnumValN(GenIntrinsic, "gen-intrinsic",
  87                                "Generate intrinsic information"),
  88                     clEnumValN(GenTgtIntrinsic, "gen-tgt-intrinsic",
  89                                "Generate target intrinsic information"),
  90                     clEnumValN(GenEDInfo, "gen-enhanced-disassembly-info",
  91                                "Generate enhanced disassembly info"),
  92                     clEnumValN(PrintEnums, "print-enums",
  93                                "Print enum values for a class"),
  94                     clEnumValN(PrintSets, "print-sets",
  95                                "Print expanded sets for testing DAG exprs"),
  96                     clEnumValEnd));
  97
  98   cl::opt<std::string>
  99   Class("class", cl::desc("Print Enum list for this class"),
 100         cl::value_desc("class name"));
 101 }
 102
 103 class LLVMTableGenAction : public TableGenAction {
 104 public:
 105   bool operator()(raw_ostream &OS, RecordKeeper &Records) {
 106     switch (Action) {
 107     case PrintRecords:
 108       OS << Records;           // No argument, dump all contents
 109       break;
 110     case GenEmitter:
 111       CodeEmitterGen(Records).run(OS);
 112       break;
 113     case GenRegisterInfo:
 114       RegisterInfoEmitter(Records).run(OS);
 115       break;
 116     case GenInstrInfo:
 117       InstrInfoEmitter(Records).run(OS);
 118       break;
 119     case GenCallingConv:
 120       CallingConvEmitter(Records).run(OS);
 121       break;
 122     case GenAsmWriter:
 123       AsmWriterEmitter(Records).run(OS);
 124       break;
 125     case GenAsmMatcher:
 126       AsmMatcherEmitter(Records).run(OS);
 127       break;
 128     case GenDisassembler:
 129       DisassemblerEmitter(Records).run(OS);
 130       break;
 131     case GenPseudoLowering:
 132       PseudoLoweringEmitter(Records).run(OS);
 133       break;
 134     case GenDAGISel:
 135       DAGISelEmitter(Records).run(OS);
 136       break;
 137     case GenFastISel:
 138       FastISelEmitter(Records).run(OS);
 139       break;
 140     case GenSubtarget:
 141       SubtargetEmitter(Records).run(OS);
 142       break;
 143     case GenIntrinsic:
 144       IntrinsicEmitter(Records).run(OS);
 145       break;
 146     case GenTgtIntrinsic:
 147       IntrinsicEmitter(Records, true).run(OS);
 148       break;
 149     case GenEDInfo:
 150       EDEmitter(Records).run(OS);
 151       break;
 152     case PrintEnums:
 153     {
 154       std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);
 155       for (unsigned i = 0, e = Recs.size(); i != e; ++i)
 156         OS << Recs[i]->getName() << ", ";
 157       OS << "\n";
 158       break;
 159     }
 160     case PrintSets:
 161     {
 162       SetTheory Sets;
 163       Sets.addFieldExpander("Set", "Elements");
 164       std::vector<Record*> Recs = Records.getAllDerivedDefinitions("Set");
 165       for (unsigned i = 0, e = Recs.size(); i != e; ++i) {
 166         OS << Recs[i]->getName() << " = [";
 167         const std::vector<Record*> *Elts = Sets.expand(Recs[i]);
 168         assert(Elts && "Couldn't expand Set instance");
 169         for (unsigned ei = 0, ee = Elts->size(); ei != ee; ++ei)
 170           OS << ' ' << (*Elts)[ei]->getName();
 171         OS << " ]\n";
 172       }
 173       break;
 174     }
 175     default:
 176       assert(1 && "Invalid Action");
 177       return true;
 178     }
 179
 180     return false;
 181   }
 182 };
 183
 184 int main(int argc, char **argv) {
 185   sys::PrintStackTraceOnErrorSignal();
 186   PrettyStackTraceProgram X(argc, argv);
 187   cl::ParseCommandLineOptions(argc, argv);
 188
 189   LLVMTableGenAction Action;
 190   return TableGenMain(argv[0], Action);
 191 }