1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
22 #include "llvm/TableGen/TableGenBackend.h"
26 using namespace X86Disassembler;
28 /// inheritsFrom - Indicates whether all instructions in one class also belong
31 /// @param child - The class that may be the subset
32 /// @param parent - The class that may be the superset
33 /// @return - True if child is a subset of parent, false otherwise.
34 static inline bool inheritsFrom(InstructionContext child,
35 InstructionContext parent,
36 bool VEX_LIG = false) {
42 return(inheritsFrom(child, IC_64BIT) ||
43 inheritsFrom(child, IC_OPSIZE) ||
44 inheritsFrom(child, IC_ADSIZE) ||
45 inheritsFrom(child, IC_XD) ||
46 inheritsFrom(child, IC_XS));
48 return(inheritsFrom(child, IC_64BIT_REXW) ||
49 inheritsFrom(child, IC_64BIT_OPSIZE) ||
50 inheritsFrom(child, IC_64BIT_ADSIZE) ||
51 inheritsFrom(child, IC_64BIT_XD) ||
52 inheritsFrom(child, IC_64BIT_XS));
54 return inheritsFrom(child, IC_64BIT_OPSIZE);
59 return inheritsFrom(child, IC_64BIT_XD);
61 return inheritsFrom(child, IC_64BIT_XS);
63 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
65 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
67 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
68 inheritsFrom(child, IC_64BIT_REXW_XD) ||
69 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
71 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
73 return(inheritsFrom(child, IC_64BIT_REXW_XD));
75 return(inheritsFrom(child, IC_64BIT_REXW_XS));
76 case IC_64BIT_XD_OPSIZE:
77 case IC_64BIT_XS_OPSIZE:
79 case IC_64BIT_REXW_XD:
80 case IC_64BIT_REXW_XS:
81 case IC_64BIT_REXW_OPSIZE:
84 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
85 inheritsFrom(child, IC_VEX_W) ||
86 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
88 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
89 inheritsFrom(child, IC_VEX_W_XS) ||
90 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
92 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
93 inheritsFrom(child, IC_VEX_W_XD) ||
94 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
96 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
97 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
98 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
100 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
102 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
104 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
105 case IC_VEX_W_OPSIZE:
106 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
108 return inheritsFrom(child, IC_VEX_L_W);
110 return inheritsFrom(child, IC_VEX_L_W_XS);
112 return inheritsFrom(child, IC_VEX_L_W_XD);
113 case IC_VEX_L_OPSIZE:
114 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
118 case IC_VEX_L_W_OPSIZE:
121 return inheritsFrom(child, IC_EVEX_W) ||
122 inheritsFrom(child, IC_EVEX_L_W);
124 return inheritsFrom(child, IC_EVEX_W_XS) ||
125 inheritsFrom(child, IC_EVEX_L_W_XS);
127 return inheritsFrom(child, IC_EVEX_W_XD) ||
128 inheritsFrom(child, IC_EVEX_L_W_XD);
130 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
131 inheritsFrom(child, IC_EVEX_W_OPSIZE);
135 case IC_EVEX_W_OPSIZE:
140 case IC_EVEX_L_OPSIZE:
145 case IC_EVEX_L_W_OPSIZE:
150 case IC_EVEX_L2_OPSIZE:
153 case IC_EVEX_L2_W_XS:
154 case IC_EVEX_L2_W_XD:
155 case IC_EVEX_L2_W_OPSIZE:
158 return inheritsFrom(child, IC_EVEX_W_K) ||
159 inheritsFrom(child, IC_EVEX_L_W_K);
161 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
162 inheritsFrom(child, IC_EVEX_L_W_XS_K);
164 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
165 inheritsFrom(child, IC_EVEX_L_W_XD_K);
166 case IC_EVEX_OPSIZE_K:
167 return inheritsFrom(child, IC_EVEX_W_OPSIZE_K) ||
168 inheritsFrom(child, IC_EVEX_W_OPSIZE_K);
172 case IC_EVEX_W_OPSIZE_K:
177 case IC_EVEX_L_OPSIZE_K:
180 case IC_EVEX_L_W_XS_K:
181 case IC_EVEX_L_W_XD_K:
182 case IC_EVEX_L_W_OPSIZE_K:
186 case IC_EVEX_L2_XS_K:
187 case IC_EVEX_L2_XD_K:
188 case IC_EVEX_L2_OPSIZE_K:
189 case IC_EVEX_L2_OPSIZE_B:
192 case IC_EVEX_L2_W_XS_K:
193 case IC_EVEX_L2_W_XD_K:
194 case IC_EVEX_L2_W_OPSIZE_K:
195 case IC_EVEX_L2_W_OPSIZE_B:
198 llvm_unreachable("Unknown instruction class");
202 /// outranks - Indicates whether, if an instruction has two different applicable
203 /// classes, which class should be preferred when performing decode. This
204 /// imposes a total ordering (ties are resolved toward "lower")
206 /// @param upper - The class that may be preferable
207 /// @param lower - The class that may be less preferable
208 /// @return - True if upper is to be preferred, false otherwise.
209 static inline bool outranks(InstructionContext upper,
210 InstructionContext lower) {
211 assert(upper < IC_max);
212 assert(lower < IC_max);
214 #define ENUM_ENTRY(n, r, d) r,
215 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
216 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
217 static int ranks[IC_max] = {
221 #undef ENUM_ENTRY_K_B
223 return (ranks[upper] > ranks[lower]);
226 /// stringForContext - Returns a string containing the name of a particular
227 /// InstructionContext, usually for diagnostic purposes.
229 /// @param insnContext - The instruction class to transform to a string.
230 /// @return - A statically-allocated string constant that contains the
231 /// name of the instruction class.
232 static inline const char* stringForContext(InstructionContext insnContext) {
233 switch (insnContext) {
235 llvm_unreachable("Unhandled instruction class");
236 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
237 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
238 ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
241 #undef ENUM_ENTRY_K_B
245 /// stringForOperandType - Like stringForContext, but for OperandTypes.
246 static inline const char* stringForOperandType(OperandType type) {
249 llvm_unreachable("Unhandled type");
250 #define ENUM_ENTRY(i, d) case i: return #i;
256 /// stringForOperandEncoding - like stringForContext, but for
257 /// OperandEncodings.
258 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
261 llvm_unreachable("Unhandled encoding");
262 #define ENUM_ENTRY(i, d) case i: return #i;
268 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
269 /// be compacted by eliminating redundant information.
271 /// @param decision - The decision to be compacted.
272 /// @return - The compactest available representation for the decision.
273 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
274 bool satisfiesOneEntry = true;
275 bool satisfiesSplitRM = true;
276 bool satisfiesSplitReg = true;
277 bool satisfiesSplitMisc = true;
279 for (unsigned index = 0; index < 256; ++index) {
280 if (decision.instructionIDs[index] != decision.instructionIDs[0])
281 satisfiesOneEntry = false;
283 if (((index & 0xc0) == 0xc0) &&
284 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
285 satisfiesSplitRM = false;
287 if (((index & 0xc0) != 0xc0) &&
288 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
289 satisfiesSplitRM = false;
291 if (((index & 0xc0) == 0xc0) &&
292 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
293 satisfiesSplitReg = false;
295 if (((index & 0xc0) != 0xc0) &&
296 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
297 satisfiesSplitMisc = false;
300 if (satisfiesOneEntry)
301 return MODRM_ONEENTRY;
303 if (satisfiesSplitRM)
304 return MODRM_SPLITRM;
306 if (satisfiesSplitReg && satisfiesSplitMisc)
307 return MODRM_SPLITREG;
309 if (satisfiesSplitMisc)
310 return MODRM_SPLITMISC;
315 /// stringForDecisionType - Returns a statically-allocated string corresponding
316 /// to a particular decision type.
318 /// @param dt - The decision type.
319 /// @return - A pointer to the statically-allocated string (e.g.,
320 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
321 static const char* stringForDecisionType(ModRMDecisionType dt) {
322 #define ENUM_ENTRY(n) case n: return #n;
325 llvm_unreachable("Unknown decision type");
331 /// stringForModifierType - Returns a statically-allocated string corresponding
332 /// to an opcode modifier type.
334 /// @param mt - The modifier type.
335 /// @return - A pointer to the statically-allocated string (e.g.,
336 /// "MODIFIER_NONE" for MODIFIER_NONE).
337 static const char* stringForModifierType(ModifierType mt) {
338 #define ENUM_ENTRY(n) case n: return #n;
341 llvm_unreachable("Unknown modifier type");
347 DisassemblerTables::DisassemblerTables() {
350 for (i = 0; i < array_lengthof(Tables); i++) {
351 Tables[i] = new ContextDecision;
352 memset(Tables[i], 0, sizeof(ContextDecision));
355 HasConflicts = false;
358 DisassemblerTables::~DisassemblerTables() {
361 for (i = 0; i < array_lengthof(Tables); i++)
365 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
366 unsigned &i1, unsigned &i2,
367 unsigned &ModRMTableNum,
368 ModRMDecision &decision) const {
369 static uint32_t sTableNumber = 0;
370 static uint32_t sEntryNumber = 1;
371 ModRMDecisionType dt = getDecisionType(decision);
373 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
375 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
378 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
379 o2.indent(i2) << 0 << " /* EmptyTable */\n";
382 o2.indent(i2) << "}";
386 std::vector<unsigned> ModRMDecision;
390 llvm_unreachable("Unknown decision type");
392 ModRMDecision.push_back(decision.instructionIDs[0]);
395 ModRMDecision.push_back(decision.instructionIDs[0x00]);
396 ModRMDecision.push_back(decision.instructionIDs[0xc0]);
399 for (unsigned index = 0; index < 64; index += 8)
400 ModRMDecision.push_back(decision.instructionIDs[index]);
401 for (unsigned index = 0xc0; index < 256; index += 8)
402 ModRMDecision.push_back(decision.instructionIDs[index]);
404 case MODRM_SPLITMISC:
405 for (unsigned index = 0; index < 64; index += 8)
406 ModRMDecision.push_back(decision.instructionIDs[index]);
407 for (unsigned index = 0xc0; index < 256; ++index)
408 ModRMDecision.push_back(decision.instructionIDs[index]);
411 for (unsigned index = 0; index < 256; ++index)
412 ModRMDecision.push_back(decision.instructionIDs[index]);
416 unsigned &EntryNumber = ModRMTable[ModRMDecision];
417 if (EntryNumber == 0) {
418 EntryNumber = ModRMTableNum;
420 ModRMTableNum += ModRMDecision.size();
421 o1 << "/* Table" << EntryNumber << " */\n";
423 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
424 E = ModRMDecision.end(); I != E; ++I) {
425 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* "
426 << InstructionSpecifiers[*I].name << " */\n";
431 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
434 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
435 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n";
438 o2.indent(i2) << "}";
442 llvm_unreachable("Unknown decision type");
452 case MODRM_SPLITMISC:
453 sEntryNumber += 8 + 64;
460 // We assume that the index can fit into uint16_t.
461 assert(sEntryNumber < 65536U &&
462 "Index into ModRMDecision is too large for uint16_t!");
467 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
468 unsigned &i1, unsigned &i2,
469 unsigned &ModRMTableNum,
470 OpcodeDecision &decision) const {
471 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
473 o2.indent(i2) << "{" << "\n";
476 for (unsigned index = 0; index < 256; ++index) {
479 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
481 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
482 decision.modRMDecisions[index]);
491 o2.indent(i2) << "}" << "\n";
493 o2.indent(i2) << "}" << "\n";
496 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
497 unsigned &i1, unsigned &i2,
498 unsigned &ModRMTableNum,
499 ContextDecision &decision,
500 const char* name) const {
501 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
503 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
506 for (unsigned index = 0; index < IC_max; ++index) {
507 o2.indent(i2) << "/* ";
508 o2 << stringForContext((InstructionContext)index);
512 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
513 decision.opcodeDecisions[index]);
515 if (index + 1 < IC_max)
520 o2.indent(i2) << "}" << "\n";
522 o2.indent(i2) << "};" << "\n";
525 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
527 unsigned NumInstructions = InstructionSpecifiers.size();
529 o << "static const struct OperandSpecifier x86OperandSets[]["
530 << X86_MAX_OPERANDS << "] = {\n";
532 typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
533 std::map<OperandListTy, unsigned> OperandSets;
535 unsigned OperandSetNum = 0;
536 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
537 OperandListTy OperandList;
539 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
541 const char *Encoding =
542 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
543 .operands[OperandIndex].encoding);
545 stringForOperandType((OperandType)InstructionSpecifiers[Index]
546 .operands[OperandIndex].type);
547 OperandList.push_back(std::make_pair(Encoding, Type));
549 unsigned &N = OperandSets[OperandList];
550 if (N != 0) continue;
554 o << " { /* " << (OperandSetNum - 1) << " */\n";
555 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
556 o << " { " << OperandList[i].first << ", "
557 << OperandList[i].second << " },\n";
563 o.indent(i * 2) << "static const struct InstructionSpecifier ";
564 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
568 for (unsigned index = 0; index < NumInstructions; ++index) {
569 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
572 o.indent(i * 2) << stringForModifierType(
573 (ModifierType)InstructionSpecifiers[index].modifierType);
576 o.indent(i * 2) << "0x";
577 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
580 OperandListTy OperandList;
581 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
583 const char *Encoding =
584 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
585 .operands[OperandIndex].encoding);
587 stringForOperandType((OperandType)InstructionSpecifiers[index]
588 .operands[OperandIndex].type);
589 OperandList.push_back(std::make_pair(Encoding, Type));
591 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
593 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
597 o.indent(i * 2) << "}";
599 if (index + 1 < NumInstructions)
606 o.indent(i * 2) << "};" << "\n";
609 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
610 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
614 for (unsigned index = 0; index < 256; ++index) {
617 if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
618 o << "IC_VEX_L_W_OPSIZE";
619 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
620 o << "IC_VEX_L_W_XD";
621 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
622 o << "IC_VEX_L_W_XS";
623 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
625 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
626 o << "IC_VEX_L_OPSIZE";
627 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
629 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
631 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
632 o << "IC_VEX_W_OPSIZE";
633 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
635 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
637 else if (index & ATTR_VEXL)
639 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
641 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
642 o << "IC_VEX_OPSIZE";
643 else if ((index & ATTR_VEX) && (index & ATTR_XD))
645 else if ((index & ATTR_VEX) && (index & ATTR_XS))
647 else if (index & ATTR_VEX)
649 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
650 o << "IC_64BIT_REXW_XS";
651 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
652 o << "IC_64BIT_REXW_XD";
653 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
654 (index & ATTR_OPSIZE))
655 o << "IC_64BIT_REXW_OPSIZE";
656 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
657 o << "IC_64BIT_XD_OPSIZE";
658 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
659 o << "IC_64BIT_XS_OPSIZE";
660 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
662 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
664 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
665 o << "IC_64BIT_OPSIZE";
666 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
667 o << "IC_64BIT_ADSIZE";
668 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
669 o << "IC_64BIT_REXW";
670 else if ((index & ATTR_64BIT))
672 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
674 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
676 else if (index & ATTR_XS)
678 else if (index & ATTR_XD)
680 else if (index & ATTR_OPSIZE)
682 else if (index & ATTR_ADSIZE)
692 o << " /* " << index << " */";
698 o.indent(i * 2) << "};" << "\n";
701 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
702 unsigned &i1, unsigned &i2,
703 unsigned &ModRMTableNum) const {
704 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
705 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
706 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
707 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
708 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], THREEBYTEA6_STR);
709 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], THREEBYTEA7_STR);
710 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOP8_MAP_STR);
711 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[7], XOP9_MAP_STR);
712 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[8], XOPA_MAP_STR);
715 void DisassemblerTables::emit(raw_ostream &o) const {
722 raw_string_ostream o1(s1);
723 raw_string_ostream o2(s2);
725 emitInstructionInfo(o, i2);
728 emitContextTable(o, i2);
731 unsigned ModRMTableNum = 0;
733 o << "static const InstrUID modRMTable[] = {\n";
735 std::vector<unsigned> EmptyTable(1, 0);
736 ModRMTable[EmptyTable] = ModRMTableNum;
737 ModRMTableNum += EmptyTable.size();
738 o1 << "/* EmptyTable */\n";
739 o1.indent(i1 * 2) << "0x0,\n";
741 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
752 void DisassemblerTables::setTableFields(ModRMDecision &decision,
753 const ModRMFilter &filter,
756 for (unsigned index = 0; index < 256; ++index) {
757 if (filter.accepts(index)) {
758 if (decision.instructionIDs[index] == uid)
761 if (decision.instructionIDs[index] != 0) {
762 InstructionSpecifier &newInfo =
763 InstructionSpecifiers[uid];
764 InstructionSpecifier &previousInfo =
765 InstructionSpecifiers[decision.instructionIDs[index]];
768 continue; // filtered instructions get lowest priority
770 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
771 newInfo.name == "XCHG32ar" ||
772 newInfo.name == "XCHG32ar64" ||
773 newInfo.name == "XCHG64ar"))
774 continue; // special case for XCHG*ar and NOOP
776 if (outranks(previousInfo.insnContext, newInfo.insnContext))
779 if (previousInfo.insnContext == newInfo.insnContext &&
780 !previousInfo.filtered) {
781 errs() << "Error: Primary decode conflict: ";
782 errs() << newInfo.name << " would overwrite " << previousInfo.name;
784 errs() << "ModRM " << index << "\n";
785 errs() << "Opcode " << (uint16_t)opcode << "\n";
786 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
791 decision.instructionIDs[index] = uid;
796 void DisassemblerTables::setTableFields(OpcodeType type,
797 InstructionContext insnContext,
799 const ModRMFilter &filter,
803 ContextDecision &decision = *Tables[type];
805 for (unsigned index = 0; index < IC_max; ++index) {
806 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
809 if (inheritsFrom((InstructionContext)index,
810 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
811 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],