1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86DisassemblerTables.h"
20 #include "TableGenBackend.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/Format.h"
25 using namespace X86Disassembler;
27 /// inheritsFrom - Indicates whether all instructions in one class also belong
30 /// @param child - The class that may be the subset
31 /// @param parent - The class that may be the superset
32 /// @return - True if child is a subset of parent, false otherwise.
33 static inline bool inheritsFrom(InstructionContext child,
34 InstructionContext parent) {
42 return(inheritsFrom(child, IC_64BIT_REXW) ||
43 inheritsFrom(child, IC_64BIT_OPSIZE) ||
44 inheritsFrom(child, IC_64BIT_XD) ||
45 inheritsFrom(child, IC_64BIT_XS));
47 return(inheritsFrom(child, IC_64BIT_OPSIZE));
49 return(inheritsFrom(child, IC_64BIT_XD) ||
50 inheritsFrom(child, IC_VEX_XD));
52 return(inheritsFrom(child, IC_64BIT_XS) ||
53 inheritsFrom(child, IC_VEX_XS));
55 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
56 inheritsFrom(child, IC_64BIT_REXW_XD) ||
57 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
59 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
61 return(inheritsFrom(child, IC_64BIT_REXW_XD));
63 return(inheritsFrom(child, IC_64BIT_REXW_XS));
64 case IC_64BIT_REXW_XD:
66 case IC_64BIT_REXW_XS:
68 case IC_64BIT_REXW_OPSIZE:
71 return(inheritsFrom(child, IC_VEX_XS) ||
72 inheritsFrom(child, IC_VEX_XD) ||
73 inheritsFrom(child, IC_VEX_L) ||
74 inheritsFrom(child, IC_VEX_W) ||
75 inheritsFrom(child, IC_VEX_OPSIZE));
77 return(inheritsFrom(child, IC_VEX_L_XS) ||
78 inheritsFrom(child, IC_VEX_W_XS));
80 return(inheritsFrom(child, IC_VEX_L_XD) ||
81 inheritsFrom(child, IC_VEX_W_XD));
83 return(inheritsFrom(child, IC_VEX_L_XS) ||
84 inheritsFrom(child, IC_VEX_L_XD));
90 return(inheritsFrom(child, IC_VEX_W_XS) ||
91 inheritsFrom(child, IC_VEX_W_XD) ||
92 inheritsFrom(child, IC_VEX_W_OPSIZE));
98 return inheritsFrom(child, IC_VEX_W_OPSIZE);
104 /// outranks - Indicates whether, if an instruction has two different applicable
105 /// classes, which class should be preferred when performing decode. This
106 /// imposes a total ordering (ties are resolved toward "lower")
108 /// @param upper - The class that may be preferable
109 /// @param lower - The class that may be less preferable
110 /// @return - True if upper is to be preferred, false otherwise.
111 static inline bool outranks(InstructionContext upper,
112 InstructionContext lower) {
113 assert(upper < IC_max);
114 assert(lower < IC_max);
116 #define ENUM_ENTRY(n, r, d) r,
117 static int ranks[IC_max] = {
122 return (ranks[upper] > ranks[lower]);
125 /// stringForContext - Returns a string containing the name of a particular
126 /// InstructionContext, usually for diagnostic purposes.
128 /// @param insnContext - The instruction class to transform to a string.
129 /// @return - A statically-allocated string constant that contains the
130 /// name of the instruction class.
131 static inline const char* stringForContext(InstructionContext insnContext) {
132 switch (insnContext) {
134 llvm_unreachable("Unhandled instruction class");
135 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
143 /// stringForOperandType - Like stringForContext, but for OperandTypes.
144 static inline const char* stringForOperandType(OperandType type) {
147 llvm_unreachable("Unhandled type");
148 #define ENUM_ENTRY(i, d) case i: return #i;
154 /// stringForOperandEncoding - like stringForContext, but for
155 /// OperandEncodings.
156 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
159 llvm_unreachable("Unhandled encoding");
160 #define ENUM_ENTRY(i, d) case i: return #i;
166 void DisassemblerTables::emitOneID(raw_ostream &o,
169 bool addComma) const {
171 o.indent(i * 2) << format("0x%hx", id);
173 o.indent(i * 2) << 0;
181 o << InstructionSpecifiers[id].name;
187 /// emitEmptyTable - Emits the modRMEmptyTable, which is used as a ID table by
188 /// all ModR/M decisions for instructions that are invalid for all possible
189 /// ModR/M byte values.
191 /// @param o - The output stream on which to emit the table.
192 /// @param i - The indentation level for that output stream.
193 static void emitEmptyTable(raw_ostream &o, uint32_t &i)
195 o.indent(i * 2) << "static const InstrUID modRMEmptyTable[1] = { 0 };\n";
199 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
200 /// be compacted by eliminating redundant information.
202 /// @param decision - The decision to be compacted.
203 /// @return - The compactest available representation for the decision.
204 static ModRMDecisionType getDecisionType(ModRMDecision &decision)
206 bool satisfiesOneEntry = true;
207 bool satisfiesSplitRM = true;
211 for (index = 0; index < 256; ++index) {
212 if (decision.instructionIDs[index] != decision.instructionIDs[0])
213 satisfiesOneEntry = false;
215 if (((index & 0xc0) == 0xc0) &&
216 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
217 satisfiesSplitRM = false;
219 if (((index & 0xc0) != 0xc0) &&
220 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
221 satisfiesSplitRM = false;
224 if (satisfiesOneEntry)
225 return MODRM_ONEENTRY;
227 if (satisfiesSplitRM)
228 return MODRM_SPLITRM;
233 /// stringForDecisionType - Returns a statically-allocated string corresponding
234 /// to a particular decision type.
236 /// @param dt - The decision type.
237 /// @return - A pointer to the statically-allocated string (e.g.,
238 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
239 static const char* stringForDecisionType(ModRMDecisionType dt)
241 #define ENUM_ENTRY(n) case n: return #n;
244 llvm_unreachable("Unknown decision type");
250 /// stringForModifierType - Returns a statically-allocated string corresponding
251 /// to an opcode modifier type.
253 /// @param mt - The modifier type.
254 /// @return - A pointer to the statically-allocated string (e.g.,
255 /// "MODIFIER_NONE" for MODIFIER_NONE).
256 static const char* stringForModifierType(ModifierType mt)
258 #define ENUM_ENTRY(n) case n: return #n;
261 llvm_unreachable("Unknown modifier type");
267 DisassemblerTables::DisassemblerTables() {
270 for (i = 0; i < 4; i++) {
271 Tables[i] = new ContextDecision;
272 memset(Tables[i], 0, sizeof(ContextDecision));
275 HasConflicts = false;
278 DisassemblerTables::~DisassemblerTables() {
281 for (i = 0; i < 4; i++)
285 void DisassemblerTables::emitModRMDecision(raw_ostream &o1,
289 ModRMDecision &decision)
291 static uint64_t sTableNumber = 0;
292 uint64_t thisTableNumber = sTableNumber;
293 ModRMDecisionType dt = getDecisionType(decision);
296 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
298 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
301 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
302 o2.indent(i2) << "modRMEmptyTable";
305 o2.indent(i2) << "}";
309 o1.indent(i1) << "static const InstrUID modRMTable" << thisTableNumber;
313 llvm_unreachable("Unknown decision type");
325 o1 << " = {" << "\n";
330 llvm_unreachable("Unknown decision type");
332 emitOneID(o1, i1, decision.instructionIDs[0], false);
335 emitOneID(o1, i1, decision.instructionIDs[0x00], true); // mod = 0b00
336 emitOneID(o1, i1, decision.instructionIDs[0xc0], false); // mod = 0b11
339 for (index = 0; index < 256; ++index)
340 emitOneID(o1, i1, decision.instructionIDs[index], index < 255);
345 o1.indent(i1) << "};" << "\n";
348 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
351 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
352 o2.indent(i2) << "modRMTable" << sTableNumber << "\n";
355 o2.indent(i2) << "}";
360 void DisassemblerTables::emitOpcodeDecision(
365 OpcodeDecision &decision) const {
368 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
370 o2.indent(i2) << "{" << "\n";
373 for (index = 0; index < 256; ++index) {
376 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
378 emitModRMDecision(o1, o2, i1, i2, decision.modRMDecisions[index]);
387 o2.indent(i2) << "}" << "\n";
389 o2.indent(i2) << "}" << "\n";
392 void DisassemblerTables::emitContextDecision(
397 ContextDecision &decision,
398 const char* name) const {
399 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
401 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
406 for (index = 0; index < IC_max; ++index) {
407 o2.indent(i2) << "/* ";
408 o2 << stringForContext((InstructionContext)index);
412 emitOpcodeDecision(o1, o2, i1, i2, decision.opcodeDecisions[index]);
414 if (index + 1 < IC_max)
419 o2.indent(i2) << "}" << "\n";
421 o2.indent(i2) << "};" << "\n";
424 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, uint32_t &i)
426 o.indent(i * 2) << "static const struct InstructionSpecifier ";
427 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
431 uint16_t numInstructions = InstructionSpecifiers.size();
432 uint16_t index, operandIndex;
434 for (index = 0; index < numInstructions; ++index) {
435 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
439 stringForModifierType(InstructionSpecifiers[index].modifierType);
442 o.indent(i * 2) << "0x";
443 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
446 o.indent(i * 2) << "{" << "\n";
449 for (operandIndex = 0; operandIndex < X86_MAX_OPERANDS; ++operandIndex) {
450 o.indent(i * 2) << "{ ";
451 o << stringForOperandEncoding(InstructionSpecifiers[index]
452 .operands[operandIndex]
455 o << stringForOperandType(InstructionSpecifiers[index]
456 .operands[operandIndex]
460 if (operandIndex < X86_MAX_OPERANDS - 1)
467 o.indent(i * 2) << "}," << "\n";
469 o.indent(i * 2) << "\"" << InstructionSpecifiers[index].name << "\"";
473 o.indent(i * 2) << "}";
475 if (index + 1 < numInstructions)
482 o.indent(i * 2) << "};" << "\n";
485 void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const {
488 o.indent(i * 2) << "static const InstructionContext " CONTEXTS_STR
492 for (index = 0; index < 256; ++index) {
495 if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
496 o << "IC_VEX_L_OPSIZE";
497 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
499 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
501 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
502 o << "IC_VEX_W_OPSIZE";
503 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
505 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
507 else if (index & ATTR_VEXL)
509 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
511 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
512 o << "IC_VEX_OPSIZE";
513 else if ((index & ATTR_VEX) && (index & ATTR_XD))
515 else if ((index & ATTR_VEX) && (index & ATTR_XS))
517 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
518 o << "IC_64BIT_REXW_XS";
519 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
520 o << "IC_64BIT_REXW_XD";
521 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
522 (index & ATTR_OPSIZE))
523 o << "IC_64BIT_REXW_OPSIZE";
524 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
526 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
528 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
529 o << "IC_64BIT_OPSIZE";
530 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
531 o << "IC_64BIT_REXW";
532 else if ((index & ATTR_64BIT))
534 else if (index & ATTR_XS)
536 else if (index & ATTR_XD)
538 else if (index & ATTR_OPSIZE)
540 else if (index & ATTR_VEX)
550 o << " /* " << index << " */";
556 o.indent(i * 2) << "};" << "\n";
559 void DisassemblerTables::emitContextDecisions(raw_ostream &o1,
564 emitContextDecision(o1, o2, i1, i2, *Tables[0], ONEBYTE_STR);
565 emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR);
566 emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR);
567 emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR);
570 void DisassemblerTables::emit(raw_ostream &o) const {
577 raw_string_ostream o1(s1);
578 raw_string_ostream o2(s2);
580 emitInstructionInfo(o, i2);
583 emitContextTable(o, i2);
586 emitEmptyTable(o1, i1);
587 emitContextDecisions(o1, o2, i1, i2);
596 void DisassemblerTables::setTableFields(ModRMDecision &decision,
597 const ModRMFilter &filter,
602 for (index = 0; index < 256; ++index) {
603 if (filter.accepts(index)) {
604 if (decision.instructionIDs[index] == uid)
607 if (decision.instructionIDs[index] != 0) {
608 InstructionSpecifier &newInfo =
609 InstructionSpecifiers[uid];
610 InstructionSpecifier &previousInfo =
611 InstructionSpecifiers[decision.instructionIDs[index]];
614 continue; // filtered instructions get lowest priority
616 if(previousInfo.name == "NOOP")
617 continue; // special case for XCHG32ar and NOOP
619 if (outranks(previousInfo.insnContext, newInfo.insnContext))
622 if (previousInfo.insnContext == newInfo.insnContext &&
623 !previousInfo.filtered) {
624 errs() << "Error: Primary decode conflict: ";
625 errs() << newInfo.name << " would overwrite " << previousInfo.name;
627 errs() << "ModRM " << index << "\n";
628 errs() << "Opcode " << (uint16_t)opcode << "\n";
629 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
634 decision.instructionIDs[index] = uid;
639 void DisassemblerTables::setTableFields(OpcodeType type,
640 InstructionContext insnContext,
642 const ModRMFilter &filter,
646 ContextDecision &decision = *Tables[type];
648 for (index = 0; index < IC_max; ++index) {
649 if (inheritsFrom((InstructionContext)index,
650 InstructionSpecifiers[uid].insnContext))
651 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],