1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
22 #include "llvm/TableGen/TableGenBackend.h"
26 using namespace X86Disassembler;
28 /// stringForContext - Returns a string containing the name of a particular
29 /// InstructionContext, usually for diagnostic purposes.
31 /// @param insnContext - The instruction class to transform to a string.
32 /// @return - A statically-allocated string constant that contains the
33 /// name of the instruction class.
34 static inline const char* stringForContext(InstructionContext insnContext) {
35 switch (insnContext) {
37 llvm_unreachable("Unhandled instruction class");
38 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
39 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
40 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
41 ENUM_ENTRY(n##_KZ_B, r, d)
48 /// stringForOperandType - Like stringForContext, but for OperandTypes.
49 static inline const char* stringForOperandType(OperandType type) {
52 llvm_unreachable("Unhandled type");
53 #define ENUM_ENTRY(i, d) case i: return #i;
59 /// stringForOperandEncoding - like stringForContext, but for
61 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
64 llvm_unreachable("Unhandled encoding");
65 #define ENUM_ENTRY(i, d) case i: return #i;
71 /// inheritsFrom - Indicates whether all instructions in one class also belong
74 /// @param child - The class that may be the subset
75 /// @param parent - The class that may be the superset
76 /// @return - True if child is a subset of parent, false otherwise.
77 static inline bool inheritsFrom(InstructionContext child,
78 InstructionContext parent,
79 bool VEX_LIG = false) {
85 return(inheritsFrom(child, IC_64BIT) ||
86 inheritsFrom(child, IC_OPSIZE) ||
87 inheritsFrom(child, IC_ADSIZE) ||
88 inheritsFrom(child, IC_XD) ||
89 inheritsFrom(child, IC_XS));
91 return(inheritsFrom(child, IC_64BIT_REXW) ||
92 inheritsFrom(child, IC_64BIT_OPSIZE) ||
93 inheritsFrom(child, IC_64BIT_ADSIZE) ||
94 inheritsFrom(child, IC_64BIT_XD) ||
95 inheritsFrom(child, IC_64BIT_XS));
97 return (inheritsFrom(child, IC_64BIT_OPSIZE) ||
98 inheritsFrom(child, IC_OPSIZE_ADSIZE));
100 return inheritsFrom(child, IC_OPSIZE_ADSIZE);
101 case IC_OPSIZE_ADSIZE:
102 case IC_64BIT_ADSIZE:
105 return inheritsFrom(child, IC_64BIT_XD);
107 return inheritsFrom(child, IC_64BIT_XS);
109 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
111 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
113 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
114 inheritsFrom(child, IC_64BIT_REXW_XD) ||
115 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
116 case IC_64BIT_OPSIZE:
117 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
119 return(inheritsFrom(child, IC_64BIT_REXW_XD));
121 return(inheritsFrom(child, IC_64BIT_REXW_XS));
122 case IC_64BIT_XD_OPSIZE:
123 case IC_64BIT_XS_OPSIZE:
125 case IC_64BIT_REXW_XD:
126 case IC_64BIT_REXW_XS:
127 case IC_64BIT_REXW_OPSIZE:
130 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
131 inheritsFrom(child, IC_VEX_W) ||
132 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
134 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
135 inheritsFrom(child, IC_VEX_W_XS) ||
136 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
138 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
139 inheritsFrom(child, IC_VEX_W_XD) ||
140 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
142 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
143 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
144 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
146 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
148 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
150 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
151 case IC_VEX_W_OPSIZE:
152 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
154 return inheritsFrom(child, IC_VEX_L_W);
156 return inheritsFrom(child, IC_VEX_L_W_XS);
158 return inheritsFrom(child, IC_VEX_L_W_XD);
159 case IC_VEX_L_OPSIZE:
160 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
164 case IC_VEX_L_W_OPSIZE:
167 return inheritsFrom(child, IC_EVEX_W) ||
168 inheritsFrom(child, IC_EVEX_L_W);
170 return inheritsFrom(child, IC_EVEX_W_XS) ||
171 inheritsFrom(child, IC_EVEX_L_W_XS);
173 return inheritsFrom(child, IC_EVEX_W_XD) ||
174 inheritsFrom(child, IC_EVEX_L_W_XD);
176 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
177 inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
181 case IC_EVEX_W_OPSIZE:
186 case IC_EVEX_L_OPSIZE:
191 case IC_EVEX_L_W_OPSIZE:
196 case IC_EVEX_L2_OPSIZE:
199 case IC_EVEX_L2_W_XS:
200 case IC_EVEX_L2_W_XD:
201 case IC_EVEX_L2_W_OPSIZE:
204 return inheritsFrom(child, IC_EVEX_W_K) ||
205 inheritsFrom(child, IC_EVEX_L_W_K);
207 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
208 inheritsFrom(child, IC_EVEX_L_W_XS_K);
210 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
211 inheritsFrom(child, IC_EVEX_L_W_XD_K);
212 case IC_EVEX_OPSIZE_K:
213 case IC_EVEX_OPSIZE_B:
218 case IC_EVEX_W_OPSIZE_K:
219 case IC_EVEX_W_OPSIZE_B:
224 case IC_EVEX_L_OPSIZE_K:
227 case IC_EVEX_W_XS_KZ:
228 case IC_EVEX_W_XD_KZ:
229 case IC_EVEX_W_OPSIZE_KZ:
232 case IC_EVEX_L_XS_KZ:
233 case IC_EVEX_L_XD_KZ:
234 case IC_EVEX_L_OPSIZE_KZ:
237 case IC_EVEX_L_W_XS_K:
238 case IC_EVEX_L_W_XD_K:
239 case IC_EVEX_L_W_OPSIZE_K:
241 case IC_EVEX_L_W_XS_KZ:
242 case IC_EVEX_L_W_XD_KZ:
243 case IC_EVEX_L_W_OPSIZE_KZ:
247 case IC_EVEX_L2_XS_K:
248 case IC_EVEX_L2_XS_B:
249 case IC_EVEX_L2_XD_B:
250 case IC_EVEX_L2_XD_K:
251 case IC_EVEX_L2_OPSIZE_K:
252 case IC_EVEX_L2_OPSIZE_B:
253 case IC_EVEX_L2_OPSIZE_K_B:
255 case IC_EVEX_L2_XS_KZ:
256 case IC_EVEX_L2_XD_KZ:
257 case IC_EVEX_L2_OPSIZE_KZ:
258 case IC_EVEX_L2_OPSIZE_KZ_B:
262 case IC_EVEX_L2_W_XS_K:
263 case IC_EVEX_L2_W_XD_K:
264 case IC_EVEX_L2_W_XD_B:
265 case IC_EVEX_L2_W_OPSIZE_K:
266 case IC_EVEX_L2_W_OPSIZE_B:
267 case IC_EVEX_L2_W_OPSIZE_K_B:
268 case IC_EVEX_L2_W_KZ:
269 case IC_EVEX_L2_W_XS_KZ:
270 case IC_EVEX_L2_W_XD_KZ:
271 case IC_EVEX_L2_W_OPSIZE_KZ:
272 case IC_EVEX_L2_W_OPSIZE_KZ_B:
275 errs() << "Unknown instruction class: " <<
276 stringForContext((InstructionContext)parent) << "\n";
277 llvm_unreachable("Unknown instruction class");
281 /// outranks - Indicates whether, if an instruction has two different applicable
282 /// classes, which class should be preferred when performing decode. This
283 /// imposes a total ordering (ties are resolved toward "lower")
285 /// @param upper - The class that may be preferable
286 /// @param lower - The class that may be less preferable
287 /// @return - True if upper is to be preferred, false otherwise.
288 static inline bool outranks(InstructionContext upper,
289 InstructionContext lower) {
290 assert(upper < IC_max);
291 assert(lower < IC_max);
293 #define ENUM_ENTRY(n, r, d) r,
294 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
295 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \
296 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
297 static int ranks[IC_max] = {
301 #undef ENUM_ENTRY_K_B
303 return (ranks[upper] > ranks[lower]);
306 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
307 /// be compacted by eliminating redundant information.
309 /// @param decision - The decision to be compacted.
310 /// @return - The compactest available representation for the decision.
311 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
312 bool satisfiesOneEntry = true;
313 bool satisfiesSplitRM = true;
314 bool satisfiesSplitReg = true;
315 bool satisfiesSplitMisc = true;
317 for (unsigned index = 0; index < 256; ++index) {
318 if (decision.instructionIDs[index] != decision.instructionIDs[0])
319 satisfiesOneEntry = false;
321 if (((index & 0xc0) == 0xc0) &&
322 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
323 satisfiesSplitRM = false;
325 if (((index & 0xc0) != 0xc0) &&
326 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
327 satisfiesSplitRM = false;
329 if (((index & 0xc0) == 0xc0) &&
330 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
331 satisfiesSplitReg = false;
333 if (((index & 0xc0) != 0xc0) &&
334 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
335 satisfiesSplitMisc = false;
338 if (satisfiesOneEntry)
339 return MODRM_ONEENTRY;
341 if (satisfiesSplitRM)
342 return MODRM_SPLITRM;
344 if (satisfiesSplitReg && satisfiesSplitMisc)
345 return MODRM_SPLITREG;
347 if (satisfiesSplitMisc)
348 return MODRM_SPLITMISC;
353 /// stringForDecisionType - Returns a statically-allocated string corresponding
354 /// to a particular decision type.
356 /// @param dt - The decision type.
357 /// @return - A pointer to the statically-allocated string (e.g.,
358 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
359 static const char* stringForDecisionType(ModRMDecisionType dt) {
360 #define ENUM_ENTRY(n) case n: return #n;
363 llvm_unreachable("Unknown decision type");
369 DisassemblerTables::DisassemblerTables() {
372 for (i = 0; i < array_lengthof(Tables); i++) {
373 Tables[i] = new ContextDecision;
374 memset(Tables[i], 0, sizeof(ContextDecision));
377 HasConflicts = false;
380 DisassemblerTables::~DisassemblerTables() {
383 for (i = 0; i < array_lengthof(Tables); i++)
387 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
388 unsigned &i1, unsigned &i2,
389 unsigned &ModRMTableNum,
390 ModRMDecision &decision) const {
391 static uint32_t sTableNumber = 0;
392 static uint32_t sEntryNumber = 1;
393 ModRMDecisionType dt = getDecisionType(decision);
395 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
397 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
400 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
401 o2.indent(i2) << 0 << " /* EmptyTable */\n";
404 o2.indent(i2) << "}";
408 std::vector<unsigned> ModRMDecision;
412 llvm_unreachable("Unknown decision type");
414 ModRMDecision.push_back(decision.instructionIDs[0]);
417 ModRMDecision.push_back(decision.instructionIDs[0x00]);
418 ModRMDecision.push_back(decision.instructionIDs[0xc0]);
421 for (unsigned index = 0; index < 64; index += 8)
422 ModRMDecision.push_back(decision.instructionIDs[index]);
423 for (unsigned index = 0xc0; index < 256; index += 8)
424 ModRMDecision.push_back(decision.instructionIDs[index]);
426 case MODRM_SPLITMISC:
427 for (unsigned index = 0; index < 64; index += 8)
428 ModRMDecision.push_back(decision.instructionIDs[index]);
429 for (unsigned index = 0xc0; index < 256; ++index)
430 ModRMDecision.push_back(decision.instructionIDs[index]);
433 for (unsigned index = 0; index < 256; ++index)
434 ModRMDecision.push_back(decision.instructionIDs[index]);
438 unsigned &EntryNumber = ModRMTable[ModRMDecision];
439 if (EntryNumber == 0) {
440 EntryNumber = ModRMTableNum;
442 ModRMTableNum += ModRMDecision.size();
443 o1 << "/* Table" << EntryNumber << " */\n";
445 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
446 E = ModRMDecision.end(); I != E; ++I) {
447 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* "
448 << InstructionSpecifiers[*I].name << " */\n";
453 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
456 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
457 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n";
460 o2.indent(i2) << "}";
464 llvm_unreachable("Unknown decision type");
474 case MODRM_SPLITMISC:
475 sEntryNumber += 8 + 64;
482 // We assume that the index can fit into uint16_t.
483 assert(sEntryNumber < 65536U &&
484 "Index into ModRMDecision is too large for uint16_t!");
489 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
490 unsigned &i1, unsigned &i2,
491 unsigned &ModRMTableNum,
492 OpcodeDecision &decision) const {
493 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
495 o2.indent(i2) << "{" << "\n";
498 for (unsigned index = 0; index < 256; ++index) {
501 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
503 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
504 decision.modRMDecisions[index]);
513 o2.indent(i2) << "}" << "\n";
515 o2.indent(i2) << "}" << "\n";
518 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
519 unsigned &i1, unsigned &i2,
520 unsigned &ModRMTableNum,
521 ContextDecision &decision,
522 const char* name) const {
523 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
525 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
528 for (unsigned index = 0; index < IC_max; ++index) {
529 o2.indent(i2) << "/* ";
530 o2 << stringForContext((InstructionContext)index);
534 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
535 decision.opcodeDecisions[index]);
537 if (index + 1 < IC_max)
542 o2.indent(i2) << "}" << "\n";
544 o2.indent(i2) << "};" << "\n";
547 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
549 unsigned NumInstructions = InstructionSpecifiers.size();
551 o << "static const struct OperandSpecifier x86OperandSets[]["
552 << X86_MAX_OPERANDS << "] = {\n";
554 typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
555 std::map<OperandListTy, unsigned> OperandSets;
557 unsigned OperandSetNum = 0;
558 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
559 OperandListTy OperandList;
561 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
563 const char *Encoding =
564 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
565 .operands[OperandIndex].encoding);
567 stringForOperandType((OperandType)InstructionSpecifiers[Index]
568 .operands[OperandIndex].type);
569 OperandList.push_back(std::make_pair(Encoding, Type));
571 unsigned &N = OperandSets[OperandList];
572 if (N != 0) continue;
576 o << " { /* " << (OperandSetNum - 1) << " */\n";
577 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
578 o << " { " << OperandList[i].first << ", "
579 << OperandList[i].second << " },\n";
585 o.indent(i * 2) << "static const struct InstructionSpecifier ";
586 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
590 for (unsigned index = 0; index < NumInstructions; ++index) {
591 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
594 OperandListTy OperandList;
595 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
597 const char *Encoding =
598 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
599 .operands[OperandIndex].encoding);
601 stringForOperandType((OperandType)InstructionSpecifiers[index]
602 .operands[OperandIndex].type);
603 OperandList.push_back(std::make_pair(Encoding, Type));
605 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
607 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
611 o.indent(i * 2) << "}";
613 if (index + 1 < NumInstructions)
620 o.indent(i * 2) << "};" << "\n";
623 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
624 const unsigned int tableSize = 16384;
625 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
626 "[" << tableSize << "] = {\n";
629 for (unsigned index = 0; index < tableSize; ++index) {
632 if (index & ATTR_EVEX) {
634 if (index & ATTR_EVEXL2)
636 else if (index & ATTR_EVEXL)
638 if (index & ATTR_REXW)
640 if (index & ATTR_OPSIZE)
642 else if (index & ATTR_XD)
644 else if (index & ATTR_XS)
646 if (index & ATTR_EVEXKZ)
648 else if (index & ATTR_EVEXK)
650 if (index & ATTR_EVEXB)
653 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
654 o << "IC_VEX_L_W_OPSIZE";
655 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
656 o << "IC_VEX_L_W_XD";
657 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
658 o << "IC_VEX_L_W_XS";
659 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
661 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
662 o << "IC_VEX_L_OPSIZE";
663 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
665 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
667 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
668 o << "IC_VEX_W_OPSIZE";
669 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
671 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
673 else if (index & ATTR_VEXL)
675 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
677 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
678 o << "IC_VEX_OPSIZE";
679 else if ((index & ATTR_VEX) && (index & ATTR_XD))
681 else if ((index & ATTR_VEX) && (index & ATTR_XS))
683 else if (index & ATTR_VEX)
685 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
686 o << "IC_64BIT_REXW_XS";
687 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
688 o << "IC_64BIT_REXW_XD";
689 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
690 (index & ATTR_OPSIZE))
691 o << "IC_64BIT_REXW_OPSIZE";
692 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
693 o << "IC_64BIT_XD_OPSIZE";
694 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
695 o << "IC_64BIT_XS_OPSIZE";
696 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
698 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
700 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
701 o << "IC_64BIT_OPSIZE";
702 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
703 o << "IC_64BIT_ADSIZE";
704 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
705 o << "IC_64BIT_REXW";
706 else if ((index & ATTR_64BIT))
708 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
710 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
712 else if (index & ATTR_XS)
714 else if (index & ATTR_XD)
716 else if (index & ATTR_OPSIZE)
718 else if (index & ATTR_ADSIZE)
723 if (index < tableSize - 1)
728 o << " /* " << index << " */";
734 o.indent(i * 2) << "};" << "\n";
737 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
738 unsigned &i1, unsigned &i2,
739 unsigned &ModRMTableNum) const {
740 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
741 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
742 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
743 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
744 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], THREEBYTEA6_STR);
745 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], THREEBYTEA7_STR);
746 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOP8_MAP_STR);
747 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[7], XOP9_MAP_STR);
748 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[8], XOPA_MAP_STR);
751 void DisassemblerTables::emit(raw_ostream &o) const {
758 raw_string_ostream o1(s1);
759 raw_string_ostream o2(s2);
761 emitInstructionInfo(o, i2);
764 emitContextTable(o, i2);
767 unsigned ModRMTableNum = 0;
769 o << "static const InstrUID modRMTable[] = {\n";
771 std::vector<unsigned> EmptyTable(1, 0);
772 ModRMTable[EmptyTable] = ModRMTableNum;
773 ModRMTableNum += EmptyTable.size();
774 o1 << "/* EmptyTable */\n";
775 o1.indent(i1 * 2) << "0x0,\n";
777 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
788 void DisassemblerTables::setTableFields(ModRMDecision &decision,
789 const ModRMFilter &filter,
792 for (unsigned index = 0; index < 256; ++index) {
793 if (filter.accepts(index)) {
794 if (decision.instructionIDs[index] == uid)
797 if (decision.instructionIDs[index] != 0) {
798 InstructionSpecifier &newInfo =
799 InstructionSpecifiers[uid];
800 InstructionSpecifier &previousInfo =
801 InstructionSpecifiers[decision.instructionIDs[index]];
804 continue; // filtered instructions get lowest priority
806 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
807 newInfo.name == "XCHG32ar" ||
808 newInfo.name == "XCHG32ar64" ||
809 newInfo.name == "XCHG64ar"))
810 continue; // special case for XCHG*ar and NOOP
812 if (outranks(previousInfo.insnContext, newInfo.insnContext))
815 if (previousInfo.insnContext == newInfo.insnContext &&
816 !previousInfo.filtered) {
817 errs() << "Error: Primary decode conflict: ";
818 errs() << newInfo.name << " would overwrite " << previousInfo.name;
820 errs() << "ModRM " << index << "\n";
821 errs() << "Opcode " << (uint16_t)opcode << "\n";
822 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
827 decision.instructionIDs[index] = uid;
832 void DisassemblerTables::setTableFields(OpcodeType type,
833 InstructionContext insnContext,
835 const ModRMFilter &filter,
839 ContextDecision &decision = *Tables[type];
841 for (unsigned index = 0; index < IC_max; ++index) {
842 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
845 if (inheritsFrom((InstructionContext)index,
846 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
847 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],