1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
25 using namespace X86Disassembler;
27 /// stringForContext - Returns a string containing the name of a particular
28 /// InstructionContext, usually for diagnostic purposes.
30 /// @param insnContext - The instruction class to transform to a string.
31 /// @return - A statically-allocated string constant that contains the
32 /// name of the instruction class.
33 static inline const char* stringForContext(InstructionContext insnContext) {
34 switch (insnContext) {
36 llvm_unreachable("Unhandled instruction class");
37 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
38 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
40 ENUM_ENTRY(n##_KZ_B, r, d)
47 /// stringForOperandType - Like stringForContext, but for OperandTypes.
48 static inline const char* stringForOperandType(OperandType type) {
51 llvm_unreachable("Unhandled type");
52 #define ENUM_ENTRY(i, d) case i: return #i;
58 /// stringForOperandEncoding - like stringForContext, but for
60 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
63 llvm_unreachable("Unhandled encoding");
64 #define ENUM_ENTRY(i, d) case i: return #i;
70 /// inheritsFrom - Indicates whether all instructions in one class also belong
73 /// @param child - The class that may be the subset
74 /// @param parent - The class that may be the superset
75 /// @return - True if child is a subset of parent, false otherwise.
76 static inline bool inheritsFrom(InstructionContext child,
77 InstructionContext parent,
78 bool VEX_LIG = false, bool AdSize64 = false) {
84 return(inheritsFrom(child, IC_64BIT, AdSize64) ||
85 inheritsFrom(child, IC_OPSIZE) ||
86 inheritsFrom(child, IC_ADSIZE) ||
87 inheritsFrom(child, IC_XD) ||
88 inheritsFrom(child, IC_XS));
90 return(inheritsFrom(child, IC_64BIT_REXW) ||
91 inheritsFrom(child, IC_64BIT_OPSIZE) ||
92 (!AdSize64 && inheritsFrom(child, IC_64BIT_ADSIZE)) ||
93 inheritsFrom(child, IC_64BIT_XD) ||
94 inheritsFrom(child, IC_64BIT_XS));
96 return inheritsFrom(child, IC_64BIT_OPSIZE) ||
97 inheritsFrom(child, IC_OPSIZE_ADSIZE);
99 return inheritsFrom(child, IC_OPSIZE_ADSIZE);
100 case IC_OPSIZE_ADSIZE:
102 case IC_64BIT_ADSIZE:
103 return inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE);
104 case IC_64BIT_OPSIZE_ADSIZE:
107 return inheritsFrom(child, IC_64BIT_XD);
109 return inheritsFrom(child, IC_64BIT_XS);
111 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
113 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
115 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
116 inheritsFrom(child, IC_64BIT_REXW_XD) ||
117 inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
118 (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE)));
119 case IC_64BIT_OPSIZE:
120 return inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
121 (!AdSize64 && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE)) ||
122 (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE));
124 return(inheritsFrom(child, IC_64BIT_REXW_XD));
126 return(inheritsFrom(child, IC_64BIT_REXW_XS));
127 case IC_64BIT_XD_OPSIZE:
128 case IC_64BIT_XS_OPSIZE:
130 case IC_64BIT_REXW_XD:
131 case IC_64BIT_REXW_XS:
132 case IC_64BIT_REXW_OPSIZE:
133 case IC_64BIT_REXW_ADSIZE:
136 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
137 inheritsFrom(child, IC_VEX_W) ||
138 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
140 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
141 inheritsFrom(child, IC_VEX_W_XS) ||
142 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
144 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
145 inheritsFrom(child, IC_VEX_W_XD) ||
146 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
148 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
149 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
150 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
152 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
154 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
156 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
157 case IC_VEX_W_OPSIZE:
158 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
160 return inheritsFrom(child, IC_VEX_L_W);
162 return inheritsFrom(child, IC_VEX_L_W_XS);
164 return inheritsFrom(child, IC_VEX_L_W_XD);
165 case IC_VEX_L_OPSIZE:
166 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
170 case IC_VEX_L_W_OPSIZE:
173 return inheritsFrom(child, IC_EVEX_W) ||
174 inheritsFrom(child, IC_EVEX_L_W);
176 return inheritsFrom(child, IC_EVEX_W_XS) ||
177 inheritsFrom(child, IC_EVEX_L_W_XS);
179 return inheritsFrom(child, IC_EVEX_W_XD) ||
180 inheritsFrom(child, IC_EVEX_L_W_XD);
182 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
183 inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
189 case IC_EVEX_W_OPSIZE:
197 case IC_EVEX_L_OPSIZE:
202 case IC_EVEX_L_W_OPSIZE:
207 case IC_EVEX_L2_OPSIZE:
210 case IC_EVEX_L2_W_XS:
211 case IC_EVEX_L2_W_XD:
212 case IC_EVEX_L2_W_OPSIZE:
215 return inheritsFrom(child, IC_EVEX_W_K) ||
216 inheritsFrom(child, IC_EVEX_L_W_K);
219 case IC_EVEX_XS_KZ_B:
220 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
221 inheritsFrom(child, IC_EVEX_L_W_XS_K);
224 case IC_EVEX_XD_KZ_B:
225 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
226 inheritsFrom(child, IC_EVEX_L_W_XD_K);
233 return inheritsFrom(child, IC_EVEX_W_XS_KZ) ||
234 inheritsFrom(child, IC_EVEX_L_W_XS_KZ);
236 return inheritsFrom(child, IC_EVEX_W_XD_KZ) ||
237 inheritsFrom(child, IC_EVEX_L_W_XD_KZ);
239 case IC_EVEX_OPSIZE_K:
240 case IC_EVEX_OPSIZE_B:
241 case IC_EVEX_OPSIZE_K_B:
242 case IC_EVEX_OPSIZE_KZ:
243 case IC_EVEX_OPSIZE_KZ_B:
248 case IC_EVEX_W_OPSIZE_K:
249 case IC_EVEX_W_OPSIZE_B:
250 case IC_EVEX_W_OPSIZE_K_B:
255 case IC_EVEX_L_OPSIZE_K:
256 case IC_EVEX_L_OPSIZE_B:
257 case IC_EVEX_L_OPSIZE_K_B:
260 case IC_EVEX_W_XS_KZ:
261 case IC_EVEX_W_XD_KZ:
264 case IC_EVEX_W_XS_K_B:
265 case IC_EVEX_W_XD_K_B:
266 case IC_EVEX_W_XS_KZ_B:
267 case IC_EVEX_W_XD_KZ_B:
268 case IC_EVEX_W_OPSIZE_KZ:
269 case IC_EVEX_W_OPSIZE_KZ_B:
272 case IC_EVEX_L_XS_KZ:
273 case IC_EVEX_L_XD_KZ:
274 case IC_EVEX_L_OPSIZE_KZ:
275 case IC_EVEX_L_OPSIZE_KZ_B:
278 case IC_EVEX_L_W_XS_K:
279 case IC_EVEX_L_W_XD_K:
280 case IC_EVEX_L_W_OPSIZE_K:
281 case IC_EVEX_L_W_OPSIZE_B:
282 case IC_EVEX_L_W_OPSIZE_K_B:
284 case IC_EVEX_L_W_XS_KZ:
285 case IC_EVEX_L_W_XD_KZ:
286 case IC_EVEX_L_W_OPSIZE_KZ:
287 case IC_EVEX_L_W_OPSIZE_KZ_B:
292 case IC_EVEX_L2_KZ_B:
293 case IC_EVEX_L2_XS_K:
294 case IC_EVEX_L2_XS_B:
295 case IC_EVEX_L2_XD_B:
296 case IC_EVEX_L2_XD_K:
297 case IC_EVEX_L2_OPSIZE_K:
298 case IC_EVEX_L2_OPSIZE_B:
299 case IC_EVEX_L2_OPSIZE_K_B:
301 case IC_EVEX_L2_XS_KZ:
302 case IC_EVEX_L2_XD_KZ:
303 case IC_EVEX_L2_OPSIZE_KZ:
304 case IC_EVEX_L2_OPSIZE_KZ_B:
308 case IC_EVEX_L2_W_XS_K:
309 case IC_EVEX_L2_W_XD_K:
310 case IC_EVEX_L2_W_XD_B:
311 case IC_EVEX_L2_W_OPSIZE_K:
312 case IC_EVEX_L2_W_OPSIZE_B:
313 case IC_EVEX_L2_W_OPSIZE_K_B:
314 case IC_EVEX_L2_W_KZ:
315 case IC_EVEX_L2_W_XS_KZ:
316 case IC_EVEX_L2_W_XD_KZ:
317 case IC_EVEX_L2_W_OPSIZE_KZ:
318 case IC_EVEX_L2_W_OPSIZE_KZ_B:
321 errs() << "Unknown instruction class: " <<
322 stringForContext((InstructionContext)parent) << "\n";
323 llvm_unreachable("Unknown instruction class");
327 /// outranks - Indicates whether, if an instruction has two different applicable
328 /// classes, which class should be preferred when performing decode. This
329 /// imposes a total ordering (ties are resolved toward "lower")
331 /// @param upper - The class that may be preferable
332 /// @param lower - The class that may be less preferable
333 /// @return - True if upper is to be preferred, false otherwise.
334 static inline bool outranks(InstructionContext upper,
335 InstructionContext lower) {
336 assert(upper < IC_max);
337 assert(lower < IC_max);
339 #define ENUM_ENTRY(n, r, d) r,
340 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
341 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \
342 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
343 static int ranks[IC_max] = {
347 #undef ENUM_ENTRY_K_B
349 return (ranks[upper] > ranks[lower]);
352 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
353 /// be compacted by eliminating redundant information.
355 /// @param decision - The decision to be compacted.
356 /// @return - The compactest available representation for the decision.
357 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
358 bool satisfiesOneEntry = true;
359 bool satisfiesSplitRM = true;
360 bool satisfiesSplitReg = true;
361 bool satisfiesSplitMisc = true;
363 for (unsigned index = 0; index < 256; ++index) {
364 if (decision.instructionIDs[index] != decision.instructionIDs[0])
365 satisfiesOneEntry = false;
367 if (((index & 0xc0) == 0xc0) &&
368 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
369 satisfiesSplitRM = false;
371 if (((index & 0xc0) != 0xc0) &&
372 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
373 satisfiesSplitRM = false;
375 if (((index & 0xc0) == 0xc0) &&
376 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
377 satisfiesSplitReg = false;
379 if (((index & 0xc0) != 0xc0) &&
380 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
381 satisfiesSplitMisc = false;
384 if (satisfiesOneEntry)
385 return MODRM_ONEENTRY;
387 if (satisfiesSplitRM)
388 return MODRM_SPLITRM;
390 if (satisfiesSplitReg && satisfiesSplitMisc)
391 return MODRM_SPLITREG;
393 if (satisfiesSplitMisc)
394 return MODRM_SPLITMISC;
399 /// stringForDecisionType - Returns a statically-allocated string corresponding
400 /// to a particular decision type.
402 /// @param dt - The decision type.
403 /// @return - A pointer to the statically-allocated string (e.g.,
404 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
405 static const char* stringForDecisionType(ModRMDecisionType dt) {
406 #define ENUM_ENTRY(n) case n: return #n;
409 llvm_unreachable("Unknown decision type");
415 DisassemblerTables::DisassemblerTables() {
418 for (i = 0; i < array_lengthof(Tables); i++) {
419 Tables[i] = new ContextDecision;
420 memset(Tables[i], 0, sizeof(ContextDecision));
423 HasConflicts = false;
426 DisassemblerTables::~DisassemblerTables() {
429 for (i = 0; i < array_lengthof(Tables); i++)
433 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
434 unsigned &i1, unsigned &i2,
435 unsigned &ModRMTableNum,
436 ModRMDecision &decision) const {
437 static uint32_t sTableNumber = 0;
438 static uint32_t sEntryNumber = 1;
439 ModRMDecisionType dt = getDecisionType(decision);
441 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
443 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
446 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
447 o2.indent(i2) << 0 << " /* EmptyTable */\n";
450 o2.indent(i2) << "}";
454 std::vector<unsigned> ModRMDecision;
458 llvm_unreachable("Unknown decision type");
460 ModRMDecision.push_back(decision.instructionIDs[0]);
463 ModRMDecision.push_back(decision.instructionIDs[0x00]);
464 ModRMDecision.push_back(decision.instructionIDs[0xc0]);
467 for (unsigned index = 0; index < 64; index += 8)
468 ModRMDecision.push_back(decision.instructionIDs[index]);
469 for (unsigned index = 0xc0; index < 256; index += 8)
470 ModRMDecision.push_back(decision.instructionIDs[index]);
472 case MODRM_SPLITMISC:
473 for (unsigned index = 0; index < 64; index += 8)
474 ModRMDecision.push_back(decision.instructionIDs[index]);
475 for (unsigned index = 0xc0; index < 256; ++index)
476 ModRMDecision.push_back(decision.instructionIDs[index]);
479 for (unsigned index = 0; index < 256; ++index)
480 ModRMDecision.push_back(decision.instructionIDs[index]);
484 unsigned &EntryNumber = ModRMTable[ModRMDecision];
485 if (EntryNumber == 0) {
486 EntryNumber = ModRMTableNum;
488 ModRMTableNum += ModRMDecision.size();
489 o1 << "/* Table" << EntryNumber << " */\n";
491 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
492 E = ModRMDecision.end(); I != E; ++I) {
493 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* "
494 << InstructionSpecifiers[*I].name << " */\n";
499 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
502 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
503 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n";
506 o2.indent(i2) << "}";
510 llvm_unreachable("Unknown decision type");
520 case MODRM_SPLITMISC:
521 sEntryNumber += 8 + 64;
528 // We assume that the index can fit into uint16_t.
529 assert(sEntryNumber < 65536U &&
530 "Index into ModRMDecision is too large for uint16_t!");
535 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
536 unsigned &i1, unsigned &i2,
537 unsigned &ModRMTableNum,
538 OpcodeDecision &decision) const {
539 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
541 o2.indent(i2) << "{" << "\n";
544 for (unsigned index = 0; index < 256; ++index) {
547 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
549 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
550 decision.modRMDecisions[index]);
559 o2.indent(i2) << "}" << "\n";
561 o2.indent(i2) << "}" << "\n";
564 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
565 unsigned &i1, unsigned &i2,
566 unsigned &ModRMTableNum,
567 ContextDecision &decision,
568 const char* name) const {
569 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
571 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
574 for (unsigned index = 0; index < IC_max; ++index) {
575 o2.indent(i2) << "/* ";
576 o2 << stringForContext((InstructionContext)index);
580 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
581 decision.opcodeDecisions[index]);
583 if (index + 1 < IC_max)
588 o2.indent(i2) << "}" << "\n";
590 o2.indent(i2) << "};" << "\n";
593 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
595 unsigned NumInstructions = InstructionSpecifiers.size();
597 o << "static const struct OperandSpecifier x86OperandSets[]["
598 << X86_MAX_OPERANDS << "] = {\n";
600 typedef SmallVector<std::pair<OperandEncoding, OperandType>,
601 X86_MAX_OPERANDS> OperandListTy;
602 std::map<OperandListTy, unsigned> OperandSets;
604 unsigned OperandSetNum = 0;
605 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
606 OperandListTy OperandList;
608 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
610 OperandEncoding Encoding = (OperandEncoding)InstructionSpecifiers[Index]
611 .operands[OperandIndex].encoding;
612 OperandType Type = (OperandType)InstructionSpecifiers[Index]
613 .operands[OperandIndex].type;
614 OperandList.push_back(std::make_pair(Encoding, Type));
616 unsigned &N = OperandSets[OperandList];
617 if (N != 0) continue;
621 o << " { /* " << (OperandSetNum - 1) << " */\n";
622 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
623 const char *Encoding = stringForOperandEncoding(OperandList[i].first);
624 const char *Type = stringForOperandType(OperandList[i].second);
625 o << " { " << Encoding << ", " << Type << " },\n";
631 o.indent(i * 2) << "static const struct InstructionSpecifier ";
632 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
636 for (unsigned index = 0; index < NumInstructions; ++index) {
637 o.indent(i * 2) << "{ /* " << index << " */\n";
640 OperandListTy OperandList;
641 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
643 OperandEncoding Encoding = (OperandEncoding)InstructionSpecifiers[index]
644 .operands[OperandIndex].encoding;
645 OperandType Type = (OperandType)InstructionSpecifiers[index]
646 .operands[OperandIndex].type;
647 OperandList.push_back(std::make_pair(Encoding, Type));
649 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
651 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */\n";
654 o.indent(i * 2) << "},\n";
658 o.indent(i * 2) << "};" << "\n";
661 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
662 const unsigned int tableSize = 16384;
663 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
664 "[" << tableSize << "] = {\n";
667 for (unsigned index = 0; index < tableSize; ++index) {
670 if (index & ATTR_EVEX) {
672 if (index & ATTR_EVEXL2)
674 else if (index & ATTR_EVEXL)
676 if (index & ATTR_REXW)
678 if (index & ATTR_OPSIZE)
680 else if (index & ATTR_XD)
682 else if (index & ATTR_XS)
684 if (index & ATTR_EVEXKZ)
686 else if (index & ATTR_EVEXK)
688 if (index & ATTR_EVEXB)
691 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
692 o << "IC_VEX_L_W_OPSIZE";
693 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
694 o << "IC_VEX_L_W_XD";
695 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
696 o << "IC_VEX_L_W_XS";
697 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
699 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
700 o << "IC_VEX_L_OPSIZE";
701 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
703 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
705 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
706 o << "IC_VEX_W_OPSIZE";
707 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
709 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
711 else if (index & ATTR_VEXL)
713 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
715 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
716 o << "IC_VEX_OPSIZE";
717 else if ((index & ATTR_VEX) && (index & ATTR_XD))
719 else if ((index & ATTR_VEX) && (index & ATTR_XS))
721 else if (index & ATTR_VEX)
723 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
724 o << "IC_64BIT_REXW_XS";
725 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
726 o << "IC_64BIT_REXW_XD";
727 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
728 (index & ATTR_OPSIZE))
729 o << "IC_64BIT_REXW_OPSIZE";
730 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
731 (index & ATTR_ADSIZE))
732 o << "IC_64BIT_REXW_ADSIZE";
733 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
734 o << "IC_64BIT_XD_OPSIZE";
735 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
736 o << "IC_64BIT_XS_OPSIZE";
737 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
739 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
741 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE) &&
742 (index & ATTR_ADSIZE))
743 o << "IC_64BIT_OPSIZE_ADSIZE";
744 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
745 o << "IC_64BIT_OPSIZE";
746 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
747 o << "IC_64BIT_ADSIZE";
748 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
749 o << "IC_64BIT_REXW";
750 else if ((index & ATTR_64BIT))
752 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
754 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
756 else if (index & ATTR_XS)
758 else if (index & ATTR_XD)
760 else if ((index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
761 o << "IC_OPSIZE_ADSIZE";
762 else if (index & ATTR_OPSIZE)
764 else if (index & ATTR_ADSIZE)
769 if (index < tableSize - 1)
774 o << " /* " << index << " */";
780 o.indent(i * 2) << "};" << "\n";
783 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
784 unsigned &i1, unsigned &i2,
785 unsigned &ModRMTableNum) const {
786 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
787 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
788 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
789 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
790 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR);
791 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR);
792 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR);
795 void DisassemblerTables::emit(raw_ostream &o) const {
802 raw_string_ostream o1(s1);
803 raw_string_ostream o2(s2);
805 emitInstructionInfo(o, i2);
808 emitContextTable(o, i2);
811 unsigned ModRMTableNum = 0;
813 o << "static const InstrUID modRMTable[] = {\n";
815 std::vector<unsigned> EmptyTable(1, 0);
816 ModRMTable[EmptyTable] = ModRMTableNum;
817 ModRMTableNum += EmptyTable.size();
818 o1 << "/* EmptyTable */\n";
819 o1.indent(i1 * 2) << "0x0,\n";
821 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
832 void DisassemblerTables::setTableFields(ModRMDecision &decision,
833 const ModRMFilter &filter,
836 for (unsigned index = 0; index < 256; ++index) {
837 if (filter.accepts(index)) {
838 if (decision.instructionIDs[index] == uid)
841 if (decision.instructionIDs[index] != 0) {
842 InstructionSpecifier &newInfo =
843 InstructionSpecifiers[uid];
844 InstructionSpecifier &previousInfo =
845 InstructionSpecifiers[decision.instructionIDs[index]];
847 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
848 newInfo.name == "XCHG32ar" ||
849 newInfo.name == "XCHG32ar64" ||
850 newInfo.name == "XCHG64ar"))
851 continue; // special case for XCHG*ar and NOOP
853 if (outranks(previousInfo.insnContext, newInfo.insnContext))
856 if (previousInfo.insnContext == newInfo.insnContext) {
857 errs() << "Error: Primary decode conflict: ";
858 errs() << newInfo.name << " would overwrite " << previousInfo.name;
860 errs() << "ModRM " << index << "\n";
861 errs() << "Opcode " << (uint16_t)opcode << "\n";
862 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
867 decision.instructionIDs[index] = uid;
872 void DisassemblerTables::setTableFields(OpcodeType type,
873 InstructionContext insnContext,
875 const ModRMFilter &filter,
879 unsigned addressSize) {
880 ContextDecision &decision = *Tables[type];
882 for (unsigned index = 0; index < IC_max; ++index) {
883 if ((is32bit || addressSize == 16) &&
884 inheritsFrom((InstructionContext)index, IC_64BIT))
887 bool adSize64 = addressSize == 64;
888 if (inheritsFrom((InstructionContext)index,
889 InstructionSpecifiers[uid].insnContext, ignoresVEX_L,
891 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],