1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
25 using namespace X86Disassembler;
27 /// stringForContext - Returns a string containing the name of a particular
28 /// InstructionContext, usually for diagnostic purposes.
30 /// @param insnContext - The instruction class to transform to a string.
31 /// @return - A statically-allocated string constant that contains the
32 /// name of the instruction class.
33 static inline const char* stringForContext(InstructionContext insnContext) {
34 switch (insnContext) {
36 llvm_unreachable("Unhandled instruction class");
37 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
38 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
40 ENUM_ENTRY(n##_KZ_B, r, d)
47 /// stringForOperandType - Like stringForContext, but for OperandTypes.
48 static inline const char* stringForOperandType(OperandType type) {
51 llvm_unreachable("Unhandled type");
52 #define ENUM_ENTRY(i, d) case i: return #i;
58 /// stringForOperandEncoding - like stringForContext, but for
60 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
63 llvm_unreachable("Unhandled encoding");
64 #define ENUM_ENTRY(i, d) case i: return #i;
70 /// inheritsFrom - Indicates whether all instructions in one class also belong
73 /// @param child - The class that may be the subset
74 /// @param parent - The class that may be the superset
75 /// @return - True if child is a subset of parent, false otherwise.
76 static inline bool inheritsFrom(InstructionContext child,
77 InstructionContext parent,
78 bool VEX_LIG = false) {
84 return(inheritsFrom(child, IC_64BIT) ||
85 inheritsFrom(child, IC_OPSIZE) ||
86 inheritsFrom(child, IC_ADSIZE) ||
87 inheritsFrom(child, IC_XD) ||
88 inheritsFrom(child, IC_XS));
90 return(inheritsFrom(child, IC_64BIT_REXW) ||
91 inheritsFrom(child, IC_64BIT_OPSIZE) ||
92 inheritsFrom(child, IC_64BIT_ADSIZE) ||
93 inheritsFrom(child, IC_64BIT_XD) ||
94 inheritsFrom(child, IC_64BIT_XS));
96 return inheritsFrom(child, IC_64BIT_OPSIZE);
101 return inheritsFrom(child, IC_64BIT_XD);
103 return inheritsFrom(child, IC_64BIT_XS);
105 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
107 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
109 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
110 inheritsFrom(child, IC_64BIT_REXW_XD) ||
111 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
112 case IC_64BIT_OPSIZE:
113 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
115 return(inheritsFrom(child, IC_64BIT_REXW_XD));
117 return(inheritsFrom(child, IC_64BIT_REXW_XS));
118 case IC_64BIT_XD_OPSIZE:
119 case IC_64BIT_XS_OPSIZE:
121 case IC_64BIT_REXW_XD:
122 case IC_64BIT_REXW_XS:
123 case IC_64BIT_REXW_OPSIZE:
126 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
127 inheritsFrom(child, IC_VEX_W) ||
128 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
130 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
131 inheritsFrom(child, IC_VEX_W_XS) ||
132 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
134 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
135 inheritsFrom(child, IC_VEX_W_XD) ||
136 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
138 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
139 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
140 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
142 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
144 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
146 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
147 case IC_VEX_W_OPSIZE:
148 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
150 return inheritsFrom(child, IC_VEX_L_W);
152 return inheritsFrom(child, IC_VEX_L_W_XS);
154 return inheritsFrom(child, IC_VEX_L_W_XD);
155 case IC_VEX_L_OPSIZE:
156 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
160 case IC_VEX_L_W_OPSIZE:
163 return inheritsFrom(child, IC_EVEX_W) ||
164 inheritsFrom(child, IC_EVEX_L_W);
166 return inheritsFrom(child, IC_EVEX_W_XS) ||
167 inheritsFrom(child, IC_EVEX_L_W_XS);
169 return inheritsFrom(child, IC_EVEX_W_XD) ||
170 inheritsFrom(child, IC_EVEX_L_W_XD);
172 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
173 inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
177 case IC_EVEX_W_OPSIZE:
182 case IC_EVEX_L_OPSIZE:
187 case IC_EVEX_L_W_OPSIZE:
192 case IC_EVEX_L2_OPSIZE:
195 case IC_EVEX_L2_W_XS:
196 case IC_EVEX_L2_W_XD:
197 case IC_EVEX_L2_W_OPSIZE:
200 return inheritsFrom(child, IC_EVEX_W_K) ||
201 inheritsFrom(child, IC_EVEX_L_W_K);
203 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
204 inheritsFrom(child, IC_EVEX_L_W_XS_K);
206 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
207 inheritsFrom(child, IC_EVEX_L_W_XD_K);
212 return inheritsFrom(child, IC_EVEX_W_XS_KZ) ||
213 inheritsFrom(child, IC_EVEX_L_W_XS_KZ);
215 return inheritsFrom(child, IC_EVEX_W_XD_KZ) ||
216 inheritsFrom(child, IC_EVEX_L_W_XD_KZ);
218 case IC_EVEX_OPSIZE_K:
219 case IC_EVEX_OPSIZE_B:
220 case IC_EVEX_OPSIZE_KZ:
225 case IC_EVEX_W_OPSIZE_K:
226 case IC_EVEX_W_OPSIZE_B:
231 case IC_EVEX_L_OPSIZE_K:
234 case IC_EVEX_W_XS_KZ:
235 case IC_EVEX_W_XD_KZ:
236 case IC_EVEX_W_OPSIZE_KZ:
239 case IC_EVEX_L_XS_KZ:
240 case IC_EVEX_L_XD_KZ:
241 case IC_EVEX_L_OPSIZE_KZ:
244 case IC_EVEX_L_W_XS_K:
245 case IC_EVEX_L_W_XD_K:
246 case IC_EVEX_L_W_OPSIZE_K:
248 case IC_EVEX_L_W_XS_KZ:
249 case IC_EVEX_L_W_XD_KZ:
250 case IC_EVEX_L_W_OPSIZE_KZ:
255 case IC_EVEX_L2_KZ_B:
256 case IC_EVEX_L2_XS_K:
257 case IC_EVEX_L2_XS_B:
258 case IC_EVEX_L2_XD_B:
259 case IC_EVEX_L2_XD_K:
260 case IC_EVEX_L2_OPSIZE_K:
261 case IC_EVEX_L2_OPSIZE_B:
262 case IC_EVEX_L2_OPSIZE_K_B:
264 case IC_EVEX_L2_XS_KZ:
265 case IC_EVEX_L2_XD_KZ:
266 case IC_EVEX_L2_OPSIZE_KZ:
267 case IC_EVEX_L2_OPSIZE_KZ_B:
271 case IC_EVEX_L2_W_XS_K:
272 case IC_EVEX_L2_W_XD_K:
273 case IC_EVEX_L2_W_XD_B:
274 case IC_EVEX_L2_W_OPSIZE_K:
275 case IC_EVEX_L2_W_OPSIZE_B:
276 case IC_EVEX_L2_W_OPSIZE_K_B:
277 case IC_EVEX_L2_W_KZ:
278 case IC_EVEX_L2_W_XS_KZ:
279 case IC_EVEX_L2_W_XD_KZ:
280 case IC_EVEX_L2_W_OPSIZE_KZ:
281 case IC_EVEX_L2_W_OPSIZE_KZ_B:
284 errs() << "Unknown instruction class: " <<
285 stringForContext((InstructionContext)parent) << "\n";
286 llvm_unreachable("Unknown instruction class");
290 /// outranks - Indicates whether, if an instruction has two different applicable
291 /// classes, which class should be preferred when performing decode. This
292 /// imposes a total ordering (ties are resolved toward "lower")
294 /// @param upper - The class that may be preferable
295 /// @param lower - The class that may be less preferable
296 /// @return - True if upper is to be preferred, false otherwise.
297 static inline bool outranks(InstructionContext upper,
298 InstructionContext lower) {
299 assert(upper < IC_max);
300 assert(lower < IC_max);
302 #define ENUM_ENTRY(n, r, d) r,
303 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
304 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \
305 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
306 static int ranks[IC_max] = {
310 #undef ENUM_ENTRY_K_B
312 return (ranks[upper] > ranks[lower]);
315 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
316 /// be compacted by eliminating redundant information.
318 /// @param decision - The decision to be compacted.
319 /// @return - The compactest available representation for the decision.
320 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
321 bool satisfiesOneEntry = true;
322 bool satisfiesSplitRM = true;
323 bool satisfiesSplitReg = true;
324 bool satisfiesSplitMisc = true;
326 for (unsigned index = 0; index < 256; ++index) {
327 if (decision.instructionIDs[index] != decision.instructionIDs[0])
328 satisfiesOneEntry = false;
330 if (((index & 0xc0) == 0xc0) &&
331 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
332 satisfiesSplitRM = false;
334 if (((index & 0xc0) != 0xc0) &&
335 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
336 satisfiesSplitRM = false;
338 if (((index & 0xc0) == 0xc0) &&
339 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
340 satisfiesSplitReg = false;
342 if (((index & 0xc0) != 0xc0) &&
343 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
344 satisfiesSplitMisc = false;
347 if (satisfiesOneEntry)
348 return MODRM_ONEENTRY;
350 if (satisfiesSplitRM)
351 return MODRM_SPLITRM;
353 if (satisfiesSplitReg && satisfiesSplitMisc)
354 return MODRM_SPLITREG;
356 if (satisfiesSplitMisc)
357 return MODRM_SPLITMISC;
362 /// stringForDecisionType - Returns a statically-allocated string corresponding
363 /// to a particular decision type.
365 /// @param dt - The decision type.
366 /// @return - A pointer to the statically-allocated string (e.g.,
367 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
368 static const char* stringForDecisionType(ModRMDecisionType dt) {
369 #define ENUM_ENTRY(n) case n: return #n;
372 llvm_unreachable("Unknown decision type");
378 DisassemblerTables::DisassemblerTables() {
381 for (i = 0; i < array_lengthof(Tables); i++) {
382 Tables[i] = new ContextDecision;
383 memset(Tables[i], 0, sizeof(ContextDecision));
386 HasConflicts = false;
389 DisassemblerTables::~DisassemblerTables() {
392 for (i = 0; i < array_lengthof(Tables); i++)
396 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
397 unsigned &i1, unsigned &i2,
398 unsigned &ModRMTableNum,
399 ModRMDecision &decision) const {
400 static uint32_t sTableNumber = 0;
401 static uint32_t sEntryNumber = 1;
402 ModRMDecisionType dt = getDecisionType(decision);
404 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
406 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
409 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
410 o2.indent(i2) << 0 << " /* EmptyTable */\n";
413 o2.indent(i2) << "}";
417 std::vector<unsigned> ModRMDecision;
421 llvm_unreachable("Unknown decision type");
423 ModRMDecision.push_back(decision.instructionIDs[0]);
426 ModRMDecision.push_back(decision.instructionIDs[0x00]);
427 ModRMDecision.push_back(decision.instructionIDs[0xc0]);
430 for (unsigned index = 0; index < 64; index += 8)
431 ModRMDecision.push_back(decision.instructionIDs[index]);
432 for (unsigned index = 0xc0; index < 256; index += 8)
433 ModRMDecision.push_back(decision.instructionIDs[index]);
435 case MODRM_SPLITMISC:
436 for (unsigned index = 0; index < 64; index += 8)
437 ModRMDecision.push_back(decision.instructionIDs[index]);
438 for (unsigned index = 0xc0; index < 256; ++index)
439 ModRMDecision.push_back(decision.instructionIDs[index]);
442 for (unsigned index = 0; index < 256; ++index)
443 ModRMDecision.push_back(decision.instructionIDs[index]);
447 unsigned &EntryNumber = ModRMTable[ModRMDecision];
448 if (EntryNumber == 0) {
449 EntryNumber = ModRMTableNum;
451 ModRMTableNum += ModRMDecision.size();
452 o1 << "/* Table" << EntryNumber << " */\n";
454 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
455 E = ModRMDecision.end(); I != E; ++I) {
456 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* "
457 << InstructionSpecifiers[*I].name << " */\n";
462 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
465 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
466 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n";
469 o2.indent(i2) << "}";
473 llvm_unreachable("Unknown decision type");
483 case MODRM_SPLITMISC:
484 sEntryNumber += 8 + 64;
491 // We assume that the index can fit into uint16_t.
492 assert(sEntryNumber < 65536U &&
493 "Index into ModRMDecision is too large for uint16_t!");
498 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
499 unsigned &i1, unsigned &i2,
500 unsigned &ModRMTableNum,
501 OpcodeDecision &decision) const {
502 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
504 o2.indent(i2) << "{" << "\n";
507 for (unsigned index = 0; index < 256; ++index) {
510 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
512 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
513 decision.modRMDecisions[index]);
522 o2.indent(i2) << "}" << "\n";
524 o2.indent(i2) << "}" << "\n";
527 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
528 unsigned &i1, unsigned &i2,
529 unsigned &ModRMTableNum,
530 ContextDecision &decision,
531 const char* name) const {
532 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
534 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
537 for (unsigned index = 0; index < IC_max; ++index) {
538 o2.indent(i2) << "/* ";
539 o2 << stringForContext((InstructionContext)index);
543 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
544 decision.opcodeDecisions[index]);
546 if (index + 1 < IC_max)
551 o2.indent(i2) << "}" << "\n";
553 o2.indent(i2) << "};" << "\n";
556 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
558 unsigned NumInstructions = InstructionSpecifiers.size();
560 o << "static const struct OperandSpecifier x86OperandSets[]["
561 << X86_MAX_OPERANDS << "] = {\n";
563 typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
564 std::map<OperandListTy, unsigned> OperandSets;
566 unsigned OperandSetNum = 0;
567 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
568 OperandListTy OperandList;
570 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
572 const char *Encoding =
573 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
574 .operands[OperandIndex].encoding);
576 stringForOperandType((OperandType)InstructionSpecifiers[Index]
577 .operands[OperandIndex].type);
578 OperandList.push_back(std::make_pair(Encoding, Type));
580 unsigned &N = OperandSets[OperandList];
581 if (N != 0) continue;
585 o << " { /* " << (OperandSetNum - 1) << " */\n";
586 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
587 o << " { " << OperandList[i].first << ", "
588 << OperandList[i].second << " },\n";
594 o.indent(i * 2) << "static const struct InstructionSpecifier ";
595 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
599 for (unsigned index = 0; index < NumInstructions; ++index) {
600 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
603 OperandListTy OperandList;
604 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
606 const char *Encoding =
607 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
608 .operands[OperandIndex].encoding);
610 stringForOperandType((OperandType)InstructionSpecifiers[index]
611 .operands[OperandIndex].type);
612 OperandList.push_back(std::make_pair(Encoding, Type));
614 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
616 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
620 o.indent(i * 2) << "}";
622 if (index + 1 < NumInstructions)
629 o.indent(i * 2) << "};" << "\n";
632 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
633 const unsigned int tableSize = 16384;
634 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
635 "[" << tableSize << "] = {\n";
638 for (unsigned index = 0; index < tableSize; ++index) {
641 if (index & ATTR_EVEX) {
643 if (index & ATTR_EVEXL2)
645 else if (index & ATTR_EVEXL)
647 if (index & ATTR_REXW)
649 if (index & ATTR_OPSIZE)
651 else if (index & ATTR_XD)
653 else if (index & ATTR_XS)
655 if (index & ATTR_EVEXKZ)
657 else if (index & ATTR_EVEXK)
659 if (index & ATTR_EVEXB)
662 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
663 o << "IC_VEX_L_W_OPSIZE";
664 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
665 o << "IC_VEX_L_W_XD";
666 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
667 o << "IC_VEX_L_W_XS";
668 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
670 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
671 o << "IC_VEX_L_OPSIZE";
672 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
674 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
676 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
677 o << "IC_VEX_W_OPSIZE";
678 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
680 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
682 else if (index & ATTR_VEXL)
684 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
686 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
687 o << "IC_VEX_OPSIZE";
688 else if ((index & ATTR_VEX) && (index & ATTR_XD))
690 else if ((index & ATTR_VEX) && (index & ATTR_XS))
692 else if (index & ATTR_VEX)
694 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
695 o << "IC_64BIT_REXW_XS";
696 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
697 o << "IC_64BIT_REXW_XD";
698 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
699 (index & ATTR_OPSIZE))
700 o << "IC_64BIT_REXW_OPSIZE";
701 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
702 o << "IC_64BIT_XD_OPSIZE";
703 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
704 o << "IC_64BIT_XS_OPSIZE";
705 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
707 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
709 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
710 o << "IC_64BIT_OPSIZE";
711 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
712 o << "IC_64BIT_ADSIZE";
713 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
714 o << "IC_64BIT_REXW";
715 else if ((index & ATTR_64BIT))
717 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
719 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
721 else if (index & ATTR_XS)
723 else if (index & ATTR_XD)
725 else if (index & ATTR_OPSIZE)
727 else if (index & ATTR_ADSIZE)
732 if (index < tableSize - 1)
737 o << " /* " << index << " */";
743 o.indent(i * 2) << "};" << "\n";
746 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
747 unsigned &i1, unsigned &i2,
748 unsigned &ModRMTableNum) const {
749 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
750 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
751 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
752 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
753 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR);
754 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR);
755 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR);
758 void DisassemblerTables::emit(raw_ostream &o) const {
765 raw_string_ostream o1(s1);
766 raw_string_ostream o2(s2);
768 emitInstructionInfo(o, i2);
771 emitContextTable(o, i2);
774 unsigned ModRMTableNum = 0;
776 o << "static const InstrUID modRMTable[] = {\n";
778 std::vector<unsigned> EmptyTable(1, 0);
779 ModRMTable[EmptyTable] = ModRMTableNum;
780 ModRMTableNum += EmptyTable.size();
781 o1 << "/* EmptyTable */\n";
782 o1.indent(i1 * 2) << "0x0,\n";
784 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
795 void DisassemblerTables::setTableFields(ModRMDecision &decision,
796 const ModRMFilter &filter,
799 for (unsigned index = 0; index < 256; ++index) {
800 if (filter.accepts(index)) {
801 if (decision.instructionIDs[index] == uid)
804 if (decision.instructionIDs[index] != 0) {
805 InstructionSpecifier &newInfo =
806 InstructionSpecifiers[uid];
807 InstructionSpecifier &previousInfo =
808 InstructionSpecifiers[decision.instructionIDs[index]];
810 // Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the
811 // presence of the AdSize prefix. However, the disassembler doesn't
812 // care about that difference in the instruction definition; it
813 // handles 16-bit vs. 32-bit addressing for itself based purely
814 // on the 0x67 prefix and the CPU mode. So there's no need to
815 // disambiguate between them; just let them conflict/coexist.
816 if (previousInfo.name + "_16" == newInfo.name)
819 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
820 newInfo.name == "XCHG32ar" ||
821 newInfo.name == "XCHG32ar64" ||
822 newInfo.name == "XCHG64ar"))
823 continue; // special case for XCHG*ar and NOOP
825 if (outranks(previousInfo.insnContext, newInfo.insnContext))
828 if (previousInfo.insnContext == newInfo.insnContext) {
829 errs() << "Error: Primary decode conflict: ";
830 errs() << newInfo.name << " would overwrite " << previousInfo.name;
832 errs() << "ModRM " << index << "\n";
833 errs() << "Opcode " << (uint16_t)opcode << "\n";
834 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
839 decision.instructionIDs[index] = uid;
844 void DisassemblerTables::setTableFields(OpcodeType type,
845 InstructionContext insnContext,
847 const ModRMFilter &filter,
851 ContextDecision &decision = *Tables[type];
853 for (unsigned index = 0; index < IC_max; ++index) {
854 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
857 if (inheritsFrom((InstructionContext)index,
858 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
859 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],