1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
22 #include "llvm/TableGen/TableGenBackend.h"
26 using namespace X86Disassembler;
28 /// stringForContext - Returns a string containing the name of a particular
29 /// InstructionContext, usually for diagnostic purposes.
31 /// @param insnContext - The instruction class to transform to a string.
32 /// @return - A statically-allocated string constant that contains the
33 /// name of the instruction class.
34 static inline const char* stringForContext(InstructionContext insnContext) {
35 switch (insnContext) {
37 llvm_unreachable("Unhandled instruction class");
38 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
39 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
40 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
41 ENUM_ENTRY(n##_KZ_B, r, d)
48 /// stringForOperandType - Like stringForContext, but for OperandTypes.
49 static inline const char* stringForOperandType(OperandType type) {
52 llvm_unreachable("Unhandled type");
53 #define ENUM_ENTRY(i, d) case i: return #i;
59 /// stringForOperandEncoding - like stringForContext, but for
61 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
64 llvm_unreachable("Unhandled encoding");
65 #define ENUM_ENTRY(i, d) case i: return #i;
71 /// inheritsFrom - Indicates whether all instructions in one class also belong
74 /// @param child - The class that may be the subset
75 /// @param parent - The class that may be the superset
76 /// @return - True if child is a subset of parent, false otherwise.
77 static inline bool inheritsFrom(InstructionContext child,
78 InstructionContext parent,
79 bool VEX_LIG = false) {
85 return(inheritsFrom(child, IC_64BIT) ||
86 inheritsFrom(child, IC_OPSIZE) ||
87 inheritsFrom(child, IC_ADSIZE) ||
88 inheritsFrom(child, IC_XD) ||
89 inheritsFrom(child, IC_XS));
91 return(inheritsFrom(child, IC_64BIT_REXW) ||
92 inheritsFrom(child, IC_64BIT_OPSIZE) ||
93 inheritsFrom(child, IC_64BIT_ADSIZE) ||
94 inheritsFrom(child, IC_64BIT_XD) ||
95 inheritsFrom(child, IC_64BIT_XS));
97 return (inheritsFrom(child, IC_64BIT_OPSIZE) ||
98 inheritsFrom(child, IC_OPSIZE_ADSIZE));
100 return inheritsFrom(child, IC_OPSIZE_ADSIZE);
101 case IC_OPSIZE_ADSIZE:
102 case IC_64BIT_ADSIZE:
105 return inheritsFrom(child, IC_64BIT_XD);
107 return inheritsFrom(child, IC_64BIT_XS);
109 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
111 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
113 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
114 inheritsFrom(child, IC_64BIT_REXW_XD) ||
115 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
116 case IC_64BIT_OPSIZE:
117 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
119 return(inheritsFrom(child, IC_64BIT_REXW_XD));
121 return(inheritsFrom(child, IC_64BIT_REXW_XS));
122 case IC_64BIT_XD_OPSIZE:
123 case IC_64BIT_XS_OPSIZE:
125 case IC_64BIT_REXW_XD:
126 case IC_64BIT_REXW_XS:
127 case IC_64BIT_REXW_OPSIZE:
130 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
131 inheritsFrom(child, IC_VEX_W) ||
132 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
134 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
135 inheritsFrom(child, IC_VEX_W_XS) ||
136 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
138 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
139 inheritsFrom(child, IC_VEX_W_XD) ||
140 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
142 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
143 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
144 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
146 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
148 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
150 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
151 case IC_VEX_W_OPSIZE:
152 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
154 return inheritsFrom(child, IC_VEX_L_W);
156 return inheritsFrom(child, IC_VEX_L_W_XS);
158 return inheritsFrom(child, IC_VEX_L_W_XD);
159 case IC_VEX_L_OPSIZE:
160 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
164 case IC_VEX_L_W_OPSIZE:
167 return inheritsFrom(child, IC_EVEX_W) ||
168 inheritsFrom(child, IC_EVEX_L_W);
170 return inheritsFrom(child, IC_EVEX_W_XS) ||
171 inheritsFrom(child, IC_EVEX_L_W_XS);
173 return inheritsFrom(child, IC_EVEX_W_XD) ||
174 inheritsFrom(child, IC_EVEX_L_W_XD);
176 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
177 inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
181 case IC_EVEX_W_OPSIZE:
186 case IC_EVEX_L_OPSIZE:
191 case IC_EVEX_L_W_OPSIZE:
196 case IC_EVEX_L2_OPSIZE:
199 case IC_EVEX_L2_W_XS:
200 case IC_EVEX_L2_W_XD:
201 case IC_EVEX_L2_W_OPSIZE:
204 return inheritsFrom(child, IC_EVEX_W_K) ||
205 inheritsFrom(child, IC_EVEX_L_W_K);
207 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
208 inheritsFrom(child, IC_EVEX_L_W_XS_K);
210 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
211 inheritsFrom(child, IC_EVEX_L_W_XD_K);
212 case IC_EVEX_OPSIZE_K:
213 return inheritsFrom(child, IC_EVEX_W_OPSIZE_K) ||
214 inheritsFrom(child, IC_EVEX_W_OPSIZE_K);
218 case IC_EVEX_W_OPSIZE_K:
223 case IC_EVEX_L_OPSIZE_K:
226 case IC_EVEX_W_XS_KZ:
227 case IC_EVEX_W_XD_KZ:
228 case IC_EVEX_W_OPSIZE_KZ:
231 case IC_EVEX_L_XS_KZ:
232 case IC_EVEX_L_XD_KZ:
233 case IC_EVEX_L_OPSIZE_KZ:
236 case IC_EVEX_L_W_XS_K:
237 case IC_EVEX_L_W_XD_K:
238 case IC_EVEX_L_W_OPSIZE_K:
240 case IC_EVEX_L_W_XS_KZ:
241 case IC_EVEX_L_W_XD_KZ:
242 case IC_EVEX_L_W_OPSIZE_KZ:
246 case IC_EVEX_L2_XS_K:
247 case IC_EVEX_L2_XS_B:
248 case IC_EVEX_L2_XD_B:
249 case IC_EVEX_L2_XD_K:
250 case IC_EVEX_L2_OPSIZE_K:
251 case IC_EVEX_L2_OPSIZE_B:
252 case IC_EVEX_L2_OPSIZE_K_B:
254 case IC_EVEX_L2_XS_KZ:
255 case IC_EVEX_L2_XD_KZ:
256 case IC_EVEX_L2_OPSIZE_KZ:
257 case IC_EVEX_L2_OPSIZE_KZ_B:
261 case IC_EVEX_L2_W_XS_K:
262 case IC_EVEX_L2_W_XD_K:
263 case IC_EVEX_L2_W_XD_B:
264 case IC_EVEX_L2_W_OPSIZE_K:
265 case IC_EVEX_L2_W_OPSIZE_B:
266 case IC_EVEX_L2_W_OPSIZE_K_B:
267 case IC_EVEX_L2_W_KZ:
268 case IC_EVEX_L2_W_XS_KZ:
269 case IC_EVEX_L2_W_XD_KZ:
270 case IC_EVEX_L2_W_OPSIZE_KZ:
271 case IC_EVEX_L2_W_OPSIZE_KZ_B:
274 errs() << "Unknown instruction class: " <<
275 stringForContext((InstructionContext)parent) << "\n";
276 llvm_unreachable("Unknown instruction class");
280 /// outranks - Indicates whether, if an instruction has two different applicable
281 /// classes, which class should be preferred when performing decode. This
282 /// imposes a total ordering (ties are resolved toward "lower")
284 /// @param upper - The class that may be preferable
285 /// @param lower - The class that may be less preferable
286 /// @return - True if upper is to be preferred, false otherwise.
287 static inline bool outranks(InstructionContext upper,
288 InstructionContext lower) {
289 assert(upper < IC_max);
290 assert(lower < IC_max);
292 #define ENUM_ENTRY(n, r, d) r,
293 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
294 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \
295 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
296 static int ranks[IC_max] = {
300 #undef ENUM_ENTRY_K_B
302 return (ranks[upper] > ranks[lower]);
305 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
306 /// be compacted by eliminating redundant information.
308 /// @param decision - The decision to be compacted.
309 /// @return - The compactest available representation for the decision.
310 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
311 bool satisfiesOneEntry = true;
312 bool satisfiesSplitRM = true;
313 bool satisfiesSplitReg = true;
314 bool satisfiesSplitMisc = true;
316 for (unsigned index = 0; index < 256; ++index) {
317 if (decision.instructionIDs[index] != decision.instructionIDs[0])
318 satisfiesOneEntry = false;
320 if (((index & 0xc0) == 0xc0) &&
321 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
322 satisfiesSplitRM = false;
324 if (((index & 0xc0) != 0xc0) &&
325 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
326 satisfiesSplitRM = false;
328 if (((index & 0xc0) == 0xc0) &&
329 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
330 satisfiesSplitReg = false;
332 if (((index & 0xc0) != 0xc0) &&
333 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
334 satisfiesSplitMisc = false;
337 if (satisfiesOneEntry)
338 return MODRM_ONEENTRY;
340 if (satisfiesSplitRM)
341 return MODRM_SPLITRM;
343 if (satisfiesSplitReg && satisfiesSplitMisc)
344 return MODRM_SPLITREG;
346 if (satisfiesSplitMisc)
347 return MODRM_SPLITMISC;
352 /// stringForDecisionType - Returns a statically-allocated string corresponding
353 /// to a particular decision type.
355 /// @param dt - The decision type.
356 /// @return - A pointer to the statically-allocated string (e.g.,
357 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
358 static const char* stringForDecisionType(ModRMDecisionType dt) {
359 #define ENUM_ENTRY(n) case n: return #n;
362 llvm_unreachable("Unknown decision type");
368 DisassemblerTables::DisassemblerTables() {
371 for (i = 0; i < array_lengthof(Tables); i++) {
372 Tables[i] = new ContextDecision;
373 memset(Tables[i], 0, sizeof(ContextDecision));
376 HasConflicts = false;
379 DisassemblerTables::~DisassemblerTables() {
382 for (i = 0; i < array_lengthof(Tables); i++)
386 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
387 unsigned &i1, unsigned &i2,
388 unsigned &ModRMTableNum,
389 ModRMDecision &decision) const {
390 static uint32_t sTableNumber = 0;
391 static uint32_t sEntryNumber = 1;
392 ModRMDecisionType dt = getDecisionType(decision);
394 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
396 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
399 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
400 o2.indent(i2) << 0 << " /* EmptyTable */\n";
403 o2.indent(i2) << "}";
407 std::vector<unsigned> ModRMDecision;
411 llvm_unreachable("Unknown decision type");
413 ModRMDecision.push_back(decision.instructionIDs[0]);
416 ModRMDecision.push_back(decision.instructionIDs[0x00]);
417 ModRMDecision.push_back(decision.instructionIDs[0xc0]);
420 for (unsigned index = 0; index < 64; index += 8)
421 ModRMDecision.push_back(decision.instructionIDs[index]);
422 for (unsigned index = 0xc0; index < 256; index += 8)
423 ModRMDecision.push_back(decision.instructionIDs[index]);
425 case MODRM_SPLITMISC:
426 for (unsigned index = 0; index < 64; index += 8)
427 ModRMDecision.push_back(decision.instructionIDs[index]);
428 for (unsigned index = 0xc0; index < 256; ++index)
429 ModRMDecision.push_back(decision.instructionIDs[index]);
432 for (unsigned index = 0; index < 256; ++index)
433 ModRMDecision.push_back(decision.instructionIDs[index]);
437 unsigned &EntryNumber = ModRMTable[ModRMDecision];
438 if (EntryNumber == 0) {
439 EntryNumber = ModRMTableNum;
441 ModRMTableNum += ModRMDecision.size();
442 o1 << "/* Table" << EntryNumber << " */\n";
444 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
445 E = ModRMDecision.end(); I != E; ++I) {
446 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* "
447 << InstructionSpecifiers[*I].name << " */\n";
452 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
455 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
456 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n";
459 o2.indent(i2) << "}";
463 llvm_unreachable("Unknown decision type");
473 case MODRM_SPLITMISC:
474 sEntryNumber += 8 + 64;
481 // We assume that the index can fit into uint16_t.
482 assert(sEntryNumber < 65536U &&
483 "Index into ModRMDecision is too large for uint16_t!");
488 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
489 unsigned &i1, unsigned &i2,
490 unsigned &ModRMTableNum,
491 OpcodeDecision &decision) const {
492 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
494 o2.indent(i2) << "{" << "\n";
497 for (unsigned index = 0; index < 256; ++index) {
500 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
502 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
503 decision.modRMDecisions[index]);
512 o2.indent(i2) << "}" << "\n";
514 o2.indent(i2) << "}" << "\n";
517 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
518 unsigned &i1, unsigned &i2,
519 unsigned &ModRMTableNum,
520 ContextDecision &decision,
521 const char* name) const {
522 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
524 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
527 for (unsigned index = 0; index < IC_max; ++index) {
528 o2.indent(i2) << "/* ";
529 o2 << stringForContext((InstructionContext)index);
533 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
534 decision.opcodeDecisions[index]);
536 if (index + 1 < IC_max)
541 o2.indent(i2) << "}" << "\n";
543 o2.indent(i2) << "};" << "\n";
546 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
548 unsigned NumInstructions = InstructionSpecifiers.size();
550 o << "static const struct OperandSpecifier x86OperandSets[]["
551 << X86_MAX_OPERANDS << "] = {\n";
553 typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
554 std::map<OperandListTy, unsigned> OperandSets;
556 unsigned OperandSetNum = 0;
557 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
558 OperandListTy OperandList;
560 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
562 const char *Encoding =
563 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
564 .operands[OperandIndex].encoding);
566 stringForOperandType((OperandType)InstructionSpecifiers[Index]
567 .operands[OperandIndex].type);
568 OperandList.push_back(std::make_pair(Encoding, Type));
570 unsigned &N = OperandSets[OperandList];
571 if (N != 0) continue;
575 o << " { /* " << (OperandSetNum - 1) << " */\n";
576 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
577 o << " { " << OperandList[i].first << ", "
578 << OperandList[i].second << " },\n";
584 o.indent(i * 2) << "static const struct InstructionSpecifier ";
585 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
589 for (unsigned index = 0; index < NumInstructions; ++index) {
590 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
593 OperandListTy OperandList;
594 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
596 const char *Encoding =
597 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
598 .operands[OperandIndex].encoding);
600 stringForOperandType((OperandType)InstructionSpecifiers[index]
601 .operands[OperandIndex].type);
602 OperandList.push_back(std::make_pair(Encoding, Type));
604 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
606 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
610 o.indent(i * 2) << "}";
612 if (index + 1 < NumInstructions)
619 o.indent(i * 2) << "};" << "\n";
622 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
623 const unsigned int tableSize = 16384;
624 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
625 "[" << tableSize << "] = {\n";
628 for (unsigned index = 0; index < tableSize; ++index) {
631 if (index & ATTR_EVEX) {
633 if (index & ATTR_EVEXL2)
635 else if (index & ATTR_EVEXL)
637 if (index & ATTR_REXW)
639 if (index & ATTR_OPSIZE)
641 else if (index & ATTR_XD)
643 else if (index & ATTR_XS)
645 if (index & ATTR_EVEXKZ)
647 else if (index & ATTR_EVEXK)
649 if (index & ATTR_EVEXB)
652 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
653 o << "IC_VEX_L_W_OPSIZE";
654 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
655 o << "IC_VEX_L_W_XD";
656 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
657 o << "IC_VEX_L_W_XS";
658 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
660 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
661 o << "IC_VEX_L_OPSIZE";
662 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
664 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
666 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
667 o << "IC_VEX_W_OPSIZE";
668 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
670 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
672 else if (index & ATTR_VEXL)
674 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
676 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
677 o << "IC_VEX_OPSIZE";
678 else if ((index & ATTR_VEX) && (index & ATTR_XD))
680 else if ((index & ATTR_VEX) && (index & ATTR_XS))
682 else if (index & ATTR_VEX)
684 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
685 o << "IC_64BIT_REXW_XS";
686 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
687 o << "IC_64BIT_REXW_XD";
688 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
689 (index & ATTR_OPSIZE))
690 o << "IC_64BIT_REXW_OPSIZE";
691 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
692 o << "IC_64BIT_XD_OPSIZE";
693 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
694 o << "IC_64BIT_XS_OPSIZE";
695 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
697 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
699 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
700 o << "IC_64BIT_OPSIZE";
701 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
702 o << "IC_64BIT_ADSIZE";
703 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
704 o << "IC_64BIT_REXW";
705 else if ((index & ATTR_64BIT))
707 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
709 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
711 else if (index & ATTR_XS)
713 else if (index & ATTR_XD)
715 else if (index & ATTR_OPSIZE)
717 else if (index & ATTR_ADSIZE)
722 if (index < tableSize - 1)
727 o << " /* " << index << " */";
733 o.indent(i * 2) << "};" << "\n";
736 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
737 unsigned &i1, unsigned &i2,
738 unsigned &ModRMTableNum) const {
739 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
740 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
741 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
742 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
743 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], THREEBYTEA6_STR);
744 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], THREEBYTEA7_STR);
745 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOP8_MAP_STR);
746 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[7], XOP9_MAP_STR);
747 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[8], XOPA_MAP_STR);
750 void DisassemblerTables::emit(raw_ostream &o) const {
757 raw_string_ostream o1(s1);
758 raw_string_ostream o2(s2);
760 emitInstructionInfo(o, i2);
763 emitContextTable(o, i2);
766 unsigned ModRMTableNum = 0;
768 o << "static const InstrUID modRMTable[] = {\n";
770 std::vector<unsigned> EmptyTable(1, 0);
771 ModRMTable[EmptyTable] = ModRMTableNum;
772 ModRMTableNum += EmptyTable.size();
773 o1 << "/* EmptyTable */\n";
774 o1.indent(i1 * 2) << "0x0,\n";
776 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
787 void DisassemblerTables::setTableFields(ModRMDecision &decision,
788 const ModRMFilter &filter,
791 for (unsigned index = 0; index < 256; ++index) {
792 if (filter.accepts(index)) {
793 if (decision.instructionIDs[index] == uid)
796 if (decision.instructionIDs[index] != 0) {
797 InstructionSpecifier &newInfo =
798 InstructionSpecifiers[uid];
799 InstructionSpecifier &previousInfo =
800 InstructionSpecifiers[decision.instructionIDs[index]];
803 continue; // filtered instructions get lowest priority
805 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
806 newInfo.name == "XCHG32ar" ||
807 newInfo.name == "XCHG32ar64" ||
808 newInfo.name == "XCHG64ar"))
809 continue; // special case for XCHG*ar and NOOP
811 if (outranks(previousInfo.insnContext, newInfo.insnContext))
814 if (previousInfo.insnContext == newInfo.insnContext &&
815 !previousInfo.filtered) {
816 errs() << "Error: Primary decode conflict: ";
817 errs() << newInfo.name << " would overwrite " << previousInfo.name;
819 errs() << "ModRM " << index << "\n";
820 errs() << "Opcode " << (uint16_t)opcode << "\n";
821 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
826 decision.instructionIDs[index] = uid;
831 void DisassemblerTables::setTableFields(OpcodeType type,
832 InstructionContext insnContext,
834 const ModRMFilter &filter,
838 ContextDecision &decision = *Tables[type];
840 for (unsigned index = 0; index < IC_max; ++index) {
841 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
844 if (inheritsFrom((InstructionContext)index,
845 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
846 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],