1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86DisassemblerTables.h"
20 #include "llvm/TableGen/TableGenBackend.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/Format.h"
26 using namespace X86Disassembler;
28 /// inheritsFrom - Indicates whether all instructions in one class also belong
31 /// @param child - The class that may be the subset
32 /// @param parent - The class that may be the superset
33 /// @return - True if child is a subset of parent, false otherwise.
34 static inline bool inheritsFrom(InstructionContext child,
35 InstructionContext parent,
36 bool VEX_LIG = false) {
42 return(inheritsFrom(child, IC_64BIT) ||
43 inheritsFrom(child, IC_OPSIZE) ||
44 inheritsFrom(child, IC_ADSIZE) ||
45 inheritsFrom(child, IC_XD) ||
46 inheritsFrom(child, IC_XS));
48 return(inheritsFrom(child, IC_64BIT_REXW) ||
49 inheritsFrom(child, IC_64BIT_OPSIZE) ||
50 inheritsFrom(child, IC_64BIT_ADSIZE) ||
51 inheritsFrom(child, IC_64BIT_XD) ||
52 inheritsFrom(child, IC_64BIT_XS));
54 return inheritsFrom(child, IC_64BIT_OPSIZE);
59 return inheritsFrom(child, IC_64BIT_XD);
61 return inheritsFrom(child, IC_64BIT_XS);
63 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
65 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
67 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
68 inheritsFrom(child, IC_64BIT_REXW_XD) ||
69 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
71 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
73 return(inheritsFrom(child, IC_64BIT_REXW_XD));
75 return(inheritsFrom(child, IC_64BIT_REXW_XS));
76 case IC_64BIT_XD_OPSIZE:
77 case IC_64BIT_XS_OPSIZE:
79 case IC_64BIT_REXW_XD:
80 case IC_64BIT_REXW_XS:
81 case IC_64BIT_REXW_OPSIZE:
84 return inheritsFrom(child, IC_VEX_W) ||
85 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
87 return inheritsFrom(child, IC_VEX_W_XS) ||
88 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
90 return inheritsFrom(child, IC_VEX_W_XD) ||
91 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
93 return inheritsFrom(child, IC_VEX_W_OPSIZE) ||
94 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
104 case IC_VEX_L_OPSIZE:
105 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
106 case IC_VEX_L_W_OPSIZE:
109 llvm_unreachable("Unknown instruction class");
113 /// outranks - Indicates whether, if an instruction has two different applicable
114 /// classes, which class should be preferred when performing decode. This
115 /// imposes a total ordering (ties are resolved toward "lower")
117 /// @param upper - The class that may be preferable
118 /// @param lower - The class that may be less preferable
119 /// @return - True if upper is to be preferred, false otherwise.
120 static inline bool outranks(InstructionContext upper,
121 InstructionContext lower) {
122 assert(upper < IC_max);
123 assert(lower < IC_max);
125 #define ENUM_ENTRY(n, r, d) r,
126 static int ranks[IC_max] = {
131 return (ranks[upper] > ranks[lower]);
134 /// stringForContext - Returns a string containing the name of a particular
135 /// InstructionContext, usually for diagnostic purposes.
137 /// @param insnContext - The instruction class to transform to a string.
138 /// @return - A statically-allocated string constant that contains the
139 /// name of the instruction class.
140 static inline const char* stringForContext(InstructionContext insnContext) {
141 switch (insnContext) {
143 llvm_unreachable("Unhandled instruction class");
144 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
150 /// stringForOperandType - Like stringForContext, but for OperandTypes.
151 static inline const char* stringForOperandType(OperandType type) {
154 llvm_unreachable("Unhandled type");
155 #define ENUM_ENTRY(i, d) case i: return #i;
161 /// stringForOperandEncoding - like stringForContext, but for
162 /// OperandEncodings.
163 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
166 llvm_unreachable("Unhandled encoding");
167 #define ENUM_ENTRY(i, d) case i: return #i;
173 void DisassemblerTables::emitOneID(raw_ostream &o,
176 bool addComma) const {
178 o.indent(i * 2) << format("0x%hx", id);
180 o.indent(i * 2) << 0;
188 o << InstructionSpecifiers[id].name;
194 /// emitEmptyTable - Emits the modRMEmptyTable, which is used as a ID table by
195 /// all ModR/M decisions for instructions that are invalid for all possible
196 /// ModR/M byte values.
198 /// @param o - The output stream on which to emit the table.
199 /// @param i - The indentation level for that output stream.
200 static void emitEmptyTable(raw_ostream &o, uint32_t &i)
202 o.indent(i * 2) << "0x0, /* EmptyTable */\n";
205 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
206 /// be compacted by eliminating redundant information.
208 /// @param decision - The decision to be compacted.
209 /// @return - The compactest available representation for the decision.
210 static ModRMDecisionType getDecisionType(ModRMDecision &decision)
212 bool satisfiesOneEntry = true;
213 bool satisfiesSplitRM = true;
214 bool satisfiesSplitReg = true;
218 for (index = 0; index < 256; ++index) {
219 if (decision.instructionIDs[index] != decision.instructionIDs[0])
220 satisfiesOneEntry = false;
222 if (((index & 0xc0) == 0xc0) &&
223 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
224 satisfiesSplitRM = false;
226 if (((index & 0xc0) != 0xc0) &&
227 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
228 satisfiesSplitRM = false;
230 if (((index & 0xc0) == 0xc0) &&
231 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
232 satisfiesSplitReg = false;
234 if (((index & 0xc0) != 0xc0) &&
235 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
236 satisfiesSplitReg = false;
239 if (satisfiesOneEntry)
240 return MODRM_ONEENTRY;
242 if (satisfiesSplitRM)
243 return MODRM_SPLITRM;
245 if (satisfiesSplitReg)
246 return MODRM_SPLITREG;
251 /// stringForDecisionType - Returns a statically-allocated string corresponding
252 /// to a particular decision type.
254 /// @param dt - The decision type.
255 /// @return - A pointer to the statically-allocated string (e.g.,
256 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
257 static const char* stringForDecisionType(ModRMDecisionType dt)
259 #define ENUM_ENTRY(n) case n: return #n;
262 llvm_unreachable("Unknown decision type");
268 /// stringForModifierType - Returns a statically-allocated string corresponding
269 /// to an opcode modifier type.
271 /// @param mt - The modifier type.
272 /// @return - A pointer to the statically-allocated string (e.g.,
273 /// "MODIFIER_NONE" for MODIFIER_NONE).
274 static const char* stringForModifierType(ModifierType mt)
276 #define ENUM_ENTRY(n) case n: return #n;
279 llvm_unreachable("Unknown modifier type");
285 DisassemblerTables::DisassemblerTables() {
288 for (i = 0; i < array_lengthof(Tables); i++) {
289 Tables[i] = new ContextDecision;
290 memset(Tables[i], 0, sizeof(ContextDecision));
293 HasConflicts = false;
296 DisassemblerTables::~DisassemblerTables() {
299 for (i = 0; i < array_lengthof(Tables); i++)
303 void DisassemblerTables::emitModRMDecision(raw_ostream &o1,
307 ModRMDecision &decision)
309 static uint64_t sTableNumber = 0;
310 static uint64_t sEntryNumber = 1;
311 ModRMDecisionType dt = getDecisionType(decision);
314 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
316 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
319 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
320 o2.indent(i2) << 0 << " /* EmptyTable */\n";
323 o2.indent(i2) << "}";
327 o1 << "/* Table" << sTableNumber << " */\n";
332 llvm_unreachable("Unknown decision type");
334 emitOneID(o1, i1, decision.instructionIDs[0], true);
337 emitOneID(o1, i1, decision.instructionIDs[0x00], true); // mod = 0b00
338 emitOneID(o1, i1, decision.instructionIDs[0xc0], true); // mod = 0b11
341 for (index = 0; index < 64; index += 8)
342 emitOneID(o1, i1, decision.instructionIDs[index], true);
343 for (index = 0xc0; index < 256; index += 8)
344 emitOneID(o1, i1, decision.instructionIDs[index], true);
347 for (index = 0; index < 256; ++index)
348 emitOneID(o1, i1, decision.instructionIDs[index], true);
354 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
357 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
358 o2.indent(i2) << sEntryNumber << " /* Table" << sTableNumber << " */\n";
361 o2.indent(i2) << "}";
365 llvm_unreachable("Unknown decision type");
383 void DisassemblerTables::emitOpcodeDecision(
388 OpcodeDecision &decision) const {
391 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
393 o2.indent(i2) << "{" << "\n";
396 for (index = 0; index < 256; ++index) {
399 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
401 emitModRMDecision(o1, o2, i1, i2, decision.modRMDecisions[index]);
410 o2.indent(i2) << "}" << "\n";
412 o2.indent(i2) << "}" << "\n";
415 void DisassemblerTables::emitContextDecision(
420 ContextDecision &decision,
421 const char* name) const {
422 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
424 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
429 for (index = 0; index < IC_max; ++index) {
430 o2.indent(i2) << "/* ";
431 o2 << stringForContext((InstructionContext)index);
435 emitOpcodeDecision(o1, o2, i1, i2, decision.opcodeDecisions[index]);
437 if (index + 1 < IC_max)
442 o2.indent(i2) << "}" << "\n";
444 o2.indent(i2) << "};" << "\n";
447 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, uint32_t &i)
449 o.indent(i * 2) << "static const struct InstructionSpecifier ";
450 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
454 uint16_t numInstructions = InstructionSpecifiers.size();
455 uint16_t index, operandIndex;
457 for (index = 0; index < numInstructions; ++index) {
458 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
462 stringForModifierType(InstructionSpecifiers[index].modifierType);
465 o.indent(i * 2) << "0x";
466 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
469 o.indent(i * 2) << "{" << "\n";
472 for (operandIndex = 0; operandIndex < X86_MAX_OPERANDS; ++operandIndex) {
473 o.indent(i * 2) << "{ ";
474 o << stringForOperandEncoding(InstructionSpecifiers[index]
475 .operands[operandIndex]
478 o << stringForOperandType(InstructionSpecifiers[index]
479 .operands[operandIndex]
483 if (operandIndex < X86_MAX_OPERANDS - 1)
490 o.indent(i * 2) << "}," << "\n";
492 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
496 o.indent(i * 2) << "}";
498 if (index + 1 < numInstructions)
505 o.indent(i * 2) << "};" << "\n";
508 void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const {
511 o.indent(i * 2) << "static const InstructionContext " CONTEXTS_STR
515 for (index = 0; index < 256; ++index) {
518 if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
519 o << "IC_VEX_L_W_OPSIZE";
520 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
521 o << "IC_VEX_L_OPSIZE";
522 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
524 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
526 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
527 o << "IC_VEX_W_OPSIZE";
528 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
530 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
532 else if (index & ATTR_VEXL)
534 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
536 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
537 o << "IC_VEX_OPSIZE";
538 else if ((index & ATTR_VEX) && (index & ATTR_XD))
540 else if ((index & ATTR_VEX) && (index & ATTR_XS))
542 else if (index & ATTR_VEX)
544 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
545 o << "IC_64BIT_REXW_XS";
546 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
547 o << "IC_64BIT_REXW_XD";
548 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
549 (index & ATTR_OPSIZE))
550 o << "IC_64BIT_REXW_OPSIZE";
551 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
552 o << "IC_64BIT_XD_OPSIZE";
553 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
554 o << "IC_64BIT_XS_OPSIZE";
555 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
557 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
559 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
560 o << "IC_64BIT_OPSIZE";
561 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
562 o << "IC_64BIT_ADSIZE";
563 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
564 o << "IC_64BIT_REXW";
565 else if ((index & ATTR_64BIT))
567 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
569 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
571 else if (index & ATTR_XS)
573 else if (index & ATTR_XD)
575 else if (index & ATTR_OPSIZE)
577 else if (index & ATTR_ADSIZE)
587 o << " /* " << index << " */";
593 o.indent(i * 2) << "};" << "\n";
596 void DisassemblerTables::emitContextDecisions(raw_ostream &o1,
601 emitContextDecision(o1, o2, i1, i2, *Tables[0], ONEBYTE_STR);
602 emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR);
603 emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR);
604 emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR);
605 emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR);
606 emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR);
609 void DisassemblerTables::emit(raw_ostream &o) const {
616 raw_string_ostream o1(s1);
617 raw_string_ostream o2(s2);
619 emitInstructionInfo(o, i2);
622 emitContextTable(o, i2);
625 o << "static const InstrUID modRMTable[] = {\n";
627 emitEmptyTable(o1, i1);
629 emitContextDecisions(o1, o2, i1, i2);
640 void DisassemblerTables::setTableFields(ModRMDecision &decision,
641 const ModRMFilter &filter,
646 for (index = 0; index < 256; ++index) {
647 if (filter.accepts(index)) {
648 if (decision.instructionIDs[index] == uid)
651 if (decision.instructionIDs[index] != 0) {
652 InstructionSpecifier &newInfo =
653 InstructionSpecifiers[uid];
654 InstructionSpecifier &previousInfo =
655 InstructionSpecifiers[decision.instructionIDs[index]];
658 continue; // filtered instructions get lowest priority
660 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
661 newInfo.name == "XCHG32ar" ||
662 newInfo.name == "XCHG32ar64" ||
663 newInfo.name == "XCHG64ar"))
664 continue; // special case for XCHG*ar and NOOP
666 if (outranks(previousInfo.insnContext, newInfo.insnContext))
669 if (previousInfo.insnContext == newInfo.insnContext &&
670 !previousInfo.filtered) {
671 errs() << "Error: Primary decode conflict: ";
672 errs() << newInfo.name << " would overwrite " << previousInfo.name;
674 errs() << "ModRM " << index << "\n";
675 errs() << "Opcode " << (uint16_t)opcode << "\n";
676 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
681 decision.instructionIDs[index] = uid;
686 void DisassemblerTables::setTableFields(OpcodeType type,
687 InstructionContext insnContext,
689 const ModRMFilter &filter,
695 ContextDecision &decision = *Tables[type];
697 for (index = 0; index < IC_max; ++index) {
698 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
701 if (inheritsFrom((InstructionContext)index,
702 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
703 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],