1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86DisassemblerTables.h"
20 #include "llvm/TableGen/TableGenBackend.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/Format.h"
26 using namespace X86Disassembler;
28 /// inheritsFrom - Indicates whether all instructions in one class also belong
31 /// @param child - The class that may be the subset
32 /// @param parent - The class that may be the superset
33 /// @return - True if child is a subset of parent, false otherwise.
34 static inline bool inheritsFrom(InstructionContext child,
35 InstructionContext parent,
36 bool VEX_LIG = false) {
42 return(inheritsFrom(child, IC_64BIT) ||
43 inheritsFrom(child, IC_OPSIZE) ||
44 inheritsFrom(child, IC_ADSIZE) ||
45 inheritsFrom(child, IC_XD) ||
46 inheritsFrom(child, IC_XS));
48 return(inheritsFrom(child, IC_64BIT_REXW) ||
49 inheritsFrom(child, IC_64BIT_OPSIZE) ||
50 inheritsFrom(child, IC_64BIT_ADSIZE) ||
51 inheritsFrom(child, IC_64BIT_XD) ||
52 inheritsFrom(child, IC_64BIT_XS));
54 return inheritsFrom(child, IC_64BIT_OPSIZE);
59 return inheritsFrom(child, IC_64BIT_XD);
61 return inheritsFrom(child, IC_64BIT_XS);
63 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
65 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
67 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
68 inheritsFrom(child, IC_64BIT_REXW_XD) ||
69 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
71 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
73 return(inheritsFrom(child, IC_64BIT_REXW_XD));
75 return(inheritsFrom(child, IC_64BIT_REXW_XS));
76 case IC_64BIT_XD_OPSIZE:
77 case IC_64BIT_XS_OPSIZE:
79 case IC_64BIT_REXW_XD:
80 case IC_64BIT_REXW_XS:
81 case IC_64BIT_REXW_OPSIZE:
84 return inheritsFrom(child, IC_VEX_W) ||
85 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
87 return inheritsFrom(child, IC_VEX_W_XS) ||
88 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
90 return inheritsFrom(child, IC_VEX_W_XD) ||
91 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
93 return inheritsFrom(child, IC_VEX_W_OPSIZE) ||
94 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
104 case IC_VEX_L_OPSIZE:
105 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
106 case IC_VEX_L_W_OPSIZE:
109 llvm_unreachable("Unknown instruction class");
113 /// outranks - Indicates whether, if an instruction has two different applicable
114 /// classes, which class should be preferred when performing decode. This
115 /// imposes a total ordering (ties are resolved toward "lower")
117 /// @param upper - The class that may be preferable
118 /// @param lower - The class that may be less preferable
119 /// @return - True if upper is to be preferred, false otherwise.
120 static inline bool outranks(InstructionContext upper,
121 InstructionContext lower) {
122 assert(upper < IC_max);
123 assert(lower < IC_max);
125 #define ENUM_ENTRY(n, r, d) r,
126 static int ranks[IC_max] = {
131 return (ranks[upper] > ranks[lower]);
134 /// stringForContext - Returns a string containing the name of a particular
135 /// InstructionContext, usually for diagnostic purposes.
137 /// @param insnContext - The instruction class to transform to a string.
138 /// @return - A statically-allocated string constant that contains the
139 /// name of the instruction class.
140 static inline const char* stringForContext(InstructionContext insnContext) {
141 switch (insnContext) {
143 llvm_unreachable("Unhandled instruction class");
144 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
150 /// stringForOperandType - Like stringForContext, but for OperandTypes.
151 static inline const char* stringForOperandType(OperandType type) {
154 llvm_unreachable("Unhandled type");
155 #define ENUM_ENTRY(i, d) case i: return #i;
161 /// stringForOperandEncoding - like stringForContext, but for
162 /// OperandEncodings.
163 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
166 llvm_unreachable("Unhandled encoding");
167 #define ENUM_ENTRY(i, d) case i: return #i;
173 void DisassemblerTables::emitOneID(raw_ostream &o, uint32_t &i, InstrUID id,
174 bool addComma) const {
176 o.indent(i * 2) << format("0x%hx", id);
178 o.indent(i * 2) << 0;
186 o << InstructionSpecifiers[id].name;
192 /// emitEmptyTable - Emits the modRMEmptyTable, which is used as a ID table by
193 /// all ModR/M decisions for instructions that are invalid for all possible
194 /// ModR/M byte values.
196 /// @param o - The output stream on which to emit the table.
197 /// @param i - The indentation level for that output stream.
198 static void emitEmptyTable(raw_ostream &o, uint32_t &i) {
199 o.indent(i * 2) << "0x0, /* EmptyTable */\n";
202 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
203 /// be compacted by eliminating redundant information.
205 /// @param decision - The decision to be compacted.
206 /// @return - The compactest available representation for the decision.
207 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
208 bool satisfiesOneEntry = true;
209 bool satisfiesSplitRM = true;
210 bool satisfiesSplitReg = true;
214 for (index = 0; index < 256; ++index) {
215 if (decision.instructionIDs[index] != decision.instructionIDs[0])
216 satisfiesOneEntry = false;
218 if (((index & 0xc0) == 0xc0) &&
219 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
220 satisfiesSplitRM = false;
222 if (((index & 0xc0) != 0xc0) &&
223 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
224 satisfiesSplitRM = false;
226 if (((index & 0xc0) == 0xc0) &&
227 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
228 satisfiesSplitReg = false;
230 if (((index & 0xc0) != 0xc0) &&
231 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
232 satisfiesSplitReg = false;
235 if (satisfiesOneEntry)
236 return MODRM_ONEENTRY;
238 if (satisfiesSplitRM)
239 return MODRM_SPLITRM;
241 if (satisfiesSplitReg)
242 return MODRM_SPLITREG;
247 /// stringForDecisionType - Returns a statically-allocated string corresponding
248 /// to a particular decision type.
250 /// @param dt - The decision type.
251 /// @return - A pointer to the statically-allocated string (e.g.,
252 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
253 static const char* stringForDecisionType(ModRMDecisionType dt) {
254 #define ENUM_ENTRY(n) case n: return #n;
257 llvm_unreachable("Unknown decision type");
263 /// stringForModifierType - Returns a statically-allocated string corresponding
264 /// to an opcode modifier type.
266 /// @param mt - The modifier type.
267 /// @return - A pointer to the statically-allocated string (e.g.,
268 /// "MODIFIER_NONE" for MODIFIER_NONE).
269 static const char* stringForModifierType(ModifierType mt) {
270 #define ENUM_ENTRY(n) case n: return #n;
273 llvm_unreachable("Unknown modifier type");
279 DisassemblerTables::DisassemblerTables() {
282 for (i = 0; i < array_lengthof(Tables); i++) {
283 Tables[i] = new ContextDecision;
284 memset(Tables[i], 0, sizeof(ContextDecision));
287 HasConflicts = false;
290 DisassemblerTables::~DisassemblerTables() {
293 for (i = 0; i < array_lengthof(Tables); i++)
297 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
298 uint32_t &i1, uint32_t &i2,
299 ModRMDecision &decision) const {
300 static uint64_t sTableNumber = 0;
301 static uint64_t sEntryNumber = 1;
302 ModRMDecisionType dt = getDecisionType(decision);
305 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
307 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
310 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
311 o2.indent(i2) << 0 << " /* EmptyTable */\n";
314 o2.indent(i2) << "}";
318 o1 << "/* Table" << sTableNumber << " */\n";
323 llvm_unreachable("Unknown decision type");
325 emitOneID(o1, i1, decision.instructionIDs[0], true);
328 emitOneID(o1, i1, decision.instructionIDs[0x00], true); // mod = 0b00
329 emitOneID(o1, i1, decision.instructionIDs[0xc0], true); // mod = 0b11
332 for (index = 0; index < 64; index += 8)
333 emitOneID(o1, i1, decision.instructionIDs[index], true);
334 for (index = 0xc0; index < 256; index += 8)
335 emitOneID(o1, i1, decision.instructionIDs[index], true);
338 for (index = 0; index < 256; ++index)
339 emitOneID(o1, i1, decision.instructionIDs[index], true);
345 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
348 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
349 o2.indent(i2) << sEntryNumber << " /* Table" << sTableNumber << " */\n";
352 o2.indent(i2) << "}";
356 llvm_unreachable("Unknown decision type");
374 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
375 uint32_t &i1, uint32_t &i2,
376 OpcodeDecision &decision) const {
379 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
381 o2.indent(i2) << "{" << "\n";
384 for (index = 0; index < 256; ++index) {
387 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
389 emitModRMDecision(o1, o2, i1, i2, decision.modRMDecisions[index]);
398 o2.indent(i2) << "}" << "\n";
400 o2.indent(i2) << "}" << "\n";
403 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
404 uint32_t &i1, uint32_t &i2,
405 ContextDecision &decision,
406 const char* name) const {
407 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
409 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
414 for (index = 0; index < IC_max; ++index) {
415 o2.indent(i2) << "/* ";
416 o2 << stringForContext((InstructionContext)index);
420 emitOpcodeDecision(o1, o2, i1, i2, decision.opcodeDecisions[index]);
422 if (index + 1 < IC_max)
427 o2.indent(i2) << "}" << "\n";
429 o2.indent(i2) << "};" << "\n";
432 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, uint32_t &i)
434 o.indent(i * 2) << "static const struct InstructionSpecifier ";
435 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
439 uint16_t numInstructions = InstructionSpecifiers.size();
440 uint16_t index, operandIndex;
442 for (index = 0; index < numInstructions; ++index) {
443 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
446 o.indent(i * 2) << stringForModifierType(
447 (ModifierType)InstructionSpecifiers[index].modifierType);
450 o.indent(i * 2) << "0x";
451 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
454 o.indent(i * 2) << "{" << "\n";
457 for (operandIndex = 0; operandIndex < X86_MAX_OPERANDS; ++operandIndex) {
458 o.indent(i * 2) << "{ ";
459 o <<stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
460 .operands[operandIndex]
463 o << stringForOperandType((OperandType)InstructionSpecifiers[index]
464 .operands[operandIndex]
468 if (operandIndex < X86_MAX_OPERANDS - 1)
475 o.indent(i * 2) << "}," << "\n";
477 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
481 o.indent(i * 2) << "}";
483 if (index + 1 < numInstructions)
490 o.indent(i * 2) << "};" << "\n";
493 void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const {
496 o.indent(i * 2) << "static const InstructionContext " CONTEXTS_STR
500 for (index = 0; index < 256; ++index) {
503 if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
504 o << "IC_VEX_L_W_OPSIZE";
505 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
506 o << "IC_VEX_L_OPSIZE";
507 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
509 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
511 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
512 o << "IC_VEX_W_OPSIZE";
513 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
515 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
517 else if (index & ATTR_VEXL)
519 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
521 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
522 o << "IC_VEX_OPSIZE";
523 else if ((index & ATTR_VEX) && (index & ATTR_XD))
525 else if ((index & ATTR_VEX) && (index & ATTR_XS))
527 else if (index & ATTR_VEX)
529 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
530 o << "IC_64BIT_REXW_XS";
531 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
532 o << "IC_64BIT_REXW_XD";
533 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
534 (index & ATTR_OPSIZE))
535 o << "IC_64BIT_REXW_OPSIZE";
536 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
537 o << "IC_64BIT_XD_OPSIZE";
538 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
539 o << "IC_64BIT_XS_OPSIZE";
540 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
542 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
544 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
545 o << "IC_64BIT_OPSIZE";
546 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
547 o << "IC_64BIT_ADSIZE";
548 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
549 o << "IC_64BIT_REXW";
550 else if ((index & ATTR_64BIT))
552 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
554 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
556 else if (index & ATTR_XS)
558 else if (index & ATTR_XD)
560 else if (index & ATTR_OPSIZE)
562 else if (index & ATTR_ADSIZE)
572 o << " /* " << index << " */";
578 o.indent(i * 2) << "};" << "\n";
581 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
582 uint32_t &i1, uint32_t &i2) const {
583 emitContextDecision(o1, o2, i1, i2, *Tables[0], ONEBYTE_STR);
584 emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR);
585 emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR);
586 emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR);
587 emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR);
588 emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR);
591 void DisassemblerTables::emit(raw_ostream &o) const {
598 raw_string_ostream o1(s1);
599 raw_string_ostream o2(s2);
601 emitInstructionInfo(o, i2);
604 emitContextTable(o, i2);
607 o << "static const InstrUID modRMTable[] = {\n";
609 emitEmptyTable(o1, i1);
611 emitContextDecisions(o1, o2, i1, i2);
622 void DisassemblerTables::setTableFields(ModRMDecision &decision,
623 const ModRMFilter &filter,
628 for (index = 0; index < 256; ++index) {
629 if (filter.accepts(index)) {
630 if (decision.instructionIDs[index] == uid)
633 if (decision.instructionIDs[index] != 0) {
634 InstructionSpecifier &newInfo =
635 InstructionSpecifiers[uid];
636 InstructionSpecifier &previousInfo =
637 InstructionSpecifiers[decision.instructionIDs[index]];
640 continue; // filtered instructions get lowest priority
642 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
643 newInfo.name == "XCHG32ar" ||
644 newInfo.name == "XCHG32ar64" ||
645 newInfo.name == "XCHG64ar"))
646 continue; // special case for XCHG*ar and NOOP
648 if (outranks(previousInfo.insnContext, newInfo.insnContext))
651 if (previousInfo.insnContext == newInfo.insnContext &&
652 !previousInfo.filtered) {
653 errs() << "Error: Primary decode conflict: ";
654 errs() << newInfo.name << " would overwrite " << previousInfo.name;
656 errs() << "ModRM " << index << "\n";
657 errs() << "Opcode " << (uint16_t)opcode << "\n";
658 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
663 decision.instructionIDs[index] = uid;
668 void DisassemblerTables::setTableFields(OpcodeType type,
669 InstructionContext insnContext,
671 const ModRMFilter &filter,
677 ContextDecision &decision = *Tables[type];
679 for (index = 0; index < IC_max; ++index) {
680 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
683 if (inheritsFrom((InstructionContext)index,
684 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
685 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],