1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86DisassemblerTables.h"
20 #include "llvm/TableGen/TableGenBackend.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/Format.h"
26 using namespace X86Disassembler;
28 /// inheritsFrom - Indicates whether all instructions in one class also belong
31 /// @param child - The class that may be the subset
32 /// @param parent - The class that may be the superset
33 /// @return - True if child is a subset of parent, false otherwise.
34 static inline bool inheritsFrom(InstructionContext child,
35 InstructionContext parent,
36 bool VEX_LIG = false) {
42 return(inheritsFrom(child, IC_64BIT) ||
43 inheritsFrom(child, IC_OPSIZE) ||
44 inheritsFrom(child, IC_XD) ||
45 inheritsFrom(child, IC_XS));
47 return(inheritsFrom(child, IC_64BIT_REXW) ||
48 inheritsFrom(child, IC_64BIT_OPSIZE) ||
49 inheritsFrom(child, IC_64BIT_XD) ||
50 inheritsFrom(child, IC_64BIT_XS));
52 return inheritsFrom(child, IC_64BIT_OPSIZE);
54 return inheritsFrom(child, IC_64BIT_XD);
56 return inheritsFrom(child, IC_64BIT_XS);
58 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
60 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
62 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
63 inheritsFrom(child, IC_64BIT_REXW_XD) ||
64 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
66 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
68 return(inheritsFrom(child, IC_64BIT_REXW_XD));
70 return(inheritsFrom(child, IC_64BIT_REXW_XS));
71 case IC_64BIT_XD_OPSIZE:
72 case IC_64BIT_XS_OPSIZE:
74 case IC_64BIT_REXW_XD:
75 case IC_64BIT_REXW_XS:
76 case IC_64BIT_REXW_OPSIZE:
79 return inheritsFrom(child, IC_VEX_W) ||
80 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
82 return inheritsFrom(child, IC_VEX_W_XS) ||
83 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
85 return inheritsFrom(child, IC_VEX_W_XD) ||
86 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
88 return inheritsFrom(child, IC_VEX_W_OPSIZE) ||
89 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
100 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
101 case IC_VEX_L_W_OPSIZE:
104 llvm_unreachable("Unknown instruction class");
109 /// outranks - Indicates whether, if an instruction has two different applicable
110 /// classes, which class should be preferred when performing decode. This
111 /// imposes a total ordering (ties are resolved toward "lower")
113 /// @param upper - The class that may be preferable
114 /// @param lower - The class that may be less preferable
115 /// @return - True if upper is to be preferred, false otherwise.
116 static inline bool outranks(InstructionContext upper,
117 InstructionContext lower) {
118 assert(upper < IC_max);
119 assert(lower < IC_max);
121 #define ENUM_ENTRY(n, r, d) r,
122 static int ranks[IC_max] = {
127 return (ranks[upper] > ranks[lower]);
130 /// stringForContext - Returns a string containing the name of a particular
131 /// InstructionContext, usually for diagnostic purposes.
133 /// @param insnContext - The instruction class to transform to a string.
134 /// @return - A statically-allocated string constant that contains the
135 /// name of the instruction class.
136 static inline const char* stringForContext(InstructionContext insnContext) {
137 switch (insnContext) {
139 llvm_unreachable("Unhandled instruction class");
140 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
148 /// stringForOperandType - Like stringForContext, but for OperandTypes.
149 static inline const char* stringForOperandType(OperandType type) {
152 llvm_unreachable("Unhandled type");
153 #define ENUM_ENTRY(i, d) case i: return #i;
159 /// stringForOperandEncoding - like stringForContext, but for
160 /// OperandEncodings.
161 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
164 llvm_unreachable("Unhandled encoding");
165 #define ENUM_ENTRY(i, d) case i: return #i;
171 void DisassemblerTables::emitOneID(raw_ostream &o,
174 bool addComma) const {
176 o.indent(i * 2) << format("0x%hx", id);
178 o.indent(i * 2) << 0;
186 o << InstructionSpecifiers[id].name;
192 /// emitEmptyTable - Emits the modRMEmptyTable, which is used as a ID table by
193 /// all ModR/M decisions for instructions that are invalid for all possible
194 /// ModR/M byte values.
196 /// @param o - The output stream on which to emit the table.
197 /// @param i - The indentation level for that output stream.
198 static void emitEmptyTable(raw_ostream &o, uint32_t &i)
200 o.indent(i * 2) << "static const InstrUID modRMEmptyTable[1] = { 0 };\n";
204 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
205 /// be compacted by eliminating redundant information.
207 /// @param decision - The decision to be compacted.
208 /// @return - The compactest available representation for the decision.
209 static ModRMDecisionType getDecisionType(ModRMDecision &decision)
211 bool satisfiesOneEntry = true;
212 bool satisfiesSplitRM = true;
216 for (index = 0; index < 256; ++index) {
217 if (decision.instructionIDs[index] != decision.instructionIDs[0])
218 satisfiesOneEntry = false;
220 if (((index & 0xc0) == 0xc0) &&
221 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
222 satisfiesSplitRM = false;
224 if (((index & 0xc0) != 0xc0) &&
225 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
226 satisfiesSplitRM = false;
229 if (satisfiesOneEntry)
230 return MODRM_ONEENTRY;
232 if (satisfiesSplitRM)
233 return MODRM_SPLITRM;
238 /// stringForDecisionType - Returns a statically-allocated string corresponding
239 /// to a particular decision type.
241 /// @param dt - The decision type.
242 /// @return - A pointer to the statically-allocated string (e.g.,
243 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
244 static const char* stringForDecisionType(ModRMDecisionType dt)
246 #define ENUM_ENTRY(n) case n: return #n;
249 llvm_unreachable("Unknown decision type");
255 /// stringForModifierType - Returns a statically-allocated string corresponding
256 /// to an opcode modifier type.
258 /// @param mt - The modifier type.
259 /// @return - A pointer to the statically-allocated string (e.g.,
260 /// "MODIFIER_NONE" for MODIFIER_NONE).
261 static const char* stringForModifierType(ModifierType mt)
263 #define ENUM_ENTRY(n) case n: return #n;
266 llvm_unreachable("Unknown modifier type");
272 DisassemblerTables::DisassemblerTables() {
275 for (i = 0; i < array_lengthof(Tables); i++) {
276 Tables[i] = new ContextDecision;
277 memset(Tables[i], 0, sizeof(ContextDecision));
280 HasConflicts = false;
283 DisassemblerTables::~DisassemblerTables() {
286 for (i = 0; i < array_lengthof(Tables); i++)
290 void DisassemblerTables::emitModRMDecision(raw_ostream &o1,
294 ModRMDecision &decision)
296 static uint64_t sTableNumber = 0;
297 uint64_t thisTableNumber = sTableNumber;
298 ModRMDecisionType dt = getDecisionType(decision);
301 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
303 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
306 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
307 o2.indent(i2) << "modRMEmptyTable";
310 o2.indent(i2) << "}";
314 o1.indent(i1) << "static const InstrUID modRMTable" << thisTableNumber;
318 llvm_unreachable("Unknown decision type");
330 o1 << " = {" << "\n";
335 llvm_unreachable("Unknown decision type");
337 emitOneID(o1, i1, decision.instructionIDs[0], false);
340 emitOneID(o1, i1, decision.instructionIDs[0x00], true); // mod = 0b00
341 emitOneID(o1, i1, decision.instructionIDs[0xc0], false); // mod = 0b11
344 for (index = 0; index < 256; ++index)
345 emitOneID(o1, i1, decision.instructionIDs[index], index < 255);
350 o1.indent(i1) << "};" << "\n";
353 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
356 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
357 o2.indent(i2) << "modRMTable" << sTableNumber << "\n";
360 o2.indent(i2) << "}";
365 void DisassemblerTables::emitOpcodeDecision(
370 OpcodeDecision &decision) const {
373 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
375 o2.indent(i2) << "{" << "\n";
378 for (index = 0; index < 256; ++index) {
381 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
383 emitModRMDecision(o1, o2, i1, i2, decision.modRMDecisions[index]);
392 o2.indent(i2) << "}" << "\n";
394 o2.indent(i2) << "}" << "\n";
397 void DisassemblerTables::emitContextDecision(
402 ContextDecision &decision,
403 const char* name) const {
404 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
406 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
411 for (index = 0; index < IC_max; ++index) {
412 o2.indent(i2) << "/* ";
413 o2 << stringForContext((InstructionContext)index);
417 emitOpcodeDecision(o1, o2, i1, i2, decision.opcodeDecisions[index]);
419 if (index + 1 < IC_max)
424 o2.indent(i2) << "}" << "\n";
426 o2.indent(i2) << "};" << "\n";
429 void DisassemblerTables::emitInstructionInfo(raw_ostream &o, uint32_t &i)
431 o.indent(i * 2) << "static const struct InstructionSpecifier ";
432 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
436 uint16_t numInstructions = InstructionSpecifiers.size();
437 uint16_t index, operandIndex;
439 for (index = 0; index < numInstructions; ++index) {
440 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
444 stringForModifierType(InstructionSpecifiers[index].modifierType);
447 o.indent(i * 2) << "0x";
448 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
451 o.indent(i * 2) << "{" << "\n";
454 for (operandIndex = 0; operandIndex < X86_MAX_OPERANDS; ++operandIndex) {
455 o.indent(i * 2) << "{ ";
456 o << stringForOperandEncoding(InstructionSpecifiers[index]
457 .operands[operandIndex]
460 o << stringForOperandType(InstructionSpecifiers[index]
461 .operands[operandIndex]
465 if (operandIndex < X86_MAX_OPERANDS - 1)
472 o.indent(i * 2) << "}," << "\n";
474 o.indent(i * 2) << "\"" << InstructionSpecifiers[index].name << "\"";
478 o.indent(i * 2) << "}";
480 if (index + 1 < numInstructions)
487 o.indent(i * 2) << "};" << "\n";
490 void DisassemblerTables::emitContextTable(raw_ostream &o, uint32_t &i) const {
493 o.indent(i * 2) << "static const InstructionContext " CONTEXTS_STR
497 for (index = 0; index < 256; ++index) {
500 if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
501 o << "IC_VEX_L_W_OPSIZE";
502 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
503 o << "IC_VEX_L_OPSIZE";
504 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
506 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
508 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
509 o << "IC_VEX_W_OPSIZE";
510 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
512 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
514 else if (index & ATTR_VEXL)
516 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
518 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
519 o << "IC_VEX_OPSIZE";
520 else if ((index & ATTR_VEX) && (index & ATTR_XD))
522 else if ((index & ATTR_VEX) && (index & ATTR_XS))
524 else if (index & ATTR_VEX)
526 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
527 o << "IC_64BIT_REXW_XS";
528 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
529 o << "IC_64BIT_REXW_XD";
530 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
531 (index & ATTR_OPSIZE))
532 o << "IC_64BIT_REXW_OPSIZE";
533 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
534 o << "IC_64BIT_XD_OPSIZE";
535 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
536 o << "IC_64BIT_XS_OPSIZE";
537 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
539 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
541 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
542 o << "IC_64BIT_OPSIZE";
543 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
544 o << "IC_64BIT_REXW";
545 else if ((index & ATTR_64BIT))
547 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
549 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
551 else if (index & ATTR_XS)
553 else if (index & ATTR_XD)
555 else if (index & ATTR_OPSIZE)
565 o << " /* " << index << " */";
571 o.indent(i * 2) << "};" << "\n";
574 void DisassemblerTables::emitContextDecisions(raw_ostream &o1,
579 emitContextDecision(o1, o2, i1, i2, *Tables[0], ONEBYTE_STR);
580 emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR);
581 emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR);
582 emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR);
583 emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR);
584 emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR);
587 void DisassemblerTables::emit(raw_ostream &o) const {
594 raw_string_ostream o1(s1);
595 raw_string_ostream o2(s2);
597 emitInstructionInfo(o, i2);
600 emitContextTable(o, i2);
603 emitEmptyTable(o1, i1);
604 emitContextDecisions(o1, o2, i1, i2);
613 void DisassemblerTables::setTableFields(ModRMDecision &decision,
614 const ModRMFilter &filter,
619 for (index = 0; index < 256; ++index) {
620 if (filter.accepts(index)) {
621 if (decision.instructionIDs[index] == uid)
624 if (decision.instructionIDs[index] != 0) {
625 InstructionSpecifier &newInfo =
626 InstructionSpecifiers[uid];
627 InstructionSpecifier &previousInfo =
628 InstructionSpecifiers[decision.instructionIDs[index]];
631 continue; // filtered instructions get lowest priority
633 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
634 newInfo.name == "XCHG32ar" ||
635 newInfo.name == "XCHG32ar64" ||
636 newInfo.name == "XCHG64ar"))
637 continue; // special case for XCHG*ar and NOOP
639 if (outranks(previousInfo.insnContext, newInfo.insnContext))
642 if (previousInfo.insnContext == newInfo.insnContext &&
643 !previousInfo.filtered) {
644 errs() << "Error: Primary decode conflict: ";
645 errs() << newInfo.name << " would overwrite " << previousInfo.name;
647 errs() << "ModRM " << index << "\n";
648 errs() << "Opcode " << (uint16_t)opcode << "\n";
649 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
654 decision.instructionIDs[index] = uid;
659 void DisassemblerTables::setTableFields(OpcodeType type,
660 InstructionContext insnContext,
662 const ModRMFilter &filter,
668 ContextDecision &decision = *Tables[type];
670 for (index = 0; index < IC_max; ++index) {
671 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
674 if (inheritsFrom((InstructionContext)index,
675 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
676 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],