1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
25 using namespace X86Disassembler;
27 /// stringForContext - Returns a string containing the name of a particular
28 /// InstructionContext, usually for diagnostic purposes.
30 /// @param insnContext - The instruction class to transform to a string.
31 /// @return - A statically-allocated string constant that contains the
32 /// name of the instruction class.
33 static inline const char* stringForContext(InstructionContext insnContext) {
34 switch (insnContext) {
36 llvm_unreachable("Unhandled instruction class");
37 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
38 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
40 ENUM_ENTRY(n##_KZ_B, r, d)
47 /// stringForOperandType - Like stringForContext, but for OperandTypes.
48 static inline const char* stringForOperandType(OperandType type) {
51 llvm_unreachable("Unhandled type");
52 #define ENUM_ENTRY(i, d) case i: return #i;
58 /// stringForOperandEncoding - like stringForContext, but for
60 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
63 llvm_unreachable("Unhandled encoding");
64 #define ENUM_ENTRY(i, d) case i: return #i;
70 /// inheritsFrom - Indicates whether all instructions in one class also belong
73 /// @param child - The class that may be the subset
74 /// @param parent - The class that may be the superset
75 /// @return - True if child is a subset of parent, false otherwise.
76 static inline bool inheritsFrom(InstructionContext child,
77 InstructionContext parent,
78 bool VEX_LIG = false, bool AdSize64 = false) {
84 return(inheritsFrom(child, IC_64BIT, AdSize64) ||
85 inheritsFrom(child, IC_OPSIZE) ||
86 inheritsFrom(child, IC_ADSIZE) ||
87 inheritsFrom(child, IC_XD) ||
88 inheritsFrom(child, IC_XS));
90 return(inheritsFrom(child, IC_64BIT_REXW) ||
91 inheritsFrom(child, IC_64BIT_OPSIZE) ||
92 (!AdSize64 && inheritsFrom(child, IC_64BIT_ADSIZE)) ||
93 inheritsFrom(child, IC_64BIT_XD) ||
94 inheritsFrom(child, IC_64BIT_XS));
96 return inheritsFrom(child, IC_64BIT_OPSIZE) ||
97 inheritsFrom(child, IC_OPSIZE_ADSIZE);
99 return inheritsFrom(child, IC_OPSIZE_ADSIZE);
100 case IC_OPSIZE_ADSIZE:
102 case IC_64BIT_ADSIZE:
103 return inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE);
104 case IC_64BIT_OPSIZE_ADSIZE:
107 return inheritsFrom(child, IC_64BIT_XD);
109 return inheritsFrom(child, IC_64BIT_XS);
111 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
113 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
115 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
116 inheritsFrom(child, IC_64BIT_REXW_XD) ||
117 inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
118 (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE)));
119 case IC_64BIT_OPSIZE:
120 return inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
121 (!AdSize64 && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE)) ||
122 (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE));
124 return(inheritsFrom(child, IC_64BIT_REXW_XD));
126 return(inheritsFrom(child, IC_64BIT_REXW_XS));
127 case IC_64BIT_XD_OPSIZE:
128 case IC_64BIT_XS_OPSIZE:
130 case IC_64BIT_REXW_XD:
131 case IC_64BIT_REXW_XS:
132 case IC_64BIT_REXW_OPSIZE:
133 case IC_64BIT_REXW_ADSIZE:
136 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
137 inheritsFrom(child, IC_VEX_W) ||
138 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
140 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
141 inheritsFrom(child, IC_VEX_W_XS) ||
142 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
144 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
145 inheritsFrom(child, IC_VEX_W_XD) ||
146 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
148 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
149 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
150 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
152 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
154 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
156 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
157 case IC_VEX_W_OPSIZE:
158 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
160 return inheritsFrom(child, IC_VEX_L_W);
162 return inheritsFrom(child, IC_VEX_L_W_XS);
164 return inheritsFrom(child, IC_VEX_L_W_XD);
165 case IC_VEX_L_OPSIZE:
166 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
170 case IC_VEX_L_W_OPSIZE:
173 return inheritsFrom(child, IC_EVEX_W) ||
174 inheritsFrom(child, IC_EVEX_L_W);
176 return inheritsFrom(child, IC_EVEX_W_XS) ||
177 inheritsFrom(child, IC_EVEX_L_W_XS);
179 return inheritsFrom(child, IC_EVEX_W_XD) ||
180 inheritsFrom(child, IC_EVEX_L_W_XD);
182 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
183 inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
189 case IC_EVEX_W_OPSIZE:
197 case IC_EVEX_L_OPSIZE:
202 case IC_EVEX_L_W_OPSIZE:
207 case IC_EVEX_L2_OPSIZE:
210 case IC_EVEX_L2_W_XS:
211 case IC_EVEX_L2_W_XD:
212 case IC_EVEX_L2_W_OPSIZE:
215 return inheritsFrom(child, IC_EVEX_W_K) ||
216 inheritsFrom(child, IC_EVEX_L_W_K);
219 case IC_EVEX_XS_KZ_B:
220 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
221 inheritsFrom(child, IC_EVEX_L_W_XS_K);
224 case IC_EVEX_XD_KZ_B:
225 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
226 inheritsFrom(child, IC_EVEX_L_W_XD_K);
233 return inheritsFrom(child, IC_EVEX_W_XS_KZ) ||
234 inheritsFrom(child, IC_EVEX_L_W_XS_KZ);
236 return inheritsFrom(child, IC_EVEX_W_XD_KZ) ||
237 inheritsFrom(child, IC_EVEX_L_W_XD_KZ);
239 case IC_EVEX_OPSIZE_K:
240 case IC_EVEX_OPSIZE_B:
241 case IC_EVEX_OPSIZE_K_B:
242 case IC_EVEX_OPSIZE_KZ:
243 case IC_EVEX_OPSIZE_KZ_B:
251 case IC_EVEX_W_OPSIZE_K:
252 case IC_EVEX_W_OPSIZE_B:
253 case IC_EVEX_W_OPSIZE_K_B:
259 case IC_EVEX_L_XD_K_B:
260 case IC_EVEX_L_OPSIZE_K:
261 case IC_EVEX_L_OPSIZE_B:
262 case IC_EVEX_L_OPSIZE_K_B:
265 case IC_EVEX_W_XS_KZ:
266 case IC_EVEX_W_XD_KZ:
269 case IC_EVEX_W_XS_K_B:
270 case IC_EVEX_W_XD_K_B:
271 case IC_EVEX_W_XS_KZ_B:
272 case IC_EVEX_W_XD_KZ_B:
273 case IC_EVEX_W_OPSIZE_KZ:
274 case IC_EVEX_W_OPSIZE_KZ_B:
277 case IC_EVEX_L_XS_KZ:
279 case IC_EVEX_L_XS_K_B:
280 case IC_EVEX_L_XS_KZ_B:
281 case IC_EVEX_L_XD_KZ:
282 case IC_EVEX_L_XD_KZ_B:
283 case IC_EVEX_L_OPSIZE_KZ:
284 case IC_EVEX_L_OPSIZE_KZ_B:
288 case IC_EVEX_L_W_K_B:
289 case IC_EVEX_L_W_XS_K:
290 case IC_EVEX_L_W_XS_B:
291 case IC_EVEX_L_W_XS_K_B:
292 case IC_EVEX_L_W_XS_KZ:
293 case IC_EVEX_L_W_XS_KZ_B:
294 case IC_EVEX_L_W_OPSIZE_K:
295 case IC_EVEX_L_W_OPSIZE_B:
296 case IC_EVEX_L_W_OPSIZE_K_B:
298 case IC_EVEX_L_W_KZ_B:
299 case IC_EVEX_L_W_XD_K:
300 case IC_EVEX_L_W_XD_B:
301 case IC_EVEX_L_W_XD_K_B:
302 case IC_EVEX_L_W_XD_KZ:
303 case IC_EVEX_L_W_XD_KZ_B:
304 case IC_EVEX_L_W_OPSIZE_KZ:
305 case IC_EVEX_L_W_OPSIZE_KZ_B:
310 case IC_EVEX_L2_KZ_B:
311 case IC_EVEX_L2_XS_K:
312 case IC_EVEX_L2_XS_K_B:
313 case IC_EVEX_L2_XS_B:
314 case IC_EVEX_L2_XD_B:
315 case IC_EVEX_L2_XD_K:
316 case IC_EVEX_L2_XD_K_B:
317 case IC_EVEX_L2_OPSIZE_K:
318 case IC_EVEX_L2_OPSIZE_B:
319 case IC_EVEX_L2_OPSIZE_K_B:
321 case IC_EVEX_L2_XS_KZ:
322 case IC_EVEX_L2_XS_KZ_B:
323 case IC_EVEX_L2_XD_KZ:
324 case IC_EVEX_L2_XD_KZ_B:
325 case IC_EVEX_L2_OPSIZE_KZ:
326 case IC_EVEX_L2_OPSIZE_KZ_B:
330 case IC_EVEX_L2_W_K_B:
331 case IC_EVEX_L2_W_KZ_B:
332 case IC_EVEX_L2_W_XS_K:
333 case IC_EVEX_L2_W_XS_B:
334 case IC_EVEX_L2_W_XS_K_B:
335 case IC_EVEX_L2_W_XD_K:
336 case IC_EVEX_L2_W_XD_B:
337 case IC_EVEX_L2_W_OPSIZE_K:
338 case IC_EVEX_L2_W_OPSIZE_B:
339 case IC_EVEX_L2_W_OPSIZE_K_B:
340 case IC_EVEX_L2_W_KZ:
341 case IC_EVEX_L2_W_XS_KZ:
342 case IC_EVEX_L2_W_XS_KZ_B:
343 case IC_EVEX_L2_W_XD_KZ:
344 case IC_EVEX_L2_W_XD_K_B:
345 case IC_EVEX_L2_W_XD_KZ_B:
346 case IC_EVEX_L2_W_OPSIZE_KZ:
347 case IC_EVEX_L2_W_OPSIZE_KZ_B:
350 errs() << "Unknown instruction class: " <<
351 stringForContext((InstructionContext)parent) << "\n";
352 llvm_unreachable("Unknown instruction class");
356 /// outranks - Indicates whether, if an instruction has two different applicable
357 /// classes, which class should be preferred when performing decode. This
358 /// imposes a total ordering (ties are resolved toward "lower")
360 /// @param upper - The class that may be preferable
361 /// @param lower - The class that may be less preferable
362 /// @return - True if upper is to be preferred, false otherwise.
363 static inline bool outranks(InstructionContext upper,
364 InstructionContext lower) {
365 assert(upper < IC_max);
366 assert(lower < IC_max);
368 #define ENUM_ENTRY(n, r, d) r,
369 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
370 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \
371 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
372 static int ranks[IC_max] = {
376 #undef ENUM_ENTRY_K_B
378 return (ranks[upper] > ranks[lower]);
381 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
382 /// be compacted by eliminating redundant information.
384 /// @param decision - The decision to be compacted.
385 /// @return - The compactest available representation for the decision.
386 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
387 bool satisfiesOneEntry = true;
388 bool satisfiesSplitRM = true;
389 bool satisfiesSplitReg = true;
390 bool satisfiesSplitMisc = true;
392 for (unsigned index = 0; index < 256; ++index) {
393 if (decision.instructionIDs[index] != decision.instructionIDs[0])
394 satisfiesOneEntry = false;
396 if (((index & 0xc0) == 0xc0) &&
397 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
398 satisfiesSplitRM = false;
400 if (((index & 0xc0) != 0xc0) &&
401 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
402 satisfiesSplitRM = false;
404 if (((index & 0xc0) == 0xc0) &&
405 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
406 satisfiesSplitReg = false;
408 if (((index & 0xc0) != 0xc0) &&
409 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
410 satisfiesSplitMisc = false;
413 if (satisfiesOneEntry)
414 return MODRM_ONEENTRY;
416 if (satisfiesSplitRM)
417 return MODRM_SPLITRM;
419 if (satisfiesSplitReg && satisfiesSplitMisc)
420 return MODRM_SPLITREG;
422 if (satisfiesSplitMisc)
423 return MODRM_SPLITMISC;
428 /// stringForDecisionType - Returns a statically-allocated string corresponding
429 /// to a particular decision type.
431 /// @param dt - The decision type.
432 /// @return - A pointer to the statically-allocated string (e.g.,
433 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
434 static const char* stringForDecisionType(ModRMDecisionType dt) {
435 #define ENUM_ENTRY(n) case n: return #n;
438 llvm_unreachable("Unknown decision type");
444 DisassemblerTables::DisassemblerTables() {
447 for (i = 0; i < array_lengthof(Tables); i++) {
448 Tables[i] = new ContextDecision;
449 memset(Tables[i], 0, sizeof(ContextDecision));
452 HasConflicts = false;
455 DisassemblerTables::~DisassemblerTables() {
458 for (i = 0; i < array_lengthof(Tables); i++)
462 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
463 unsigned &i1, unsigned &i2,
464 unsigned &ModRMTableNum,
465 ModRMDecision &decision) const {
466 static uint32_t sTableNumber = 0;
467 static uint32_t sEntryNumber = 1;
468 ModRMDecisionType dt = getDecisionType(decision);
470 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
472 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
475 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
476 o2.indent(i2) << 0 << " /* EmptyTable */\n";
479 o2.indent(i2) << "}";
483 std::vector<unsigned> ModRMDecision;
487 llvm_unreachable("Unknown decision type");
489 ModRMDecision.push_back(decision.instructionIDs[0]);
492 ModRMDecision.push_back(decision.instructionIDs[0x00]);
493 ModRMDecision.push_back(decision.instructionIDs[0xc0]);
496 for (unsigned index = 0; index < 64; index += 8)
497 ModRMDecision.push_back(decision.instructionIDs[index]);
498 for (unsigned index = 0xc0; index < 256; index += 8)
499 ModRMDecision.push_back(decision.instructionIDs[index]);
501 case MODRM_SPLITMISC:
502 for (unsigned index = 0; index < 64; index += 8)
503 ModRMDecision.push_back(decision.instructionIDs[index]);
504 for (unsigned index = 0xc0; index < 256; ++index)
505 ModRMDecision.push_back(decision.instructionIDs[index]);
508 for (unsigned index = 0; index < 256; ++index)
509 ModRMDecision.push_back(decision.instructionIDs[index]);
513 unsigned &EntryNumber = ModRMTable[ModRMDecision];
514 if (EntryNumber == 0) {
515 EntryNumber = ModRMTableNum;
517 ModRMTableNum += ModRMDecision.size();
518 o1 << "/* Table" << EntryNumber << " */\n";
520 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
521 E = ModRMDecision.end(); I != E; ++I) {
522 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* "
523 << InstructionSpecifiers[*I].name << " */\n";
528 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
531 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
532 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n";
535 o2.indent(i2) << "}";
539 llvm_unreachable("Unknown decision type");
549 case MODRM_SPLITMISC:
550 sEntryNumber += 8 + 64;
557 // We assume that the index can fit into uint16_t.
558 assert(sEntryNumber < 65536U &&
559 "Index into ModRMDecision is too large for uint16_t!");
564 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
565 unsigned &i1, unsigned &i2,
566 unsigned &ModRMTableNum,
567 OpcodeDecision &decision) const {
568 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
570 o2.indent(i2) << "{" << "\n";
573 for (unsigned index = 0; index < 256; ++index) {
576 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
578 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
579 decision.modRMDecisions[index]);
588 o2.indent(i2) << "}" << "\n";
590 o2.indent(i2) << "}" << "\n";
593 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
594 unsigned &i1, unsigned &i2,
595 unsigned &ModRMTableNum,
596 ContextDecision &decision,
597 const char* name) const {
598 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
600 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
603 for (unsigned index = 0; index < IC_max; ++index) {
604 o2.indent(i2) << "/* ";
605 o2 << stringForContext((InstructionContext)index);
609 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
610 decision.opcodeDecisions[index]);
612 if (index + 1 < IC_max)
617 o2.indent(i2) << "}" << "\n";
619 o2.indent(i2) << "};" << "\n";
622 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
624 unsigned NumInstructions = InstructionSpecifiers.size();
626 o << "static const struct OperandSpecifier x86OperandSets[]["
627 << X86_MAX_OPERANDS << "] = {\n";
629 typedef SmallVector<std::pair<OperandEncoding, OperandType>,
630 X86_MAX_OPERANDS> OperandListTy;
631 std::map<OperandListTy, unsigned> OperandSets;
633 unsigned OperandSetNum = 0;
634 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
635 OperandListTy OperandList;
637 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
639 OperandEncoding Encoding = (OperandEncoding)InstructionSpecifiers[Index]
640 .operands[OperandIndex].encoding;
641 OperandType Type = (OperandType)InstructionSpecifiers[Index]
642 .operands[OperandIndex].type;
643 OperandList.push_back(std::make_pair(Encoding, Type));
645 unsigned &N = OperandSets[OperandList];
646 if (N != 0) continue;
650 o << " { /* " << (OperandSetNum - 1) << " */\n";
651 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
652 const char *Encoding = stringForOperandEncoding(OperandList[i].first);
653 const char *Type = stringForOperandType(OperandList[i].second);
654 o << " { " << Encoding << ", " << Type << " },\n";
660 o.indent(i * 2) << "static const struct InstructionSpecifier ";
661 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
665 for (unsigned index = 0; index < NumInstructions; ++index) {
666 o.indent(i * 2) << "{ /* " << index << " */\n";
669 OperandListTy OperandList;
670 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
672 OperandEncoding Encoding = (OperandEncoding)InstructionSpecifiers[index]
673 .operands[OperandIndex].encoding;
674 OperandType Type = (OperandType)InstructionSpecifiers[index]
675 .operands[OperandIndex].type;
676 OperandList.push_back(std::make_pair(Encoding, Type));
678 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
680 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */\n";
683 o.indent(i * 2) << "},\n";
687 o.indent(i * 2) << "};" << "\n";
690 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
691 const unsigned int tableSize = 16384;
692 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
693 "[" << tableSize << "] = {\n";
696 for (unsigned index = 0; index < tableSize; ++index) {
699 if (index & ATTR_EVEX) {
701 if (index & ATTR_EVEXL2)
703 else if (index & ATTR_EVEXL)
705 if (index & ATTR_REXW)
707 if (index & ATTR_OPSIZE)
709 else if (index & ATTR_XD)
711 else if (index & ATTR_XS)
713 if (index & ATTR_EVEXKZ)
715 else if (index & ATTR_EVEXK)
717 if (index & ATTR_EVEXB)
720 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
721 o << "IC_VEX_L_W_OPSIZE";
722 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
723 o << "IC_VEX_L_W_XD";
724 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
725 o << "IC_VEX_L_W_XS";
726 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
728 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
729 o << "IC_VEX_L_OPSIZE";
730 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
732 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
734 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
735 o << "IC_VEX_W_OPSIZE";
736 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
738 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
740 else if (index & ATTR_VEXL)
742 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
744 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
745 o << "IC_VEX_OPSIZE";
746 else if ((index & ATTR_VEX) && (index & ATTR_XD))
748 else if ((index & ATTR_VEX) && (index & ATTR_XS))
750 else if (index & ATTR_VEX)
752 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
753 o << "IC_64BIT_REXW_XS";
754 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
755 o << "IC_64BIT_REXW_XD";
756 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
757 (index & ATTR_OPSIZE))
758 o << "IC_64BIT_REXW_OPSIZE";
759 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
760 (index & ATTR_ADSIZE))
761 o << "IC_64BIT_REXW_ADSIZE";
762 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
763 o << "IC_64BIT_XD_OPSIZE";
764 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
765 o << "IC_64BIT_XS_OPSIZE";
766 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
768 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
770 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE) &&
771 (index & ATTR_ADSIZE))
772 o << "IC_64BIT_OPSIZE_ADSIZE";
773 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
774 o << "IC_64BIT_OPSIZE";
775 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
776 o << "IC_64BIT_ADSIZE";
777 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
778 o << "IC_64BIT_REXW";
779 else if ((index & ATTR_64BIT))
781 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
783 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
785 else if (index & ATTR_XS)
787 else if (index & ATTR_XD)
789 else if ((index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
790 o << "IC_OPSIZE_ADSIZE";
791 else if (index & ATTR_OPSIZE)
793 else if (index & ATTR_ADSIZE)
798 if (index < tableSize - 1)
803 o << " /* " << index << " */";
809 o.indent(i * 2) << "};" << "\n";
812 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
813 unsigned &i1, unsigned &i2,
814 unsigned &ModRMTableNum) const {
815 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
816 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
817 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
818 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
819 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR);
820 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR);
821 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR);
824 void DisassemblerTables::emit(raw_ostream &o) const {
831 raw_string_ostream o1(s1);
832 raw_string_ostream o2(s2);
834 emitInstructionInfo(o, i2);
837 emitContextTable(o, i2);
840 unsigned ModRMTableNum = 0;
842 o << "static const InstrUID modRMTable[] = {\n";
844 std::vector<unsigned> EmptyTable(1, 0);
845 ModRMTable[EmptyTable] = ModRMTableNum;
846 ModRMTableNum += EmptyTable.size();
847 o1 << "/* EmptyTable */\n";
848 o1.indent(i1 * 2) << "0x0,\n";
850 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
861 void DisassemblerTables::setTableFields(ModRMDecision &decision,
862 const ModRMFilter &filter,
865 for (unsigned index = 0; index < 256; ++index) {
866 if (filter.accepts(index)) {
867 if (decision.instructionIDs[index] == uid)
870 if (decision.instructionIDs[index] != 0) {
871 InstructionSpecifier &newInfo =
872 InstructionSpecifiers[uid];
873 InstructionSpecifier &previousInfo =
874 InstructionSpecifiers[decision.instructionIDs[index]];
876 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
877 newInfo.name == "XCHG32ar" ||
878 newInfo.name == "XCHG32ar64" ||
879 newInfo.name == "XCHG64ar"))
880 continue; // special case for XCHG*ar and NOOP
882 if (outranks(previousInfo.insnContext, newInfo.insnContext))
885 if (previousInfo.insnContext == newInfo.insnContext) {
886 errs() << "Error: Primary decode conflict: ";
887 errs() << newInfo.name << " would overwrite " << previousInfo.name;
889 errs() << "ModRM " << index << "\n";
890 errs() << "Opcode " << (uint16_t)opcode << "\n";
891 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
896 decision.instructionIDs[index] = uid;
901 void DisassemblerTables::setTableFields(OpcodeType type,
902 InstructionContext insnContext,
904 const ModRMFilter &filter,
908 unsigned addressSize) {
909 ContextDecision &decision = *Tables[type];
911 for (unsigned index = 0; index < IC_max; ++index) {
912 if ((is32bit || addressSize == 16) &&
913 inheritsFrom((InstructionContext)index, IC_64BIT))
916 bool adSize64 = addressSize == 64;
917 if (inheritsFrom((InstructionContext)index,
918 InstructionSpecifiers[uid].insnContext, ignoresVEX_L,
920 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],