1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
22 #include "llvm/TableGen/TableGenBackend.h"
26 using namespace X86Disassembler;
28 /// inheritsFrom - Indicates whether all instructions in one class also belong
31 /// @param child - The class that may be the subset
32 /// @param parent - The class that may be the superset
33 /// @return - True if child is a subset of parent, false otherwise.
34 static inline bool inheritsFrom(InstructionContext child,
35 InstructionContext parent,
36 bool VEX_LIG = false) {
42 return(inheritsFrom(child, IC_64BIT) ||
43 inheritsFrom(child, IC_OPSIZE) ||
44 inheritsFrom(child, IC_ADSIZE) ||
45 inheritsFrom(child, IC_XD) ||
46 inheritsFrom(child, IC_XS));
48 return(inheritsFrom(child, IC_64BIT_REXW) ||
49 inheritsFrom(child, IC_64BIT_OPSIZE) ||
50 inheritsFrom(child, IC_64BIT_ADSIZE) ||
51 inheritsFrom(child, IC_64BIT_XD) ||
52 inheritsFrom(child, IC_64BIT_XS));
54 return inheritsFrom(child, IC_64BIT_OPSIZE);
59 return inheritsFrom(child, IC_64BIT_XD);
61 return inheritsFrom(child, IC_64BIT_XS);
63 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
65 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
67 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
68 inheritsFrom(child, IC_64BIT_REXW_XD) ||
69 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
71 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
73 return(inheritsFrom(child, IC_64BIT_REXW_XD));
75 return(inheritsFrom(child, IC_64BIT_REXW_XS));
76 case IC_64BIT_XD_OPSIZE:
77 case IC_64BIT_XS_OPSIZE:
79 case IC_64BIT_REXW_XD:
80 case IC_64BIT_REXW_XS:
81 case IC_64BIT_REXW_OPSIZE:
84 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
85 inheritsFrom(child, IC_VEX_W) ||
86 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
88 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
89 inheritsFrom(child, IC_VEX_W_XS) ||
90 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
92 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
93 inheritsFrom(child, IC_VEX_W_XD) ||
94 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
96 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
97 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
98 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
100 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
102 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
104 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
105 case IC_VEX_W_OPSIZE:
106 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
108 return inheritsFrom(child, IC_VEX_L_W);
110 return inheritsFrom(child, IC_VEX_L_W_XS);
112 return inheritsFrom(child, IC_VEX_L_W_XD);
113 case IC_VEX_L_OPSIZE:
114 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
118 case IC_VEX_L_W_OPSIZE:
121 return inheritsFrom(child, IC_EVEX_W) ||
122 inheritsFrom(child, IC_EVEX_L_W);
124 return inheritsFrom(child, IC_EVEX_W_XS) ||
125 inheritsFrom(child, IC_EVEX_L_W_XS);
127 return inheritsFrom(child, IC_EVEX_W_XD) ||
128 inheritsFrom(child, IC_EVEX_L_W_XD);
130 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
131 inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
135 case IC_EVEX_W_OPSIZE:
140 case IC_EVEX_L_OPSIZE:
145 case IC_EVEX_L_W_OPSIZE:
150 case IC_EVEX_L2_OPSIZE:
153 case IC_EVEX_L2_W_XS:
154 case IC_EVEX_L2_W_XD:
155 case IC_EVEX_L2_W_OPSIZE:
158 return inheritsFrom(child, IC_EVEX_W_K) ||
159 inheritsFrom(child, IC_EVEX_L_W_K);
161 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
162 inheritsFrom(child, IC_EVEX_L_W_XS_K);
164 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
165 inheritsFrom(child, IC_EVEX_L_W_XD_K);
166 case IC_EVEX_OPSIZE_K:
167 return inheritsFrom(child, IC_EVEX_W_OPSIZE_K) ||
168 inheritsFrom(child, IC_EVEX_W_OPSIZE_K);
172 case IC_EVEX_W_OPSIZE_K:
177 case IC_EVEX_L_OPSIZE_K:
180 case IC_EVEX_W_XS_KZ:
181 case IC_EVEX_W_XD_KZ:
182 case IC_EVEX_W_OPSIZE_KZ:
185 case IC_EVEX_L_XS_KZ:
186 case IC_EVEX_L_XD_KZ:
187 case IC_EVEX_L_OPSIZE_KZ:
190 case IC_EVEX_L_W_XS_K:
191 case IC_EVEX_L_W_XD_K:
192 case IC_EVEX_L_W_OPSIZE_K:
194 case IC_EVEX_L_W_XS_KZ:
195 case IC_EVEX_L_W_XD_KZ:
196 case IC_EVEX_L_W_OPSIZE_KZ:
200 case IC_EVEX_L2_XS_K:
201 case IC_EVEX_L2_XD_K:
202 case IC_EVEX_L2_OPSIZE_K:
203 case IC_EVEX_L2_OPSIZE_B:
204 case IC_EVEX_L2_OPSIZE_K_B:
206 case IC_EVEX_L2_XS_KZ:
207 case IC_EVEX_L2_XD_KZ:
208 case IC_EVEX_L2_OPSIZE_KZ:
209 case IC_EVEX_L2_OPSIZE_KZ_B:
213 case IC_EVEX_L2_W_XS_K:
214 case IC_EVEX_L2_W_XD_K:
215 case IC_EVEX_L2_W_OPSIZE_K:
216 case IC_EVEX_L2_W_OPSIZE_B:
217 case IC_EVEX_L2_W_OPSIZE_K_B:
218 case IC_EVEX_L2_W_KZ:
219 case IC_EVEX_L2_W_XS_KZ:
220 case IC_EVEX_L2_W_XD_KZ:
221 case IC_EVEX_L2_W_OPSIZE_KZ:
222 case IC_EVEX_L2_W_OPSIZE_KZ_B:
225 llvm_unreachable("Unknown instruction class");
229 /// outranks - Indicates whether, if an instruction has two different applicable
230 /// classes, which class should be preferred when performing decode. This
231 /// imposes a total ordering (ties are resolved toward "lower")
233 /// @param upper - The class that may be preferable
234 /// @param lower - The class that may be less preferable
235 /// @return - True if upper is to be preferred, false otherwise.
236 static inline bool outranks(InstructionContext upper,
237 InstructionContext lower) {
238 assert(upper < IC_max);
239 assert(lower < IC_max);
241 #define ENUM_ENTRY(n, r, d) r,
242 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
243 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \
244 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
245 static int ranks[IC_max] = {
249 #undef ENUM_ENTRY_K_B
251 return (ranks[upper] > ranks[lower]);
254 /// stringForContext - Returns a string containing the name of a particular
255 /// InstructionContext, usually for diagnostic purposes.
257 /// @param insnContext - The instruction class to transform to a string.
258 /// @return - A statically-allocated string constant that contains the
259 /// name of the instruction class.
260 static inline const char* stringForContext(InstructionContext insnContext) {
261 switch (insnContext) {
263 llvm_unreachable("Unhandled instruction class");
264 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
265 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
266 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
267 ENUM_ENTRY(n##_KZ_B, r, d)
270 #undef ENUM_ENTRY_K_B
274 /// stringForOperandType - Like stringForContext, but for OperandTypes.
275 static inline const char* stringForOperandType(OperandType type) {
278 llvm_unreachable("Unhandled type");
279 #define ENUM_ENTRY(i, d) case i: return #i;
285 /// stringForOperandEncoding - like stringForContext, but for
286 /// OperandEncodings.
287 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
290 llvm_unreachable("Unhandled encoding");
291 #define ENUM_ENTRY(i, d) case i: return #i;
297 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
298 /// be compacted by eliminating redundant information.
300 /// @param decision - The decision to be compacted.
301 /// @return - The compactest available representation for the decision.
302 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
303 bool satisfiesOneEntry = true;
304 bool satisfiesSplitRM = true;
305 bool satisfiesSplitReg = true;
306 bool satisfiesSplitMisc = true;
308 for (unsigned index = 0; index < 256; ++index) {
309 if (decision.instructionIDs[index] != decision.instructionIDs[0])
310 satisfiesOneEntry = false;
312 if (((index & 0xc0) == 0xc0) &&
313 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
314 satisfiesSplitRM = false;
316 if (((index & 0xc0) != 0xc0) &&
317 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
318 satisfiesSplitRM = false;
320 if (((index & 0xc0) == 0xc0) &&
321 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
322 satisfiesSplitReg = false;
324 if (((index & 0xc0) != 0xc0) &&
325 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
326 satisfiesSplitMisc = false;
329 if (satisfiesOneEntry)
330 return MODRM_ONEENTRY;
332 if (satisfiesSplitRM)
333 return MODRM_SPLITRM;
335 if (satisfiesSplitReg && satisfiesSplitMisc)
336 return MODRM_SPLITREG;
338 if (satisfiesSplitMisc)
339 return MODRM_SPLITMISC;
344 /// stringForDecisionType - Returns a statically-allocated string corresponding
345 /// to a particular decision type.
347 /// @param dt - The decision type.
348 /// @return - A pointer to the statically-allocated string (e.g.,
349 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
350 static const char* stringForDecisionType(ModRMDecisionType dt) {
351 #define ENUM_ENTRY(n) case n: return #n;
354 llvm_unreachable("Unknown decision type");
360 /// stringForModifierType - Returns a statically-allocated string corresponding
361 /// to an opcode modifier type.
363 /// @param mt - The modifier type.
364 /// @return - A pointer to the statically-allocated string (e.g.,
365 /// "MODIFIER_NONE" for MODIFIER_NONE).
366 static const char* stringForModifierType(ModifierType mt) {
367 #define ENUM_ENTRY(n) case n: return #n;
370 llvm_unreachable("Unknown modifier type");
376 DisassemblerTables::DisassemblerTables() {
379 for (i = 0; i < array_lengthof(Tables); i++) {
380 Tables[i] = new ContextDecision;
381 memset(Tables[i], 0, sizeof(ContextDecision));
384 HasConflicts = false;
387 DisassemblerTables::~DisassemblerTables() {
390 for (i = 0; i < array_lengthof(Tables); i++)
394 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
395 unsigned &i1, unsigned &i2,
396 unsigned &ModRMTableNum,
397 ModRMDecision &decision) const {
398 static uint32_t sTableNumber = 0;
399 static uint32_t sEntryNumber = 1;
400 ModRMDecisionType dt = getDecisionType(decision);
402 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
404 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
407 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
408 o2.indent(i2) << 0 << " /* EmptyTable */\n";
411 o2.indent(i2) << "}";
415 std::vector<unsigned> ModRMDecision;
419 llvm_unreachable("Unknown decision type");
421 ModRMDecision.push_back(decision.instructionIDs[0]);
424 ModRMDecision.push_back(decision.instructionIDs[0x00]);
425 ModRMDecision.push_back(decision.instructionIDs[0xc0]);
428 for (unsigned index = 0; index < 64; index += 8)
429 ModRMDecision.push_back(decision.instructionIDs[index]);
430 for (unsigned index = 0xc0; index < 256; index += 8)
431 ModRMDecision.push_back(decision.instructionIDs[index]);
433 case MODRM_SPLITMISC:
434 for (unsigned index = 0; index < 64; index += 8)
435 ModRMDecision.push_back(decision.instructionIDs[index]);
436 for (unsigned index = 0xc0; index < 256; ++index)
437 ModRMDecision.push_back(decision.instructionIDs[index]);
440 for (unsigned index = 0; index < 256; ++index)
441 ModRMDecision.push_back(decision.instructionIDs[index]);
445 unsigned &EntryNumber = ModRMTable[ModRMDecision];
446 if (EntryNumber == 0) {
447 EntryNumber = ModRMTableNum;
449 ModRMTableNum += ModRMDecision.size();
450 o1 << "/* Table" << EntryNumber << " */\n";
452 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
453 E = ModRMDecision.end(); I != E; ++I) {
454 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* "
455 << InstructionSpecifiers[*I].name << " */\n";
460 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
463 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
464 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n";
467 o2.indent(i2) << "}";
471 llvm_unreachable("Unknown decision type");
481 case MODRM_SPLITMISC:
482 sEntryNumber += 8 + 64;
489 // We assume that the index can fit into uint16_t.
490 assert(sEntryNumber < 65536U &&
491 "Index into ModRMDecision is too large for uint16_t!");
496 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
497 unsigned &i1, unsigned &i2,
498 unsigned &ModRMTableNum,
499 OpcodeDecision &decision) const {
500 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
502 o2.indent(i2) << "{" << "\n";
505 for (unsigned index = 0; index < 256; ++index) {
508 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
510 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
511 decision.modRMDecisions[index]);
520 o2.indent(i2) << "}" << "\n";
522 o2.indent(i2) << "}" << "\n";
525 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
526 unsigned &i1, unsigned &i2,
527 unsigned &ModRMTableNum,
528 ContextDecision &decision,
529 const char* name) const {
530 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
532 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
535 for (unsigned index = 0; index < IC_max; ++index) {
536 o2.indent(i2) << "/* ";
537 o2 << stringForContext((InstructionContext)index);
541 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
542 decision.opcodeDecisions[index]);
544 if (index + 1 < IC_max)
549 o2.indent(i2) << "}" << "\n";
551 o2.indent(i2) << "};" << "\n";
554 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
556 unsigned NumInstructions = InstructionSpecifiers.size();
558 o << "static const struct OperandSpecifier x86OperandSets[]["
559 << X86_MAX_OPERANDS << "] = {\n";
561 typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
562 std::map<OperandListTy, unsigned> OperandSets;
564 unsigned OperandSetNum = 0;
565 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
566 OperandListTy OperandList;
568 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
570 const char *Encoding =
571 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
572 .operands[OperandIndex].encoding);
574 stringForOperandType((OperandType)InstructionSpecifiers[Index]
575 .operands[OperandIndex].type);
576 OperandList.push_back(std::make_pair(Encoding, Type));
578 unsigned &N = OperandSets[OperandList];
579 if (N != 0) continue;
583 o << " { /* " << (OperandSetNum - 1) << " */\n";
584 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
585 o << " { " << OperandList[i].first << ", "
586 << OperandList[i].second << " },\n";
592 o.indent(i * 2) << "static const struct InstructionSpecifier ";
593 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
597 for (unsigned index = 0; index < NumInstructions; ++index) {
598 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
601 o.indent(i * 2) << stringForModifierType(
602 (ModifierType)InstructionSpecifiers[index].modifierType);
605 o.indent(i * 2) << "0x";
606 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
609 OperandListTy OperandList;
610 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
612 const char *Encoding =
613 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
614 .operands[OperandIndex].encoding);
616 stringForOperandType((OperandType)InstructionSpecifiers[index]
617 .operands[OperandIndex].type);
618 OperandList.push_back(std::make_pair(Encoding, Type));
620 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
622 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
626 o.indent(i * 2) << "}";
628 if (index + 1 < NumInstructions)
635 o.indent(i * 2) << "};" << "\n";
638 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
639 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
643 for (unsigned index = 0; index < 256; ++index) {
646 if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
647 o << "IC_VEX_L_W_OPSIZE";
648 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
649 o << "IC_VEX_L_W_XD";
650 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
651 o << "IC_VEX_L_W_XS";
652 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
654 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
655 o << "IC_VEX_L_OPSIZE";
656 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
658 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
660 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
661 o << "IC_VEX_W_OPSIZE";
662 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
664 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
666 else if (index & ATTR_VEXL)
668 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
670 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
671 o << "IC_VEX_OPSIZE";
672 else if ((index & ATTR_VEX) && (index & ATTR_XD))
674 else if ((index & ATTR_VEX) && (index & ATTR_XS))
676 else if (index & ATTR_VEX)
678 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
679 o << "IC_64BIT_REXW_XS";
680 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
681 o << "IC_64BIT_REXW_XD";
682 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
683 (index & ATTR_OPSIZE))
684 o << "IC_64BIT_REXW_OPSIZE";
685 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
686 o << "IC_64BIT_XD_OPSIZE";
687 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
688 o << "IC_64BIT_XS_OPSIZE";
689 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
691 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
693 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
694 o << "IC_64BIT_OPSIZE";
695 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
696 o << "IC_64BIT_ADSIZE";
697 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
698 o << "IC_64BIT_REXW";
699 else if ((index & ATTR_64BIT))
701 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
703 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
705 else if (index & ATTR_XS)
707 else if (index & ATTR_XD)
709 else if (index & ATTR_OPSIZE)
711 else if (index & ATTR_ADSIZE)
721 o << " /* " << index << " */";
727 o.indent(i * 2) << "};" << "\n";
730 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
731 unsigned &i1, unsigned &i2,
732 unsigned &ModRMTableNum) const {
733 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
734 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
735 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
736 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
737 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], THREEBYTEA6_STR);
738 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], THREEBYTEA7_STR);
739 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOP8_MAP_STR);
740 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[7], XOP9_MAP_STR);
741 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[8], XOPA_MAP_STR);
744 void DisassemblerTables::emit(raw_ostream &o) const {
751 raw_string_ostream o1(s1);
752 raw_string_ostream o2(s2);
754 emitInstructionInfo(o, i2);
757 emitContextTable(o, i2);
760 unsigned ModRMTableNum = 0;
762 o << "static const InstrUID modRMTable[] = {\n";
764 std::vector<unsigned> EmptyTable(1, 0);
765 ModRMTable[EmptyTable] = ModRMTableNum;
766 ModRMTableNum += EmptyTable.size();
767 o1 << "/* EmptyTable */\n";
768 o1.indent(i1 * 2) << "0x0,\n";
770 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
781 void DisassemblerTables::setTableFields(ModRMDecision &decision,
782 const ModRMFilter &filter,
785 for (unsigned index = 0; index < 256; ++index) {
786 if (filter.accepts(index)) {
787 if (decision.instructionIDs[index] == uid)
790 if (decision.instructionIDs[index] != 0) {
791 InstructionSpecifier &newInfo =
792 InstructionSpecifiers[uid];
793 InstructionSpecifier &previousInfo =
794 InstructionSpecifiers[decision.instructionIDs[index]];
797 continue; // filtered instructions get lowest priority
799 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
800 newInfo.name == "XCHG32ar" ||
801 newInfo.name == "XCHG32ar64" ||
802 newInfo.name == "XCHG64ar"))
803 continue; // special case for XCHG*ar and NOOP
805 if (outranks(previousInfo.insnContext, newInfo.insnContext))
808 if (previousInfo.insnContext == newInfo.insnContext &&
809 !previousInfo.filtered) {
810 errs() << "Error: Primary decode conflict: ";
811 errs() << newInfo.name << " would overwrite " << previousInfo.name;
813 errs() << "ModRM " << index << "\n";
814 errs() << "Opcode " << (uint16_t)opcode << "\n";
815 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
820 decision.instructionIDs[index] = uid;
825 void DisassemblerTables::setTableFields(OpcodeType type,
826 InstructionContext insnContext,
828 const ModRMFilter &filter,
832 ContextDecision &decision = *Tables[type];
834 for (unsigned index = 0; index < IC_max; ++index) {
835 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
838 if (inheritsFrom((InstructionContext)index,
839 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
840 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],