1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86DisassemblerTables.h"
20 #include "llvm/TableGen/TableGenBackend.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/Format.h"
26 using namespace X86Disassembler;
28 /// inheritsFrom - Indicates whether all instructions in one class also belong
31 /// @param child - The class that may be the subset
32 /// @param parent - The class that may be the superset
33 /// @return - True if child is a subset of parent, false otherwise.
34 static inline bool inheritsFrom(InstructionContext child,
35 InstructionContext parent,
36 bool VEX_LIG = false) {
42 return(inheritsFrom(child, IC_64BIT) ||
43 inheritsFrom(child, IC_OPSIZE) ||
44 inheritsFrom(child, IC_ADSIZE) ||
45 inheritsFrom(child, IC_XD) ||
46 inheritsFrom(child, IC_XS));
48 return(inheritsFrom(child, IC_64BIT_REXW) ||
49 inheritsFrom(child, IC_64BIT_OPSIZE) ||
50 inheritsFrom(child, IC_64BIT_ADSIZE) ||
51 inheritsFrom(child, IC_64BIT_XD) ||
52 inheritsFrom(child, IC_64BIT_XS));
54 return inheritsFrom(child, IC_64BIT_OPSIZE);
59 return inheritsFrom(child, IC_64BIT_XD);
61 return inheritsFrom(child, IC_64BIT_XS);
63 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
65 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
67 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
68 inheritsFrom(child, IC_64BIT_REXW_XD) ||
69 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
71 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
73 return(inheritsFrom(child, IC_64BIT_REXW_XD));
75 return(inheritsFrom(child, IC_64BIT_REXW_XS));
76 case IC_64BIT_XD_OPSIZE:
77 case IC_64BIT_XS_OPSIZE:
79 case IC_64BIT_REXW_XD:
80 case IC_64BIT_REXW_XS:
81 case IC_64BIT_REXW_OPSIZE:
84 return inheritsFrom(child, IC_VEX_W) ||
85 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
87 return inheritsFrom(child, IC_VEX_W_XS) ||
88 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
90 return inheritsFrom(child, IC_VEX_W_XD) ||
91 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
93 return inheritsFrom(child, IC_VEX_W_OPSIZE) ||
94 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
104 case IC_VEX_L_OPSIZE:
105 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
106 case IC_VEX_L_W_OPSIZE:
109 llvm_unreachable("Unknown instruction class");
113 /// outranks - Indicates whether, if an instruction has two different applicable
114 /// classes, which class should be preferred when performing decode. This
115 /// imposes a total ordering (ties are resolved toward "lower")
117 /// @param upper - The class that may be preferable
118 /// @param lower - The class that may be less preferable
119 /// @return - True if upper is to be preferred, false otherwise.
120 static inline bool outranks(InstructionContext upper,
121 InstructionContext lower) {
122 assert(upper < IC_max);
123 assert(lower < IC_max);
125 #define ENUM_ENTRY(n, r, d) r,
126 static int ranks[IC_max] = {
131 return (ranks[upper] > ranks[lower]);
134 /// stringForContext - Returns a string containing the name of a particular
135 /// InstructionContext, usually for diagnostic purposes.
137 /// @param insnContext - The instruction class to transform to a string.
138 /// @return - A statically-allocated string constant that contains the
139 /// name of the instruction class.
140 static inline const char* stringForContext(InstructionContext insnContext) {
141 switch (insnContext) {
143 llvm_unreachable("Unhandled instruction class");
144 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
150 /// stringForOperandType - Like stringForContext, but for OperandTypes.
151 static inline const char* stringForOperandType(OperandType type) {
154 llvm_unreachable("Unhandled type");
155 #define ENUM_ENTRY(i, d) case i: return #i;
161 /// stringForOperandEncoding - like stringForContext, but for
162 /// OperandEncodings.
163 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
166 llvm_unreachable("Unhandled encoding");
167 #define ENUM_ENTRY(i, d) case i: return #i;
173 void DisassemblerTables::emitOneID(raw_ostream &o, unsigned &i, InstrUID id,
174 bool addComma) const {
176 o.indent(i * 2) << format("0x%hx", id);
178 o.indent(i * 2) << 0;
186 o << InstructionSpecifiers[id].name;
192 /// emitEmptyTable - Emits the modRMEmptyTable, which is used as a ID table by
193 /// all ModR/M decisions for instructions that are invalid for all possible
194 /// ModR/M byte values.
196 /// @param o - The output stream on which to emit the table.
197 /// @param i - The indentation level for that output stream.
198 static void emitEmptyTable(raw_ostream &o, unsigned &i) {
199 o.indent(i * 2) << "0x0, /* EmptyTable */\n";
202 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
203 /// be compacted by eliminating redundant information.
205 /// @param decision - The decision to be compacted.
206 /// @return - The compactest available representation for the decision.
207 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
208 bool satisfiesOneEntry = true;
209 bool satisfiesSplitRM = true;
210 bool satisfiesSplitReg = true;
212 for (unsigned index = 0; index < 256; ++index) {
213 if (decision.instructionIDs[index] != decision.instructionIDs[0])
214 satisfiesOneEntry = false;
216 if (((index & 0xc0) == 0xc0) &&
217 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
218 satisfiesSplitRM = false;
220 if (((index & 0xc0) != 0xc0) &&
221 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
222 satisfiesSplitRM = false;
224 if (((index & 0xc0) == 0xc0) &&
225 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
226 satisfiesSplitReg = false;
228 if (((index & 0xc0) != 0xc0) &&
229 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
230 satisfiesSplitReg = false;
233 if (satisfiesOneEntry)
234 return MODRM_ONEENTRY;
236 if (satisfiesSplitRM)
237 return MODRM_SPLITRM;
239 if (satisfiesSplitReg)
240 return MODRM_SPLITREG;
245 /// stringForDecisionType - Returns a statically-allocated string corresponding
246 /// to a particular decision type.
248 /// @param dt - The decision type.
249 /// @return - A pointer to the statically-allocated string (e.g.,
250 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
251 static const char* stringForDecisionType(ModRMDecisionType dt) {
252 #define ENUM_ENTRY(n) case n: return #n;
255 llvm_unreachable("Unknown decision type");
261 /// stringForModifierType - Returns a statically-allocated string corresponding
262 /// to an opcode modifier type.
264 /// @param mt - The modifier type.
265 /// @return - A pointer to the statically-allocated string (e.g.,
266 /// "MODIFIER_NONE" for MODIFIER_NONE).
267 static const char* stringForModifierType(ModifierType mt) {
268 #define ENUM_ENTRY(n) case n: return #n;
271 llvm_unreachable("Unknown modifier type");
277 DisassemblerTables::DisassemblerTables() {
280 for (i = 0; i < array_lengthof(Tables); i++) {
281 Tables[i] = new ContextDecision;
282 memset(Tables[i], 0, sizeof(ContextDecision));
285 HasConflicts = false;
288 DisassemblerTables::~DisassemblerTables() {
291 for (i = 0; i < array_lengthof(Tables); i++)
295 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
296 unsigned &i1, unsigned &i2,
297 ModRMDecision &decision) const {
298 static uint32_t sTableNumber = 0;
299 static uint32_t sEntryNumber = 1;
300 ModRMDecisionType dt = getDecisionType(decision);
302 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
304 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
307 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
308 o2.indent(i2) << 0 << " /* EmptyTable */\n";
311 o2.indent(i2) << "}";
315 o1 << "/* Table" << sTableNumber << " */\n";
320 llvm_unreachable("Unknown decision type");
322 emitOneID(o1, i1, decision.instructionIDs[0], true);
325 emitOneID(o1, i1, decision.instructionIDs[0x00], true); // mod = 0b00
326 emitOneID(o1, i1, decision.instructionIDs[0xc0], true); // mod = 0b11
329 for (unsigned index = 0; index < 64; index += 8)
330 emitOneID(o1, i1, decision.instructionIDs[index], true);
331 for (unsigned index = 0xc0; index < 256; index += 8)
332 emitOneID(o1, i1, decision.instructionIDs[index], true);
335 for (unsigned index = 0; index < 256; ++index)
336 emitOneID(o1, i1, decision.instructionIDs[index], true);
342 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
345 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
346 o2.indent(i2) << sEntryNumber << " /* Table" << sTableNumber << " */\n";
349 o2.indent(i2) << "}";
353 llvm_unreachable("Unknown decision type");
371 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
372 unsigned &i1, unsigned &i2,
373 OpcodeDecision &decision) const {
374 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
376 o2.indent(i2) << "{" << "\n";
379 for (unsigned index = 0; index < 256; ++index) {
382 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
384 emitModRMDecision(o1, o2, i1, i2, decision.modRMDecisions[index]);
393 o2.indent(i2) << "}" << "\n";
395 o2.indent(i2) << "}" << "\n";
398 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
399 unsigned &i1, unsigned &i2,
400 ContextDecision &decision,
401 const char* name) const {
402 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
404 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
407 for (unsigned index = 0; index < IC_max; ++index) {
408 o2.indent(i2) << "/* ";
409 o2 << stringForContext((InstructionContext)index);
413 emitOpcodeDecision(o1, o2, i1, i2, decision.opcodeDecisions[index]);
415 if (index + 1 < IC_max)
420 o2.indent(i2) << "}" << "\n";
422 o2.indent(i2) << "};" << "\n";
425 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
427 o.indent(i * 2) << "static const struct InstructionSpecifier ";
428 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
432 unsigned numInstructions = InstructionSpecifiers.size();
434 for (unsigned index = 0; index < numInstructions; ++index) {
435 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
438 o.indent(i * 2) << stringForModifierType(
439 (ModifierType)InstructionSpecifiers[index].modifierType);
442 o.indent(i * 2) << "0x";
443 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
446 o.indent(i * 2) << "{" << "\n";
449 for (unsigned operandIndex = 0; operandIndex < X86_MAX_OPERANDS;
451 o.indent(i * 2) << "{ ";
452 o <<stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
453 .operands[operandIndex]
456 o << stringForOperandType((OperandType)InstructionSpecifiers[index]
457 .operands[operandIndex]
461 if (operandIndex < X86_MAX_OPERANDS - 1)
468 o.indent(i * 2) << "}," << "\n";
470 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
474 o.indent(i * 2) << "}";
476 if (index + 1 < numInstructions)
483 o.indent(i * 2) << "};" << "\n";
486 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
487 o.indent(i * 2) << "static const InstructionContext " CONTEXTS_STR
491 for (unsigned index = 0; index < 256; ++index) {
494 if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
495 o << "IC_VEX_L_W_OPSIZE";
496 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
497 o << "IC_VEX_L_OPSIZE";
498 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
500 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
502 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
503 o << "IC_VEX_W_OPSIZE";
504 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
506 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
508 else if (index & ATTR_VEXL)
510 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
512 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
513 o << "IC_VEX_OPSIZE";
514 else if ((index & ATTR_VEX) && (index & ATTR_XD))
516 else if ((index & ATTR_VEX) && (index & ATTR_XS))
518 else if (index & ATTR_VEX)
520 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
521 o << "IC_64BIT_REXW_XS";
522 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
523 o << "IC_64BIT_REXW_XD";
524 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
525 (index & ATTR_OPSIZE))
526 o << "IC_64BIT_REXW_OPSIZE";
527 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
528 o << "IC_64BIT_XD_OPSIZE";
529 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
530 o << "IC_64BIT_XS_OPSIZE";
531 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
533 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
535 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
536 o << "IC_64BIT_OPSIZE";
537 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
538 o << "IC_64BIT_ADSIZE";
539 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
540 o << "IC_64BIT_REXW";
541 else if ((index & ATTR_64BIT))
543 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
545 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
547 else if (index & ATTR_XS)
549 else if (index & ATTR_XD)
551 else if (index & ATTR_OPSIZE)
553 else if (index & ATTR_ADSIZE)
563 o << " /* " << index << " */";
569 o.indent(i * 2) << "};" << "\n";
572 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
573 unsigned &i1, unsigned &i2) const {
574 emitContextDecision(o1, o2, i1, i2, *Tables[0], ONEBYTE_STR);
575 emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR);
576 emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR);
577 emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR);
578 emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR);
579 emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR);
582 void DisassemblerTables::emit(raw_ostream &o) const {
589 raw_string_ostream o1(s1);
590 raw_string_ostream o2(s2);
592 emitInstructionInfo(o, i2);
595 emitContextTable(o, i2);
598 o << "static const InstrUID modRMTable[] = {\n";
600 emitEmptyTable(o1, i1);
602 emitContextDecisions(o1, o2, i1, i2);
613 void DisassemblerTables::setTableFields(ModRMDecision &decision,
614 const ModRMFilter &filter,
617 for (unsigned index = 0; index < 256; ++index) {
618 if (filter.accepts(index)) {
619 if (decision.instructionIDs[index] == uid)
622 if (decision.instructionIDs[index] != 0) {
623 InstructionSpecifier &newInfo =
624 InstructionSpecifiers[uid];
625 InstructionSpecifier &previousInfo =
626 InstructionSpecifiers[decision.instructionIDs[index]];
629 continue; // filtered instructions get lowest priority
631 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
632 newInfo.name == "XCHG32ar" ||
633 newInfo.name == "XCHG32ar64" ||
634 newInfo.name == "XCHG64ar"))
635 continue; // special case for XCHG*ar and NOOP
637 if (outranks(previousInfo.insnContext, newInfo.insnContext))
640 if (previousInfo.insnContext == newInfo.insnContext &&
641 !previousInfo.filtered) {
642 errs() << "Error: Primary decode conflict: ";
643 errs() << newInfo.name << " would overwrite " << previousInfo.name;
645 errs() << "ModRM " << index << "\n";
646 errs() << "Opcode " << (uint16_t)opcode << "\n";
647 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
652 decision.instructionIDs[index] = uid;
657 void DisassemblerTables::setTableFields(OpcodeType type,
658 InstructionContext insnContext,
660 const ModRMFilter &filter,
664 ContextDecision &decision = *Tables[type];
666 for (unsigned index = 0; index < IC_max; ++index) {
667 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
670 if (inheritsFrom((InstructionContext)index,
671 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
672 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],