1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
22 #include "llvm/TableGen/TableGenBackend.h"
26 using namespace X86Disassembler;
28 /// inheritsFrom - Indicates whether all instructions in one class also belong
31 /// @param child - The class that may be the subset
32 /// @param parent - The class that may be the superset
33 /// @return - True if child is a subset of parent, false otherwise.
34 static inline bool inheritsFrom(InstructionContext child,
35 InstructionContext parent,
36 bool VEX_LIG = false) {
42 return(inheritsFrom(child, IC_64BIT) ||
43 inheritsFrom(child, IC_OPSIZE) ||
44 inheritsFrom(child, IC_ADSIZE) ||
45 inheritsFrom(child, IC_XD) ||
46 inheritsFrom(child, IC_XS));
48 return(inheritsFrom(child, IC_64BIT_REXW) ||
49 inheritsFrom(child, IC_64BIT_OPSIZE) ||
50 inheritsFrom(child, IC_64BIT_ADSIZE) ||
51 inheritsFrom(child, IC_64BIT_XD) ||
52 inheritsFrom(child, IC_64BIT_XS));
54 return inheritsFrom(child, IC_64BIT_OPSIZE);
59 return inheritsFrom(child, IC_64BIT_XD);
61 return inheritsFrom(child, IC_64BIT_XS);
63 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
65 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
67 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
68 inheritsFrom(child, IC_64BIT_REXW_XD) ||
69 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
71 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
73 return(inheritsFrom(child, IC_64BIT_REXW_XD));
75 return(inheritsFrom(child, IC_64BIT_REXW_XS));
76 case IC_64BIT_XD_OPSIZE:
77 case IC_64BIT_XS_OPSIZE:
79 case IC_64BIT_REXW_XD:
80 case IC_64BIT_REXW_XS:
81 case IC_64BIT_REXW_OPSIZE:
84 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
85 inheritsFrom(child, IC_VEX_W) ||
86 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
88 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
89 inheritsFrom(child, IC_VEX_W_XS) ||
90 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
92 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
93 inheritsFrom(child, IC_VEX_W_XD) ||
94 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
96 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
97 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
98 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
100 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
102 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
104 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
105 case IC_VEX_W_OPSIZE:
106 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
108 return inheritsFrom(child, IC_VEX_L_W);
110 return inheritsFrom(child, IC_VEX_L_W_XS);
112 return inheritsFrom(child, IC_VEX_L_W_XD);
113 case IC_VEX_L_OPSIZE:
114 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
118 case IC_VEX_L_W_OPSIZE:
121 return inheritsFrom(child, IC_EVEX_W) ||
122 inheritsFrom(child, IC_EVEX_L_W);
124 return inheritsFrom(child, IC_EVEX_W_XS) ||
125 inheritsFrom(child, IC_EVEX_L_W_XS);
127 return inheritsFrom(child, IC_EVEX_W_XD) ||
128 inheritsFrom(child, IC_EVEX_L_W_XD);
130 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
131 inheritsFrom(child, IC_EVEX_W_OPSIZE);
135 case IC_EVEX_W_OPSIZE:
140 case IC_EVEX_L_OPSIZE:
145 case IC_EVEX_L_W_OPSIZE:
150 case IC_EVEX_L2_OPSIZE:
153 case IC_EVEX_L2_W_XS:
154 case IC_EVEX_L2_W_XD:
155 case IC_EVEX_L2_W_OPSIZE:
158 return inheritsFrom(child, IC_EVEX_W_K) ||
159 inheritsFrom(child, IC_EVEX_L_W_K);
161 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
162 inheritsFrom(child, IC_EVEX_L_W_XS_K);
164 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
165 inheritsFrom(child, IC_EVEX_L_W_XD_K);
166 case IC_EVEX_OPSIZE_K:
167 return inheritsFrom(child, IC_EVEX_W_OPSIZE_K) ||
168 inheritsFrom(child, IC_EVEX_W_OPSIZE_K);
172 case IC_EVEX_W_OPSIZE_K:
177 case IC_EVEX_L_OPSIZE_K:
180 case IC_EVEX_L_W_XS_K:
181 case IC_EVEX_L_W_XD_K:
182 case IC_EVEX_L_W_OPSIZE_K:
186 case IC_EVEX_L2_XS_K:
187 case IC_EVEX_L2_XD_K:
188 case IC_EVEX_L2_OPSIZE_K:
189 case IC_EVEX_L2_OPSIZE_B:
192 case IC_EVEX_L2_W_XS_K:
193 case IC_EVEX_L2_W_XD_K:
194 case IC_EVEX_L2_W_OPSIZE_K:
195 case IC_EVEX_L2_W_OPSIZE_B:
198 llvm_unreachable("Unknown instruction class");
202 /// outranks - Indicates whether, if an instruction has two different applicable
203 /// classes, which class should be preferred when performing decode. This
204 /// imposes a total ordering (ties are resolved toward "lower")
206 /// @param upper - The class that may be preferable
207 /// @param lower - The class that may be less preferable
208 /// @return - True if upper is to be preferred, false otherwise.
209 static inline bool outranks(InstructionContext upper,
210 InstructionContext lower) {
211 assert(upper < IC_max);
212 assert(lower < IC_max);
214 #define ENUM_ENTRY(n, r, d) r,
215 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
216 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
217 static int ranks[IC_max] = {
221 #undef ENUM_ENTRY_K_B
223 return (ranks[upper] > ranks[lower]);
226 /// stringForContext - Returns a string containing the name of a particular
227 /// InstructionContext, usually for diagnostic purposes.
229 /// @param insnContext - The instruction class to transform to a string.
230 /// @return - A statically-allocated string constant that contains the
231 /// name of the instruction class.
232 static inline const char* stringForContext(InstructionContext insnContext) {
233 switch (insnContext) {
235 llvm_unreachable("Unhandled instruction class");
236 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
237 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
238 ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
241 #undef ENUM_ENTRY_K_B
245 /// stringForOperandType - Like stringForContext, but for OperandTypes.
246 static inline const char* stringForOperandType(OperandType type) {
249 llvm_unreachable("Unhandled type");
250 #define ENUM_ENTRY(i, d) case i: return #i;
256 /// stringForOperandEncoding - like stringForContext, but for
257 /// OperandEncodings.
258 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
261 llvm_unreachable("Unhandled encoding");
262 #define ENUM_ENTRY(i, d) case i: return #i;
268 void DisassemblerTables::emitOneID(raw_ostream &o, unsigned &i, InstrUID id,
269 bool addComma) const {
271 o.indent(i * 2) << format("0x%hx", id);
273 o.indent(i * 2) << 0;
281 o << InstructionSpecifiers[id].name;
287 /// emitEmptyTable - Emits the modRMEmptyTable, which is used as a ID table by
288 /// all ModR/M decisions for instructions that are invalid for all possible
289 /// ModR/M byte values.
291 /// @param o - The output stream on which to emit the table.
292 /// @param i - The indentation level for that output stream.
293 static void emitEmptyTable(raw_ostream &o, unsigned &i) {
294 o.indent(i * 2) << "0x0, /* EmptyTable */\n";
297 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
298 /// be compacted by eliminating redundant information.
300 /// @param decision - The decision to be compacted.
301 /// @return - The compactest available representation for the decision.
302 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
303 bool satisfiesOneEntry = true;
304 bool satisfiesSplitRM = true;
305 bool satisfiesSplitReg = true;
306 bool satisfiesSplitMisc = true;
308 for (unsigned index = 0; index < 256; ++index) {
309 if (decision.instructionIDs[index] != decision.instructionIDs[0])
310 satisfiesOneEntry = false;
312 if (((index & 0xc0) == 0xc0) &&
313 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
314 satisfiesSplitRM = false;
316 if (((index & 0xc0) != 0xc0) &&
317 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
318 satisfiesSplitRM = false;
320 if (((index & 0xc0) == 0xc0) &&
321 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
322 satisfiesSplitReg = false;
324 if (((index & 0xc0) != 0xc0) &&
325 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
326 satisfiesSplitMisc = false;
329 if (satisfiesOneEntry)
330 return MODRM_ONEENTRY;
332 if (satisfiesSplitRM)
333 return MODRM_SPLITRM;
335 if (satisfiesSplitReg && satisfiesSplitMisc)
336 return MODRM_SPLITREG;
338 if (satisfiesSplitMisc)
339 return MODRM_SPLITMISC;
344 /// stringForDecisionType - Returns a statically-allocated string corresponding
345 /// to a particular decision type.
347 /// @param dt - The decision type.
348 /// @return - A pointer to the statically-allocated string (e.g.,
349 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
350 static const char* stringForDecisionType(ModRMDecisionType dt) {
351 #define ENUM_ENTRY(n) case n: return #n;
354 llvm_unreachable("Unknown decision type");
360 /// stringForModifierType - Returns a statically-allocated string corresponding
361 /// to an opcode modifier type.
363 /// @param mt - The modifier type.
364 /// @return - A pointer to the statically-allocated string (e.g.,
365 /// "MODIFIER_NONE" for MODIFIER_NONE).
366 static const char* stringForModifierType(ModifierType mt) {
367 #define ENUM_ENTRY(n) case n: return #n;
370 llvm_unreachable("Unknown modifier type");
376 DisassemblerTables::DisassemblerTables() {
379 for (i = 0; i < array_lengthof(Tables); i++) {
380 Tables[i] = new ContextDecision;
381 memset(Tables[i], 0, sizeof(ContextDecision));
384 HasConflicts = false;
387 DisassemblerTables::~DisassemblerTables() {
390 for (i = 0; i < array_lengthof(Tables); i++)
394 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
395 unsigned &i1, unsigned &i2,
396 ModRMDecision &decision) const {
397 static uint32_t sTableNumber = 0;
398 static uint32_t sEntryNumber = 1;
399 ModRMDecisionType dt = getDecisionType(decision);
401 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
403 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
406 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
407 o2.indent(i2) << 0 << " /* EmptyTable */\n";
410 o2.indent(i2) << "}";
414 o1 << "/* Table" << sTableNumber << " */\n";
419 llvm_unreachable("Unknown decision type");
421 emitOneID(o1, i1, decision.instructionIDs[0], true);
424 emitOneID(o1, i1, decision.instructionIDs[0x00], true); // mod = 0b00
425 emitOneID(o1, i1, decision.instructionIDs[0xc0], true); // mod = 0b11
428 for (unsigned index = 0; index < 64; index += 8)
429 emitOneID(o1, i1, decision.instructionIDs[index], true);
430 for (unsigned index = 0xc0; index < 256; index += 8)
431 emitOneID(o1, i1, decision.instructionIDs[index], true);
433 case MODRM_SPLITMISC:
434 for (unsigned index = 0; index < 64; index += 8)
435 emitOneID(o1, i1, decision.instructionIDs[index], true);
436 for (unsigned index = 0xc0; index < 256; ++index)
437 emitOneID(o1, i1, decision.instructionIDs[index], true);
440 for (unsigned index = 0; index < 256; ++index)
441 emitOneID(o1, i1, decision.instructionIDs[index], true);
447 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
450 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
451 o2.indent(i2) << sEntryNumber << " /* Table" << sTableNumber << " */\n";
454 o2.indent(i2) << "}";
458 llvm_unreachable("Unknown decision type");
468 case MODRM_SPLITMISC:
469 sEntryNumber += 8 + 64;
476 // We assume that the index can fit into uint16_t.
477 assert(sEntryNumber < 65536U &&
478 "Index into ModRMDecision is too large for uint16_t!");
483 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
484 unsigned &i1, unsigned &i2,
485 OpcodeDecision &decision) const {
486 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
488 o2.indent(i2) << "{" << "\n";
491 for (unsigned index = 0; index < 256; ++index) {
494 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
496 emitModRMDecision(o1, o2, i1, i2, decision.modRMDecisions[index]);
505 o2.indent(i2) << "}" << "\n";
507 o2.indent(i2) << "}" << "\n";
510 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
511 unsigned &i1, unsigned &i2,
512 ContextDecision &decision,
513 const char* name) const {
514 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
516 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
519 for (unsigned index = 0; index < IC_max; ++index) {
520 o2.indent(i2) << "/* ";
521 o2 << stringForContext((InstructionContext)index);
525 emitOpcodeDecision(o1, o2, i1, i2, decision.opcodeDecisions[index]);
527 if (index + 1 < IC_max)
532 o2.indent(i2) << "}" << "\n";
534 o2.indent(i2) << "};" << "\n";
537 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
539 unsigned NumInstructions = InstructionSpecifiers.size();
541 o << "static const struct OperandSpecifier x86OperandSets[]["
542 << X86_MAX_OPERANDS << "] = {\n";
544 typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
545 std::map<OperandListTy, unsigned> OperandSets;
547 unsigned OperandSetNum = 0;
548 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
549 OperandListTy OperandList;
551 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
553 const char *Encoding =
554 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
555 .operands[OperandIndex].encoding);
557 stringForOperandType((OperandType)InstructionSpecifiers[Index]
558 .operands[OperandIndex].type);
559 OperandList.push_back(std::make_pair(Encoding, Type));
561 unsigned &N = OperandSets[OperandList];
562 if (N != 0) continue;
566 o << " { /* " << (OperandSetNum - 1) << " */\n";
567 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
568 o << " { " << OperandList[i].first << ", "
569 << OperandList[i].second << " },\n";
575 o.indent(i * 2) << "static const struct InstructionSpecifier ";
576 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
580 for (unsigned index = 0; index < NumInstructions; ++index) {
581 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
584 o.indent(i * 2) << stringForModifierType(
585 (ModifierType)InstructionSpecifiers[index].modifierType);
588 o.indent(i * 2) << "0x";
589 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
592 OperandListTy OperandList;
593 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
595 const char *Encoding =
596 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
597 .operands[OperandIndex].encoding);
599 stringForOperandType((OperandType)InstructionSpecifiers[index]
600 .operands[OperandIndex].type);
601 OperandList.push_back(std::make_pair(Encoding, Type));
603 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
605 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
609 o.indent(i * 2) << "}";
611 if (index + 1 < NumInstructions)
618 o.indent(i * 2) << "};" << "\n";
621 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
622 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
626 for (unsigned index = 0; index < 256; ++index) {
629 if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
630 o << "IC_VEX_L_W_OPSIZE";
631 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
632 o << "IC_VEX_L_W_XD";
633 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
634 o << "IC_VEX_L_W_XS";
635 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
637 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
638 o << "IC_VEX_L_OPSIZE";
639 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
641 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
643 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
644 o << "IC_VEX_W_OPSIZE";
645 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
647 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
649 else if (index & ATTR_VEXL)
651 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
653 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
654 o << "IC_VEX_OPSIZE";
655 else if ((index & ATTR_VEX) && (index & ATTR_XD))
657 else if ((index & ATTR_VEX) && (index & ATTR_XS))
659 else if (index & ATTR_VEX)
661 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
662 o << "IC_64BIT_REXW_XS";
663 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
664 o << "IC_64BIT_REXW_XD";
665 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
666 (index & ATTR_OPSIZE))
667 o << "IC_64BIT_REXW_OPSIZE";
668 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
669 o << "IC_64BIT_XD_OPSIZE";
670 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
671 o << "IC_64BIT_XS_OPSIZE";
672 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
674 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
676 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
677 o << "IC_64BIT_OPSIZE";
678 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
679 o << "IC_64BIT_ADSIZE";
680 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
681 o << "IC_64BIT_REXW";
682 else if ((index & ATTR_64BIT))
684 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
686 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
688 else if (index & ATTR_XS)
690 else if (index & ATTR_XD)
692 else if (index & ATTR_OPSIZE)
694 else if (index & ATTR_ADSIZE)
704 o << " /* " << index << " */";
710 o.indent(i * 2) << "};" << "\n";
713 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
714 unsigned &i1, unsigned &i2) const {
715 emitContextDecision(o1, o2, i1, i2, *Tables[0], ONEBYTE_STR);
716 emitContextDecision(o1, o2, i1, i2, *Tables[1], TWOBYTE_STR);
717 emitContextDecision(o1, o2, i1, i2, *Tables[2], THREEBYTE38_STR);
718 emitContextDecision(o1, o2, i1, i2, *Tables[3], THREEBYTE3A_STR);
719 emitContextDecision(o1, o2, i1, i2, *Tables[4], THREEBYTEA6_STR);
720 emitContextDecision(o1, o2, i1, i2, *Tables[5], THREEBYTEA7_STR);
723 void DisassemblerTables::emit(raw_ostream &o) const {
730 raw_string_ostream o1(s1);
731 raw_string_ostream o2(s2);
733 emitInstructionInfo(o, i2);
736 emitContextTable(o, i2);
739 o << "static const InstrUID modRMTable[] = {\n";
741 emitEmptyTable(o1, i1);
743 emitContextDecisions(o1, o2, i1, i2);
754 void DisassemblerTables::setTableFields(ModRMDecision &decision,
755 const ModRMFilter &filter,
758 for (unsigned index = 0; index < 256; ++index) {
759 if (filter.accepts(index)) {
760 if (decision.instructionIDs[index] == uid)
763 if (decision.instructionIDs[index] != 0) {
764 InstructionSpecifier &newInfo =
765 InstructionSpecifiers[uid];
766 InstructionSpecifier &previousInfo =
767 InstructionSpecifiers[decision.instructionIDs[index]];
770 continue; // filtered instructions get lowest priority
772 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
773 newInfo.name == "XCHG32ar" ||
774 newInfo.name == "XCHG32ar64" ||
775 newInfo.name == "XCHG64ar"))
776 continue; // special case for XCHG*ar and NOOP
778 if (outranks(previousInfo.insnContext, newInfo.insnContext))
781 if (previousInfo.insnContext == newInfo.insnContext &&
782 !previousInfo.filtered) {
783 errs() << "Error: Primary decode conflict: ";
784 errs() << newInfo.name << " would overwrite " << previousInfo.name;
786 errs() << "ModRM " << index << "\n";
787 errs() << "Opcode " << (uint16_t)opcode << "\n";
788 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
793 decision.instructionIDs[index] = uid;
798 void DisassemblerTables::setTableFields(OpcodeType type,
799 InstructionContext insnContext,
801 const ModRMFilter &filter,
805 ContextDecision &decision = *Tables[type];
807 for (unsigned index = 0; index < IC_max; ++index) {
808 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
811 if (inheritsFrom((InstructionContext)index,
812 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
813 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],