1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
25 using namespace X86Disassembler;
27 /// stringForContext - Returns a string containing the name of a particular
28 /// InstructionContext, usually for diagnostic purposes.
30 /// @param insnContext - The instruction class to transform to a string.
31 /// @return - A statically-allocated string constant that contains the
32 /// name of the instruction class.
33 static inline const char* stringForContext(InstructionContext insnContext) {
34 switch (insnContext) {
36 llvm_unreachable("Unhandled instruction class");
37 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
38 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
40 ENUM_ENTRY(n##_KZ_B, r, d)
47 /// stringForOperandType - Like stringForContext, but for OperandTypes.
48 static inline const char* stringForOperandType(OperandType type) {
51 llvm_unreachable("Unhandled type");
52 #define ENUM_ENTRY(i, d) case i: return #i;
58 /// stringForOperandEncoding - like stringForContext, but for
60 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
63 llvm_unreachable("Unhandled encoding");
64 #define ENUM_ENTRY(i, d) case i: return #i;
70 /// inheritsFrom - Indicates whether all instructions in one class also belong
73 /// @param child - The class that may be the subset
74 /// @param parent - The class that may be the superset
75 /// @return - True if child is a subset of parent, false otherwise.
76 static inline bool inheritsFrom(InstructionContext child,
77 InstructionContext parent,
78 bool VEX_LIG = false) {
84 return(inheritsFrom(child, IC_64BIT) ||
85 inheritsFrom(child, IC_OPSIZE) ||
86 inheritsFrom(child, IC_ADSIZE) ||
87 inheritsFrom(child, IC_XD) ||
88 inheritsFrom(child, IC_XS));
90 return(inheritsFrom(child, IC_64BIT_REXW) ||
91 inheritsFrom(child, IC_64BIT_OPSIZE) ||
92 inheritsFrom(child, IC_64BIT_ADSIZE) ||
93 inheritsFrom(child, IC_64BIT_XD) ||
94 inheritsFrom(child, IC_64BIT_XS));
96 return inheritsFrom(child, IC_64BIT_OPSIZE);
101 return inheritsFrom(child, IC_64BIT_XD);
103 return inheritsFrom(child, IC_64BIT_XS);
105 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
107 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
109 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
110 inheritsFrom(child, IC_64BIT_REXW_XD) ||
111 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
112 case IC_64BIT_OPSIZE:
113 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
115 return(inheritsFrom(child, IC_64BIT_REXW_XD));
117 return(inheritsFrom(child, IC_64BIT_REXW_XS));
118 case IC_64BIT_XD_OPSIZE:
119 case IC_64BIT_XS_OPSIZE:
121 case IC_64BIT_REXW_XD:
122 case IC_64BIT_REXW_XS:
123 case IC_64BIT_REXW_OPSIZE:
126 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
127 inheritsFrom(child, IC_VEX_W) ||
128 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
130 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
131 inheritsFrom(child, IC_VEX_W_XS) ||
132 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
134 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
135 inheritsFrom(child, IC_VEX_W_XD) ||
136 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
138 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
139 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
140 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
142 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
144 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
146 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
147 case IC_VEX_W_OPSIZE:
148 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
150 return inheritsFrom(child, IC_VEX_L_W);
152 return inheritsFrom(child, IC_VEX_L_W_XS);
154 return inheritsFrom(child, IC_VEX_L_W_XD);
155 case IC_VEX_L_OPSIZE:
156 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
160 case IC_VEX_L_W_OPSIZE:
163 return inheritsFrom(child, IC_EVEX_W) ||
164 inheritsFrom(child, IC_EVEX_L_W);
166 return inheritsFrom(child, IC_EVEX_W_XS) ||
167 inheritsFrom(child, IC_EVEX_L_W_XS);
169 return inheritsFrom(child, IC_EVEX_W_XD) ||
170 inheritsFrom(child, IC_EVEX_L_W_XD);
172 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
173 inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
177 case IC_EVEX_W_OPSIZE:
182 case IC_EVEX_L_OPSIZE:
187 case IC_EVEX_L_W_OPSIZE:
192 case IC_EVEX_L2_OPSIZE:
195 case IC_EVEX_L2_W_XS:
196 case IC_EVEX_L2_W_XD:
197 case IC_EVEX_L2_W_OPSIZE:
200 return inheritsFrom(child, IC_EVEX_W_K) ||
201 inheritsFrom(child, IC_EVEX_L_W_K);
203 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
204 inheritsFrom(child, IC_EVEX_L_W_XS_K);
206 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
207 inheritsFrom(child, IC_EVEX_L_W_XD_K);
212 return inheritsFrom(child, IC_EVEX_W_XS_KZ) ||
213 inheritsFrom(child, IC_EVEX_L_W_XS_KZ);
215 return inheritsFrom(child, IC_EVEX_W_XD_KZ) ||
216 inheritsFrom(child, IC_EVEX_L_W_XD_KZ);
218 case IC_EVEX_OPSIZE_K:
219 case IC_EVEX_OPSIZE_B:
220 case IC_EVEX_OPSIZE_K_B:
221 case IC_EVEX_OPSIZE_KZ:
222 case IC_EVEX_OPSIZE_KZ_B:
227 case IC_EVEX_W_OPSIZE_K:
228 case IC_EVEX_W_OPSIZE_B:
229 case IC_EVEX_W_OPSIZE_K_B:
234 case IC_EVEX_L_OPSIZE_K:
235 case IC_EVEX_L_OPSIZE_B:
236 case IC_EVEX_L_OPSIZE_K_B:
239 case IC_EVEX_W_XS_KZ:
240 case IC_EVEX_W_XD_KZ:
241 case IC_EVEX_W_OPSIZE_KZ:
242 case IC_EVEX_W_OPSIZE_KZ_B:
245 case IC_EVEX_L_XS_KZ:
246 case IC_EVEX_L_XD_KZ:
247 case IC_EVEX_L_OPSIZE_KZ:
248 case IC_EVEX_L_OPSIZE_KZ_B:
251 case IC_EVEX_L_W_XS_K:
252 case IC_EVEX_L_W_XD_K:
253 case IC_EVEX_L_W_OPSIZE_K:
254 case IC_EVEX_L_W_OPSIZE_B:
255 case IC_EVEX_L_W_OPSIZE_K_B:
257 case IC_EVEX_L_W_XS_KZ:
258 case IC_EVEX_L_W_XD_KZ:
259 case IC_EVEX_L_W_OPSIZE_KZ:
260 case IC_EVEX_L_W_OPSIZE_KZ_B:
265 case IC_EVEX_L2_KZ_B:
266 case IC_EVEX_L2_XS_K:
267 case IC_EVEX_L2_XS_B:
268 case IC_EVEX_L2_XD_B:
269 case IC_EVEX_L2_XD_K:
270 case IC_EVEX_L2_OPSIZE_K:
271 case IC_EVEX_L2_OPSIZE_B:
272 case IC_EVEX_L2_OPSIZE_K_B:
274 case IC_EVEX_L2_XS_KZ:
275 case IC_EVEX_L2_XD_KZ:
276 case IC_EVEX_L2_OPSIZE_KZ:
277 case IC_EVEX_L2_OPSIZE_KZ_B:
281 case IC_EVEX_L2_W_XS_K:
282 case IC_EVEX_L2_W_XD_K:
283 case IC_EVEX_L2_W_XD_B:
284 case IC_EVEX_L2_W_OPSIZE_K:
285 case IC_EVEX_L2_W_OPSIZE_B:
286 case IC_EVEX_L2_W_OPSIZE_K_B:
287 case IC_EVEX_L2_W_KZ:
288 case IC_EVEX_L2_W_XS_KZ:
289 case IC_EVEX_L2_W_XD_KZ:
290 case IC_EVEX_L2_W_OPSIZE_KZ:
291 case IC_EVEX_L2_W_OPSIZE_KZ_B:
294 errs() << "Unknown instruction class: " <<
295 stringForContext((InstructionContext)parent) << "\n";
296 llvm_unreachable("Unknown instruction class");
300 /// outranks - Indicates whether, if an instruction has two different applicable
301 /// classes, which class should be preferred when performing decode. This
302 /// imposes a total ordering (ties are resolved toward "lower")
304 /// @param upper - The class that may be preferable
305 /// @param lower - The class that may be less preferable
306 /// @return - True if upper is to be preferred, false otherwise.
307 static inline bool outranks(InstructionContext upper,
308 InstructionContext lower) {
309 assert(upper < IC_max);
310 assert(lower < IC_max);
312 #define ENUM_ENTRY(n, r, d) r,
313 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
314 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \
315 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
316 static int ranks[IC_max] = {
320 #undef ENUM_ENTRY_K_B
322 return (ranks[upper] > ranks[lower]);
325 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
326 /// be compacted by eliminating redundant information.
328 /// @param decision - The decision to be compacted.
329 /// @return - The compactest available representation for the decision.
330 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
331 bool satisfiesOneEntry = true;
332 bool satisfiesSplitRM = true;
333 bool satisfiesSplitReg = true;
334 bool satisfiesSplitMisc = true;
336 for (unsigned index = 0; index < 256; ++index) {
337 if (decision.instructionIDs[index] != decision.instructionIDs[0])
338 satisfiesOneEntry = false;
340 if (((index & 0xc0) == 0xc0) &&
341 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
342 satisfiesSplitRM = false;
344 if (((index & 0xc0) != 0xc0) &&
345 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
346 satisfiesSplitRM = false;
348 if (((index & 0xc0) == 0xc0) &&
349 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
350 satisfiesSplitReg = false;
352 if (((index & 0xc0) != 0xc0) &&
353 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
354 satisfiesSplitMisc = false;
357 if (satisfiesOneEntry)
358 return MODRM_ONEENTRY;
360 if (satisfiesSplitRM)
361 return MODRM_SPLITRM;
363 if (satisfiesSplitReg && satisfiesSplitMisc)
364 return MODRM_SPLITREG;
366 if (satisfiesSplitMisc)
367 return MODRM_SPLITMISC;
372 /// stringForDecisionType - Returns a statically-allocated string corresponding
373 /// to a particular decision type.
375 /// @param dt - The decision type.
376 /// @return - A pointer to the statically-allocated string (e.g.,
377 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
378 static const char* stringForDecisionType(ModRMDecisionType dt) {
379 #define ENUM_ENTRY(n) case n: return #n;
382 llvm_unreachable("Unknown decision type");
388 DisassemblerTables::DisassemblerTables() {
391 for (i = 0; i < array_lengthof(Tables); i++) {
392 Tables[i] = new ContextDecision;
393 memset(Tables[i], 0, sizeof(ContextDecision));
396 HasConflicts = false;
399 DisassemblerTables::~DisassemblerTables() {
402 for (i = 0; i < array_lengthof(Tables); i++)
406 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
407 unsigned &i1, unsigned &i2,
408 unsigned &ModRMTableNum,
409 ModRMDecision &decision) const {
410 static uint32_t sTableNumber = 0;
411 static uint32_t sEntryNumber = 1;
412 ModRMDecisionType dt = getDecisionType(decision);
414 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
416 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
419 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
420 o2.indent(i2) << 0 << " /* EmptyTable */\n";
423 o2.indent(i2) << "}";
427 std::vector<unsigned> ModRMDecision;
431 llvm_unreachable("Unknown decision type");
433 ModRMDecision.push_back(decision.instructionIDs[0]);
436 ModRMDecision.push_back(decision.instructionIDs[0x00]);
437 ModRMDecision.push_back(decision.instructionIDs[0xc0]);
440 for (unsigned index = 0; index < 64; index += 8)
441 ModRMDecision.push_back(decision.instructionIDs[index]);
442 for (unsigned index = 0xc0; index < 256; index += 8)
443 ModRMDecision.push_back(decision.instructionIDs[index]);
445 case MODRM_SPLITMISC:
446 for (unsigned index = 0; index < 64; index += 8)
447 ModRMDecision.push_back(decision.instructionIDs[index]);
448 for (unsigned index = 0xc0; index < 256; ++index)
449 ModRMDecision.push_back(decision.instructionIDs[index]);
452 for (unsigned index = 0; index < 256; ++index)
453 ModRMDecision.push_back(decision.instructionIDs[index]);
457 unsigned &EntryNumber = ModRMTable[ModRMDecision];
458 if (EntryNumber == 0) {
459 EntryNumber = ModRMTableNum;
461 ModRMTableNum += ModRMDecision.size();
462 o1 << "/* Table" << EntryNumber << " */\n";
464 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
465 E = ModRMDecision.end(); I != E; ++I) {
466 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* "
467 << InstructionSpecifiers[*I].name << " */\n";
472 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
475 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
476 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n";
479 o2.indent(i2) << "}";
483 llvm_unreachable("Unknown decision type");
493 case MODRM_SPLITMISC:
494 sEntryNumber += 8 + 64;
501 // We assume that the index can fit into uint16_t.
502 assert(sEntryNumber < 65536U &&
503 "Index into ModRMDecision is too large for uint16_t!");
508 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
509 unsigned &i1, unsigned &i2,
510 unsigned &ModRMTableNum,
511 OpcodeDecision &decision) const {
512 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
514 o2.indent(i2) << "{" << "\n";
517 for (unsigned index = 0; index < 256; ++index) {
520 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
522 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
523 decision.modRMDecisions[index]);
532 o2.indent(i2) << "}" << "\n";
534 o2.indent(i2) << "}" << "\n";
537 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
538 unsigned &i1, unsigned &i2,
539 unsigned &ModRMTableNum,
540 ContextDecision &decision,
541 const char* name) const {
542 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
544 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
547 for (unsigned index = 0; index < IC_max; ++index) {
548 o2.indent(i2) << "/* ";
549 o2 << stringForContext((InstructionContext)index);
553 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
554 decision.opcodeDecisions[index]);
556 if (index + 1 < IC_max)
561 o2.indent(i2) << "}" << "\n";
563 o2.indent(i2) << "};" << "\n";
566 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
568 unsigned NumInstructions = InstructionSpecifiers.size();
570 o << "static const struct OperandSpecifier x86OperandSets[]["
571 << X86_MAX_OPERANDS << "] = {\n";
573 typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
574 std::map<OperandListTy, unsigned> OperandSets;
576 unsigned OperandSetNum = 0;
577 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
578 OperandListTy OperandList;
580 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
582 const char *Encoding =
583 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
584 .operands[OperandIndex].encoding);
586 stringForOperandType((OperandType)InstructionSpecifiers[Index]
587 .operands[OperandIndex].type);
588 OperandList.push_back(std::make_pair(Encoding, Type));
590 unsigned &N = OperandSets[OperandList];
591 if (N != 0) continue;
595 o << " { /* " << (OperandSetNum - 1) << " */\n";
596 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
597 o << " { " << OperandList[i].first << ", "
598 << OperandList[i].second << " },\n";
604 o.indent(i * 2) << "static const struct InstructionSpecifier ";
605 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
609 for (unsigned index = 0; index < NumInstructions; ++index) {
610 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
613 OperandListTy OperandList;
614 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
616 const char *Encoding =
617 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
618 .operands[OperandIndex].encoding);
620 stringForOperandType((OperandType)InstructionSpecifiers[index]
621 .operands[OperandIndex].type);
622 OperandList.push_back(std::make_pair(Encoding, Type));
624 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
626 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
630 o.indent(i * 2) << "}";
632 if (index + 1 < NumInstructions)
639 o.indent(i * 2) << "};" << "\n";
642 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
643 const unsigned int tableSize = 16384;
644 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
645 "[" << tableSize << "] = {\n";
648 for (unsigned index = 0; index < tableSize; ++index) {
651 if (index & ATTR_EVEX) {
653 if (index & ATTR_EVEXL2)
655 else if (index & ATTR_EVEXL)
657 if (index & ATTR_REXW)
659 if (index & ATTR_OPSIZE)
661 else if (index & ATTR_XD)
663 else if (index & ATTR_XS)
665 if (index & ATTR_EVEXKZ)
667 else if (index & ATTR_EVEXK)
669 if (index & ATTR_EVEXB)
672 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
673 o << "IC_VEX_L_W_OPSIZE";
674 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
675 o << "IC_VEX_L_W_XD";
676 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
677 o << "IC_VEX_L_W_XS";
678 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
680 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
681 o << "IC_VEX_L_OPSIZE";
682 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
684 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
686 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
687 o << "IC_VEX_W_OPSIZE";
688 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
690 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
692 else if (index & ATTR_VEXL)
694 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
696 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
697 o << "IC_VEX_OPSIZE";
698 else if ((index & ATTR_VEX) && (index & ATTR_XD))
700 else if ((index & ATTR_VEX) && (index & ATTR_XS))
702 else if (index & ATTR_VEX)
704 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
705 o << "IC_64BIT_REXW_XS";
706 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
707 o << "IC_64BIT_REXW_XD";
708 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
709 (index & ATTR_OPSIZE))
710 o << "IC_64BIT_REXW_OPSIZE";
711 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
712 o << "IC_64BIT_XD_OPSIZE";
713 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
714 o << "IC_64BIT_XS_OPSIZE";
715 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
717 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
719 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
720 o << "IC_64BIT_OPSIZE";
721 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
722 o << "IC_64BIT_ADSIZE";
723 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
724 o << "IC_64BIT_REXW";
725 else if ((index & ATTR_64BIT))
727 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
729 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
731 else if (index & ATTR_XS)
733 else if (index & ATTR_XD)
735 else if (index & ATTR_OPSIZE)
737 else if (index & ATTR_ADSIZE)
742 if (index < tableSize - 1)
747 o << " /* " << index << " */";
753 o.indent(i * 2) << "};" << "\n";
756 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
757 unsigned &i1, unsigned &i2,
758 unsigned &ModRMTableNum) const {
759 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
760 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
761 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
762 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
763 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR);
764 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR);
765 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR);
768 void DisassemblerTables::emit(raw_ostream &o) const {
775 raw_string_ostream o1(s1);
776 raw_string_ostream o2(s2);
778 emitInstructionInfo(o, i2);
781 emitContextTable(o, i2);
784 unsigned ModRMTableNum = 0;
786 o << "static const InstrUID modRMTable[] = {\n";
788 std::vector<unsigned> EmptyTable(1, 0);
789 ModRMTable[EmptyTable] = ModRMTableNum;
790 ModRMTableNum += EmptyTable.size();
791 o1 << "/* EmptyTable */\n";
792 o1.indent(i1 * 2) << "0x0,\n";
794 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
805 void DisassemblerTables::setTableFields(ModRMDecision &decision,
806 const ModRMFilter &filter,
809 for (unsigned index = 0; index < 256; ++index) {
810 if (filter.accepts(index)) {
811 if (decision.instructionIDs[index] == uid)
814 if (decision.instructionIDs[index] != 0) {
815 InstructionSpecifier &newInfo =
816 InstructionSpecifiers[uid];
817 InstructionSpecifier &previousInfo =
818 InstructionSpecifiers[decision.instructionIDs[index]];
820 // Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the
821 // presence of the AdSize prefix. However, the disassembler doesn't
822 // care about that difference in the instruction definition; it
823 // handles 16-bit vs. 32-bit addressing for itself based purely
824 // on the 0x67 prefix and the CPU mode. So there's no need to
825 // disambiguate between them; just let them conflict/coexist.
826 if (previousInfo.name + "_16" == newInfo.name)
829 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
830 newInfo.name == "XCHG32ar" ||
831 newInfo.name == "XCHG32ar64" ||
832 newInfo.name == "XCHG64ar"))
833 continue; // special case for XCHG*ar and NOOP
835 if (outranks(previousInfo.insnContext, newInfo.insnContext))
838 if (previousInfo.insnContext == newInfo.insnContext) {
839 errs() << "Error: Primary decode conflict: ";
840 errs() << newInfo.name << " would overwrite " << previousInfo.name;
842 errs() << "ModRM " << index << "\n";
843 errs() << "Opcode " << (uint16_t)opcode << "\n";
844 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
849 decision.instructionIDs[index] = uid;
854 void DisassemblerTables::setTableFields(OpcodeType type,
855 InstructionContext insnContext,
857 const ModRMFilter &filter,
861 ContextDecision &decision = *Tables[type];
863 for (unsigned index = 0; index < IC_max; ++index) {
864 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
867 if (inheritsFrom((InstructionContext)index,
868 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
869 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],