1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
25 using namespace X86Disassembler;
27 /// stringForContext - Returns a string containing the name of a particular
28 /// InstructionContext, usually for diagnostic purposes.
30 /// @param insnContext - The instruction class to transform to a string.
31 /// @return - A statically-allocated string constant that contains the
32 /// name of the instruction class.
33 static inline const char* stringForContext(InstructionContext insnContext) {
34 switch (insnContext) {
36 llvm_unreachable("Unhandled instruction class");
37 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
38 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
40 ENUM_ENTRY(n##_KZ_B, r, d)
47 /// stringForOperandType - Like stringForContext, but for OperandTypes.
48 static inline const char* stringForOperandType(OperandType type) {
51 llvm_unreachable("Unhandled type");
52 #define ENUM_ENTRY(i, d) case i: return #i;
58 /// stringForOperandEncoding - like stringForContext, but for
60 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
63 llvm_unreachable("Unhandled encoding");
64 #define ENUM_ENTRY(i, d) case i: return #i;
70 /// inheritsFrom - Indicates whether all instructions in one class also belong
73 /// @param child - The class that may be the subset
74 /// @param parent - The class that may be the superset
75 /// @return - True if child is a subset of parent, false otherwise.
76 static inline bool inheritsFrom(InstructionContext child,
77 InstructionContext parent,
78 bool VEX_LIG = false, bool AdSize64 = false) {
84 return(inheritsFrom(child, IC_64BIT, AdSize64) ||
85 inheritsFrom(child, IC_OPSIZE) ||
86 inheritsFrom(child, IC_ADSIZE) ||
87 inheritsFrom(child, IC_XD) ||
88 inheritsFrom(child, IC_XS));
90 return(inheritsFrom(child, IC_64BIT_REXW) ||
91 inheritsFrom(child, IC_64BIT_OPSIZE) ||
92 (!AdSize64 && inheritsFrom(child, IC_64BIT_ADSIZE)) ||
93 inheritsFrom(child, IC_64BIT_XD) ||
94 inheritsFrom(child, IC_64BIT_XS));
96 return inheritsFrom(child, IC_64BIT_OPSIZE) ||
97 inheritsFrom(child, IC_OPSIZE_ADSIZE);
99 return inheritsFrom(child, IC_OPSIZE_ADSIZE);
100 case IC_OPSIZE_ADSIZE:
102 case IC_64BIT_ADSIZE:
103 return inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE);
104 case IC_64BIT_OPSIZE_ADSIZE:
107 return inheritsFrom(child, IC_64BIT_XD);
109 return inheritsFrom(child, IC_64BIT_XS);
111 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
113 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
115 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
116 inheritsFrom(child, IC_64BIT_REXW_XD) ||
117 inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
118 (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE)));
119 case IC_64BIT_OPSIZE:
120 return inheritsFrom(child, IC_64BIT_REXW_OPSIZE) ||
121 (!AdSize64 && inheritsFrom(child, IC_64BIT_OPSIZE_ADSIZE)) ||
122 (!AdSize64 && inheritsFrom(child, IC_64BIT_REXW_ADSIZE));
124 return(inheritsFrom(child, IC_64BIT_REXW_XD));
126 return(inheritsFrom(child, IC_64BIT_REXW_XS));
127 case IC_64BIT_XD_OPSIZE:
128 case IC_64BIT_XS_OPSIZE:
130 case IC_64BIT_REXW_XD:
131 case IC_64BIT_REXW_XS:
132 case IC_64BIT_REXW_OPSIZE:
133 case IC_64BIT_REXW_ADSIZE:
136 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
137 inheritsFrom(child, IC_VEX_W) ||
138 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
140 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
141 inheritsFrom(child, IC_VEX_W_XS) ||
142 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
144 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
145 inheritsFrom(child, IC_VEX_W_XD) ||
146 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
148 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
149 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
150 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
152 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
154 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
156 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
157 case IC_VEX_W_OPSIZE:
158 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
160 return inheritsFrom(child, IC_VEX_L_W);
162 return inheritsFrom(child, IC_VEX_L_W_XS);
164 return inheritsFrom(child, IC_VEX_L_W_XD);
165 case IC_VEX_L_OPSIZE:
166 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
170 case IC_VEX_L_W_OPSIZE:
173 return inheritsFrom(child, IC_EVEX_W) ||
174 inheritsFrom(child, IC_EVEX_L_W);
176 return inheritsFrom(child, IC_EVEX_W_XS) ||
177 inheritsFrom(child, IC_EVEX_L_W_XS);
179 return inheritsFrom(child, IC_EVEX_W_XD) ||
180 inheritsFrom(child, IC_EVEX_L_W_XD);
182 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
183 inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
189 case IC_EVEX_W_OPSIZE:
197 case IC_EVEX_L_OPSIZE:
202 case IC_EVEX_L_W_OPSIZE:
207 case IC_EVEX_L2_OPSIZE:
210 case IC_EVEX_L2_W_XS:
211 case IC_EVEX_L2_W_XD:
212 case IC_EVEX_L2_W_OPSIZE:
215 return inheritsFrom(child, IC_EVEX_W_K) ||
216 inheritsFrom(child, IC_EVEX_L_W_K);
219 case IC_EVEX_XS_KZ_B:
220 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
221 inheritsFrom(child, IC_EVEX_L_W_XS_K);
224 case IC_EVEX_XD_KZ_B:
225 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
226 inheritsFrom(child, IC_EVEX_L_W_XD_K);
233 return inheritsFrom(child, IC_EVEX_W_XS_KZ) ||
234 inheritsFrom(child, IC_EVEX_L_W_XS_KZ);
236 return inheritsFrom(child, IC_EVEX_W_XD_KZ) ||
237 inheritsFrom(child, IC_EVEX_L_W_XD_KZ);
239 case IC_EVEX_OPSIZE_K:
240 case IC_EVEX_OPSIZE_B:
241 case IC_EVEX_OPSIZE_K_B:
242 case IC_EVEX_OPSIZE_KZ:
243 case IC_EVEX_OPSIZE_KZ_B:
248 case IC_EVEX_W_OPSIZE_K:
249 case IC_EVEX_W_OPSIZE_B:
250 case IC_EVEX_W_OPSIZE_K_B:
255 case IC_EVEX_L_OPSIZE_K:
256 case IC_EVEX_L_OPSIZE_B:
257 case IC_EVEX_L_OPSIZE_K_B:
260 case IC_EVEX_W_XS_KZ:
261 case IC_EVEX_W_XD_KZ:
264 case IC_EVEX_W_XS_K_B:
265 case IC_EVEX_W_XD_K_B:
266 case IC_EVEX_W_XS_KZ_B:
267 case IC_EVEX_W_XD_KZ_B:
268 case IC_EVEX_W_OPSIZE_KZ:
269 case IC_EVEX_W_OPSIZE_KZ_B:
272 case IC_EVEX_L_XS_KZ:
274 case IC_EVEX_L_XS_K_B:
275 case IC_EVEX_L_XD_KZ:
276 case IC_EVEX_L_OPSIZE_KZ:
277 case IC_EVEX_L_OPSIZE_KZ_B:
280 case IC_EVEX_L_W_XS_K:
281 case IC_EVEX_L_W_XS_B:
282 case IC_EVEX_L_W_XS_K_B:
283 case IC_EVEX_L_W_XD_K:
284 case IC_EVEX_L_W_OPSIZE_K:
285 case IC_EVEX_L_W_OPSIZE_B:
286 case IC_EVEX_L_W_OPSIZE_K_B:
288 case IC_EVEX_L_W_XS_KZ:
289 case IC_EVEX_L_W_XD_KZ:
290 case IC_EVEX_L_W_OPSIZE_KZ:
291 case IC_EVEX_L_W_OPSIZE_KZ_B:
296 case IC_EVEX_L2_KZ_B:
297 case IC_EVEX_L2_XS_K:
298 case IC_EVEX_L2_XS_K_B:
299 case IC_EVEX_L2_XS_B:
300 case IC_EVEX_L2_XD_B:
301 case IC_EVEX_L2_XD_K:
302 case IC_EVEX_L2_OPSIZE_K:
303 case IC_EVEX_L2_OPSIZE_B:
304 case IC_EVEX_L2_OPSIZE_K_B:
306 case IC_EVEX_L2_XS_KZ:
307 case IC_EVEX_L2_XD_KZ:
308 case IC_EVEX_L2_OPSIZE_KZ:
309 case IC_EVEX_L2_OPSIZE_KZ_B:
313 case IC_EVEX_L2_W_XS_K:
314 case IC_EVEX_L2_W_XS_B:
315 case IC_EVEX_L2_W_XS_K_B:
316 case IC_EVEX_L2_W_XD_K:
317 case IC_EVEX_L2_W_XD_B:
318 case IC_EVEX_L2_W_OPSIZE_K:
319 case IC_EVEX_L2_W_OPSIZE_B:
320 case IC_EVEX_L2_W_OPSIZE_K_B:
321 case IC_EVEX_L2_W_KZ:
322 case IC_EVEX_L2_W_XS_KZ:
323 case IC_EVEX_L2_W_XD_KZ:
324 case IC_EVEX_L2_W_OPSIZE_KZ:
325 case IC_EVEX_L2_W_OPSIZE_KZ_B:
328 errs() << "Unknown instruction class: " <<
329 stringForContext((InstructionContext)parent) << "\n";
330 llvm_unreachable("Unknown instruction class");
334 /// outranks - Indicates whether, if an instruction has two different applicable
335 /// classes, which class should be preferred when performing decode. This
336 /// imposes a total ordering (ties are resolved toward "lower")
338 /// @param upper - The class that may be preferable
339 /// @param lower - The class that may be less preferable
340 /// @return - True if upper is to be preferred, false otherwise.
341 static inline bool outranks(InstructionContext upper,
342 InstructionContext lower) {
343 assert(upper < IC_max);
344 assert(lower < IC_max);
346 #define ENUM_ENTRY(n, r, d) r,
347 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
348 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \
349 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
350 static int ranks[IC_max] = {
354 #undef ENUM_ENTRY_K_B
356 return (ranks[upper] > ranks[lower]);
359 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
360 /// be compacted by eliminating redundant information.
362 /// @param decision - The decision to be compacted.
363 /// @return - The compactest available representation for the decision.
364 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
365 bool satisfiesOneEntry = true;
366 bool satisfiesSplitRM = true;
367 bool satisfiesSplitReg = true;
368 bool satisfiesSplitMisc = true;
370 for (unsigned index = 0; index < 256; ++index) {
371 if (decision.instructionIDs[index] != decision.instructionIDs[0])
372 satisfiesOneEntry = false;
374 if (((index & 0xc0) == 0xc0) &&
375 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
376 satisfiesSplitRM = false;
378 if (((index & 0xc0) != 0xc0) &&
379 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
380 satisfiesSplitRM = false;
382 if (((index & 0xc0) == 0xc0) &&
383 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
384 satisfiesSplitReg = false;
386 if (((index & 0xc0) != 0xc0) &&
387 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
388 satisfiesSplitMisc = false;
391 if (satisfiesOneEntry)
392 return MODRM_ONEENTRY;
394 if (satisfiesSplitRM)
395 return MODRM_SPLITRM;
397 if (satisfiesSplitReg && satisfiesSplitMisc)
398 return MODRM_SPLITREG;
400 if (satisfiesSplitMisc)
401 return MODRM_SPLITMISC;
406 /// stringForDecisionType - Returns a statically-allocated string corresponding
407 /// to a particular decision type.
409 /// @param dt - The decision type.
410 /// @return - A pointer to the statically-allocated string (e.g.,
411 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
412 static const char* stringForDecisionType(ModRMDecisionType dt) {
413 #define ENUM_ENTRY(n) case n: return #n;
416 llvm_unreachable("Unknown decision type");
422 DisassemblerTables::DisassemblerTables() {
425 for (i = 0; i < array_lengthof(Tables); i++) {
426 Tables[i] = new ContextDecision;
427 memset(Tables[i], 0, sizeof(ContextDecision));
430 HasConflicts = false;
433 DisassemblerTables::~DisassemblerTables() {
436 for (i = 0; i < array_lengthof(Tables); i++)
440 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
441 unsigned &i1, unsigned &i2,
442 unsigned &ModRMTableNum,
443 ModRMDecision &decision) const {
444 static uint32_t sTableNumber = 0;
445 static uint32_t sEntryNumber = 1;
446 ModRMDecisionType dt = getDecisionType(decision);
448 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
450 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
453 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
454 o2.indent(i2) << 0 << " /* EmptyTable */\n";
457 o2.indent(i2) << "}";
461 std::vector<unsigned> ModRMDecision;
465 llvm_unreachable("Unknown decision type");
467 ModRMDecision.push_back(decision.instructionIDs[0]);
470 ModRMDecision.push_back(decision.instructionIDs[0x00]);
471 ModRMDecision.push_back(decision.instructionIDs[0xc0]);
474 for (unsigned index = 0; index < 64; index += 8)
475 ModRMDecision.push_back(decision.instructionIDs[index]);
476 for (unsigned index = 0xc0; index < 256; index += 8)
477 ModRMDecision.push_back(decision.instructionIDs[index]);
479 case MODRM_SPLITMISC:
480 for (unsigned index = 0; index < 64; index += 8)
481 ModRMDecision.push_back(decision.instructionIDs[index]);
482 for (unsigned index = 0xc0; index < 256; ++index)
483 ModRMDecision.push_back(decision.instructionIDs[index]);
486 for (unsigned index = 0; index < 256; ++index)
487 ModRMDecision.push_back(decision.instructionIDs[index]);
491 unsigned &EntryNumber = ModRMTable[ModRMDecision];
492 if (EntryNumber == 0) {
493 EntryNumber = ModRMTableNum;
495 ModRMTableNum += ModRMDecision.size();
496 o1 << "/* Table" << EntryNumber << " */\n";
498 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
499 E = ModRMDecision.end(); I != E; ++I) {
500 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* "
501 << InstructionSpecifiers[*I].name << " */\n";
506 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
509 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
510 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n";
513 o2.indent(i2) << "}";
517 llvm_unreachable("Unknown decision type");
527 case MODRM_SPLITMISC:
528 sEntryNumber += 8 + 64;
535 // We assume that the index can fit into uint16_t.
536 assert(sEntryNumber < 65536U &&
537 "Index into ModRMDecision is too large for uint16_t!");
542 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
543 unsigned &i1, unsigned &i2,
544 unsigned &ModRMTableNum,
545 OpcodeDecision &decision) const {
546 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
548 o2.indent(i2) << "{" << "\n";
551 for (unsigned index = 0; index < 256; ++index) {
554 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
556 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
557 decision.modRMDecisions[index]);
566 o2.indent(i2) << "}" << "\n";
568 o2.indent(i2) << "}" << "\n";
571 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
572 unsigned &i1, unsigned &i2,
573 unsigned &ModRMTableNum,
574 ContextDecision &decision,
575 const char* name) const {
576 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
578 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
581 for (unsigned index = 0; index < IC_max; ++index) {
582 o2.indent(i2) << "/* ";
583 o2 << stringForContext((InstructionContext)index);
587 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
588 decision.opcodeDecisions[index]);
590 if (index + 1 < IC_max)
595 o2.indent(i2) << "}" << "\n";
597 o2.indent(i2) << "};" << "\n";
600 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
602 unsigned NumInstructions = InstructionSpecifiers.size();
604 o << "static const struct OperandSpecifier x86OperandSets[]["
605 << X86_MAX_OPERANDS << "] = {\n";
607 typedef SmallVector<std::pair<OperandEncoding, OperandType>,
608 X86_MAX_OPERANDS> OperandListTy;
609 std::map<OperandListTy, unsigned> OperandSets;
611 unsigned OperandSetNum = 0;
612 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
613 OperandListTy OperandList;
615 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
617 OperandEncoding Encoding = (OperandEncoding)InstructionSpecifiers[Index]
618 .operands[OperandIndex].encoding;
619 OperandType Type = (OperandType)InstructionSpecifiers[Index]
620 .operands[OperandIndex].type;
621 OperandList.push_back(std::make_pair(Encoding, Type));
623 unsigned &N = OperandSets[OperandList];
624 if (N != 0) continue;
628 o << " { /* " << (OperandSetNum - 1) << " */\n";
629 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
630 const char *Encoding = stringForOperandEncoding(OperandList[i].first);
631 const char *Type = stringForOperandType(OperandList[i].second);
632 o << " { " << Encoding << ", " << Type << " },\n";
638 o.indent(i * 2) << "static const struct InstructionSpecifier ";
639 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
643 for (unsigned index = 0; index < NumInstructions; ++index) {
644 o.indent(i * 2) << "{ /* " << index << " */\n";
647 OperandListTy OperandList;
648 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
650 OperandEncoding Encoding = (OperandEncoding)InstructionSpecifiers[index]
651 .operands[OperandIndex].encoding;
652 OperandType Type = (OperandType)InstructionSpecifiers[index]
653 .operands[OperandIndex].type;
654 OperandList.push_back(std::make_pair(Encoding, Type));
656 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
658 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */\n";
661 o.indent(i * 2) << "},\n";
665 o.indent(i * 2) << "};" << "\n";
668 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
669 const unsigned int tableSize = 16384;
670 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
671 "[" << tableSize << "] = {\n";
674 for (unsigned index = 0; index < tableSize; ++index) {
677 if (index & ATTR_EVEX) {
679 if (index & ATTR_EVEXL2)
681 else if (index & ATTR_EVEXL)
683 if (index & ATTR_REXW)
685 if (index & ATTR_OPSIZE)
687 else if (index & ATTR_XD)
689 else if (index & ATTR_XS)
691 if (index & ATTR_EVEXKZ)
693 else if (index & ATTR_EVEXK)
695 if (index & ATTR_EVEXB)
698 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
699 o << "IC_VEX_L_W_OPSIZE";
700 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
701 o << "IC_VEX_L_W_XD";
702 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
703 o << "IC_VEX_L_W_XS";
704 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
706 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
707 o << "IC_VEX_L_OPSIZE";
708 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
710 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
712 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
713 o << "IC_VEX_W_OPSIZE";
714 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
716 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
718 else if (index & ATTR_VEXL)
720 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
722 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
723 o << "IC_VEX_OPSIZE";
724 else if ((index & ATTR_VEX) && (index & ATTR_XD))
726 else if ((index & ATTR_VEX) && (index & ATTR_XS))
728 else if (index & ATTR_VEX)
730 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
731 o << "IC_64BIT_REXW_XS";
732 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
733 o << "IC_64BIT_REXW_XD";
734 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
735 (index & ATTR_OPSIZE))
736 o << "IC_64BIT_REXW_OPSIZE";
737 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
738 (index & ATTR_ADSIZE))
739 o << "IC_64BIT_REXW_ADSIZE";
740 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
741 o << "IC_64BIT_XD_OPSIZE";
742 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
743 o << "IC_64BIT_XS_OPSIZE";
744 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
746 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
748 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE) &&
749 (index & ATTR_ADSIZE))
750 o << "IC_64BIT_OPSIZE_ADSIZE";
751 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
752 o << "IC_64BIT_OPSIZE";
753 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
754 o << "IC_64BIT_ADSIZE";
755 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
756 o << "IC_64BIT_REXW";
757 else if ((index & ATTR_64BIT))
759 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
761 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
763 else if (index & ATTR_XS)
765 else if (index & ATTR_XD)
767 else if ((index & ATTR_OPSIZE) && (index & ATTR_ADSIZE))
768 o << "IC_OPSIZE_ADSIZE";
769 else if (index & ATTR_OPSIZE)
771 else if (index & ATTR_ADSIZE)
776 if (index < tableSize - 1)
781 o << " /* " << index << " */";
787 o.indent(i * 2) << "};" << "\n";
790 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
791 unsigned &i1, unsigned &i2,
792 unsigned &ModRMTableNum) const {
793 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
794 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
795 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
796 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
797 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR);
798 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR);
799 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR);
802 void DisassemblerTables::emit(raw_ostream &o) const {
809 raw_string_ostream o1(s1);
810 raw_string_ostream o2(s2);
812 emitInstructionInfo(o, i2);
815 emitContextTable(o, i2);
818 unsigned ModRMTableNum = 0;
820 o << "static const InstrUID modRMTable[] = {\n";
822 std::vector<unsigned> EmptyTable(1, 0);
823 ModRMTable[EmptyTable] = ModRMTableNum;
824 ModRMTableNum += EmptyTable.size();
825 o1 << "/* EmptyTable */\n";
826 o1.indent(i1 * 2) << "0x0,\n";
828 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
839 void DisassemblerTables::setTableFields(ModRMDecision &decision,
840 const ModRMFilter &filter,
843 for (unsigned index = 0; index < 256; ++index) {
844 if (filter.accepts(index)) {
845 if (decision.instructionIDs[index] == uid)
848 if (decision.instructionIDs[index] != 0) {
849 InstructionSpecifier &newInfo =
850 InstructionSpecifiers[uid];
851 InstructionSpecifier &previousInfo =
852 InstructionSpecifiers[decision.instructionIDs[index]];
854 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
855 newInfo.name == "XCHG32ar" ||
856 newInfo.name == "XCHG32ar64" ||
857 newInfo.name == "XCHG64ar"))
858 continue; // special case for XCHG*ar and NOOP
860 if (outranks(previousInfo.insnContext, newInfo.insnContext))
863 if (previousInfo.insnContext == newInfo.insnContext) {
864 errs() << "Error: Primary decode conflict: ";
865 errs() << newInfo.name << " would overwrite " << previousInfo.name;
867 errs() << "ModRM " << index << "\n";
868 errs() << "Opcode " << (uint16_t)opcode << "\n";
869 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
874 decision.instructionIDs[index] = uid;
879 void DisassemblerTables::setTableFields(OpcodeType type,
880 InstructionContext insnContext,
882 const ModRMFilter &filter,
886 unsigned addressSize) {
887 ContextDecision &decision = *Tables[type];
889 for (unsigned index = 0; index < IC_max; ++index) {
890 if ((is32bit || addressSize == 16) &&
891 inheritsFrom((InstructionContext)index, IC_64BIT))
894 bool adSize64 = addressSize == 64;
895 if (inheritsFrom((InstructionContext)index,
896 InstructionSpecifiers[uid].insnContext, ignoresVEX_L,
898 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],