1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
25 using namespace X86Disassembler;
27 /// stringForContext - Returns a string containing the name of a particular
28 /// InstructionContext, usually for diagnostic purposes.
30 /// @param insnContext - The instruction class to transform to a string.
31 /// @return - A statically-allocated string constant that contains the
32 /// name of the instruction class.
33 static inline const char* stringForContext(InstructionContext insnContext) {
34 switch (insnContext) {
36 llvm_unreachable("Unhandled instruction class");
37 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
38 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
40 ENUM_ENTRY(n##_KZ_B, r, d)
47 /// stringForOperandType - Like stringForContext, but for OperandTypes.
48 static inline const char* stringForOperandType(OperandType type) {
51 llvm_unreachable("Unhandled type");
52 #define ENUM_ENTRY(i, d) case i: return #i;
58 /// stringForOperandEncoding - like stringForContext, but for
60 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
63 llvm_unreachable("Unhandled encoding");
64 #define ENUM_ENTRY(i, d) case i: return #i;
70 /// inheritsFrom - Indicates whether all instructions in one class also belong
73 /// @param child - The class that may be the subset
74 /// @param parent - The class that may be the superset
75 /// @return - True if child is a subset of parent, false otherwise.
76 static inline bool inheritsFrom(InstructionContext child,
77 InstructionContext parent,
78 bool VEX_LIG = false) {
84 return(inheritsFrom(child, IC_64BIT) ||
85 inheritsFrom(child, IC_OPSIZE) ||
86 inheritsFrom(child, IC_ADSIZE) ||
87 inheritsFrom(child, IC_XD) ||
88 inheritsFrom(child, IC_XS));
90 return(inheritsFrom(child, IC_64BIT_REXW) ||
91 inheritsFrom(child, IC_64BIT_OPSIZE) ||
92 inheritsFrom(child, IC_64BIT_ADSIZE) ||
93 inheritsFrom(child, IC_64BIT_XD) ||
94 inheritsFrom(child, IC_64BIT_XS));
96 return inheritsFrom(child, IC_64BIT_OPSIZE);
101 return inheritsFrom(child, IC_64BIT_XD);
103 return inheritsFrom(child, IC_64BIT_XS);
105 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
107 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
109 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
110 inheritsFrom(child, IC_64BIT_REXW_XD) ||
111 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
112 case IC_64BIT_OPSIZE:
113 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
115 return(inheritsFrom(child, IC_64BIT_REXW_XD));
117 return(inheritsFrom(child, IC_64BIT_REXW_XS));
118 case IC_64BIT_XD_OPSIZE:
119 case IC_64BIT_XS_OPSIZE:
121 case IC_64BIT_REXW_XD:
122 case IC_64BIT_REXW_XS:
123 case IC_64BIT_REXW_OPSIZE:
126 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
127 inheritsFrom(child, IC_VEX_W) ||
128 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
130 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
131 inheritsFrom(child, IC_VEX_W_XS) ||
132 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
134 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
135 inheritsFrom(child, IC_VEX_W_XD) ||
136 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
138 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
139 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
140 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
142 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
144 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
146 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
147 case IC_VEX_W_OPSIZE:
148 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
150 return inheritsFrom(child, IC_VEX_L_W);
152 return inheritsFrom(child, IC_VEX_L_W_XS);
154 return inheritsFrom(child, IC_VEX_L_W_XD);
155 case IC_VEX_L_OPSIZE:
156 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
160 case IC_VEX_L_W_OPSIZE:
163 return inheritsFrom(child, IC_EVEX_W) ||
164 inheritsFrom(child, IC_EVEX_L_W);
166 return inheritsFrom(child, IC_EVEX_W_XS) ||
167 inheritsFrom(child, IC_EVEX_L_W_XS);
169 return inheritsFrom(child, IC_EVEX_W_XD) ||
170 inheritsFrom(child, IC_EVEX_L_W_XD);
172 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
173 inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
177 case IC_EVEX_W_OPSIZE:
182 case IC_EVEX_L_OPSIZE:
187 case IC_EVEX_L_W_OPSIZE:
192 case IC_EVEX_L2_OPSIZE:
195 case IC_EVEX_L2_W_XS:
196 case IC_EVEX_L2_W_XD:
197 case IC_EVEX_L2_W_OPSIZE:
200 return inheritsFrom(child, IC_EVEX_W_K) ||
201 inheritsFrom(child, IC_EVEX_L_W_K);
203 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
204 inheritsFrom(child, IC_EVEX_L_W_XS_K);
206 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
207 inheritsFrom(child, IC_EVEX_L_W_XD_K);
208 case IC_EVEX_OPSIZE_K:
209 case IC_EVEX_OPSIZE_B:
214 case IC_EVEX_W_OPSIZE_K:
215 case IC_EVEX_W_OPSIZE_B:
220 case IC_EVEX_L_OPSIZE_K:
223 case IC_EVEX_W_XS_KZ:
224 case IC_EVEX_W_XD_KZ:
225 case IC_EVEX_W_OPSIZE_KZ:
228 case IC_EVEX_L_XS_KZ:
229 case IC_EVEX_L_XD_KZ:
230 case IC_EVEX_L_OPSIZE_KZ:
233 case IC_EVEX_L_W_XS_K:
234 case IC_EVEX_L_W_XD_K:
235 case IC_EVEX_L_W_OPSIZE_K:
237 case IC_EVEX_L_W_XS_KZ:
238 case IC_EVEX_L_W_XD_KZ:
239 case IC_EVEX_L_W_OPSIZE_KZ:
244 case IC_EVEX_L2_KZ_B:
245 case IC_EVEX_L2_XS_K:
246 case IC_EVEX_L2_XS_B:
247 case IC_EVEX_L2_XD_B:
248 case IC_EVEX_L2_XD_K:
249 case IC_EVEX_L2_OPSIZE_K:
250 case IC_EVEX_L2_OPSIZE_B:
251 case IC_EVEX_L2_OPSIZE_K_B:
253 case IC_EVEX_L2_XS_KZ:
254 case IC_EVEX_L2_XD_KZ:
255 case IC_EVEX_L2_OPSIZE_KZ:
256 case IC_EVEX_L2_OPSIZE_KZ_B:
260 case IC_EVEX_L2_W_XS_K:
261 case IC_EVEX_L2_W_XD_K:
262 case IC_EVEX_L2_W_XD_B:
263 case IC_EVEX_L2_W_OPSIZE_K:
264 case IC_EVEX_L2_W_OPSIZE_B:
265 case IC_EVEX_L2_W_OPSIZE_K_B:
266 case IC_EVEX_L2_W_KZ:
267 case IC_EVEX_L2_W_XS_KZ:
268 case IC_EVEX_L2_W_XD_KZ:
269 case IC_EVEX_L2_W_OPSIZE_KZ:
270 case IC_EVEX_L2_W_OPSIZE_KZ_B:
273 errs() << "Unknown instruction class: " <<
274 stringForContext((InstructionContext)parent) << "\n";
275 llvm_unreachable("Unknown instruction class");
279 /// outranks - Indicates whether, if an instruction has two different applicable
280 /// classes, which class should be preferred when performing decode. This
281 /// imposes a total ordering (ties are resolved toward "lower")
283 /// @param upper - The class that may be preferable
284 /// @param lower - The class that may be less preferable
285 /// @return - True if upper is to be preferred, false otherwise.
286 static inline bool outranks(InstructionContext upper,
287 InstructionContext lower) {
288 assert(upper < IC_max);
289 assert(lower < IC_max);
291 #define ENUM_ENTRY(n, r, d) r,
292 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
293 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \
294 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
295 static int ranks[IC_max] = {
299 #undef ENUM_ENTRY_K_B
301 return (ranks[upper] > ranks[lower]);
304 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
305 /// be compacted by eliminating redundant information.
307 /// @param decision - The decision to be compacted.
308 /// @return - The compactest available representation for the decision.
309 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
310 bool satisfiesOneEntry = true;
311 bool satisfiesSplitRM = true;
312 bool satisfiesSplitReg = true;
313 bool satisfiesSplitMisc = true;
315 for (unsigned index = 0; index < 256; ++index) {
316 if (decision.instructionIDs[index] != decision.instructionIDs[0])
317 satisfiesOneEntry = false;
319 if (((index & 0xc0) == 0xc0) &&
320 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
321 satisfiesSplitRM = false;
323 if (((index & 0xc0) != 0xc0) &&
324 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
325 satisfiesSplitRM = false;
327 if (((index & 0xc0) == 0xc0) &&
328 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
329 satisfiesSplitReg = false;
331 if (((index & 0xc0) != 0xc0) &&
332 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
333 satisfiesSplitMisc = false;
336 if (satisfiesOneEntry)
337 return MODRM_ONEENTRY;
339 if (satisfiesSplitRM)
340 return MODRM_SPLITRM;
342 if (satisfiesSplitReg && satisfiesSplitMisc)
343 return MODRM_SPLITREG;
345 if (satisfiesSplitMisc)
346 return MODRM_SPLITMISC;
351 /// stringForDecisionType - Returns a statically-allocated string corresponding
352 /// to a particular decision type.
354 /// @param dt - The decision type.
355 /// @return - A pointer to the statically-allocated string (e.g.,
356 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
357 static const char* stringForDecisionType(ModRMDecisionType dt) {
358 #define ENUM_ENTRY(n) case n: return #n;
361 llvm_unreachable("Unknown decision type");
367 DisassemblerTables::DisassemblerTables() {
370 for (i = 0; i < array_lengthof(Tables); i++) {
371 Tables[i] = new ContextDecision;
372 memset(Tables[i], 0, sizeof(ContextDecision));
375 HasConflicts = false;
378 DisassemblerTables::~DisassemblerTables() {
381 for (i = 0; i < array_lengthof(Tables); i++)
385 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
386 unsigned &i1, unsigned &i2,
387 unsigned &ModRMTableNum,
388 ModRMDecision &decision) const {
389 static uint32_t sTableNumber = 0;
390 static uint32_t sEntryNumber = 1;
391 ModRMDecisionType dt = getDecisionType(decision);
393 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
395 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
398 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
399 o2.indent(i2) << 0 << " /* EmptyTable */\n";
402 o2.indent(i2) << "}";
406 std::vector<unsigned> ModRMDecision;
410 llvm_unreachable("Unknown decision type");
412 ModRMDecision.push_back(decision.instructionIDs[0]);
415 ModRMDecision.push_back(decision.instructionIDs[0x00]);
416 ModRMDecision.push_back(decision.instructionIDs[0xc0]);
419 for (unsigned index = 0; index < 64; index += 8)
420 ModRMDecision.push_back(decision.instructionIDs[index]);
421 for (unsigned index = 0xc0; index < 256; index += 8)
422 ModRMDecision.push_back(decision.instructionIDs[index]);
424 case MODRM_SPLITMISC:
425 for (unsigned index = 0; index < 64; index += 8)
426 ModRMDecision.push_back(decision.instructionIDs[index]);
427 for (unsigned index = 0xc0; index < 256; ++index)
428 ModRMDecision.push_back(decision.instructionIDs[index]);
431 for (unsigned index = 0; index < 256; ++index)
432 ModRMDecision.push_back(decision.instructionIDs[index]);
436 unsigned &EntryNumber = ModRMTable[ModRMDecision];
437 if (EntryNumber == 0) {
438 EntryNumber = ModRMTableNum;
440 ModRMTableNum += ModRMDecision.size();
441 o1 << "/* Table" << EntryNumber << " */\n";
443 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
444 E = ModRMDecision.end(); I != E; ++I) {
445 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* "
446 << InstructionSpecifiers[*I].name << " */\n";
451 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
454 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
455 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n";
458 o2.indent(i2) << "}";
462 llvm_unreachable("Unknown decision type");
472 case MODRM_SPLITMISC:
473 sEntryNumber += 8 + 64;
480 // We assume that the index can fit into uint16_t.
481 assert(sEntryNumber < 65536U &&
482 "Index into ModRMDecision is too large for uint16_t!");
487 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
488 unsigned &i1, unsigned &i2,
489 unsigned &ModRMTableNum,
490 OpcodeDecision &decision) const {
491 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
493 o2.indent(i2) << "{" << "\n";
496 for (unsigned index = 0; index < 256; ++index) {
499 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
501 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
502 decision.modRMDecisions[index]);
511 o2.indent(i2) << "}" << "\n";
513 o2.indent(i2) << "}" << "\n";
516 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
517 unsigned &i1, unsigned &i2,
518 unsigned &ModRMTableNum,
519 ContextDecision &decision,
520 const char* name) const {
521 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
523 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
526 for (unsigned index = 0; index < IC_max; ++index) {
527 o2.indent(i2) << "/* ";
528 o2 << stringForContext((InstructionContext)index);
532 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
533 decision.opcodeDecisions[index]);
535 if (index + 1 < IC_max)
540 o2.indent(i2) << "}" << "\n";
542 o2.indent(i2) << "};" << "\n";
545 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
547 unsigned NumInstructions = InstructionSpecifiers.size();
549 o << "static const struct OperandSpecifier x86OperandSets[]["
550 << X86_MAX_OPERANDS << "] = {\n";
552 typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
553 std::map<OperandListTy, unsigned> OperandSets;
555 unsigned OperandSetNum = 0;
556 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
557 OperandListTy OperandList;
559 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
561 const char *Encoding =
562 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
563 .operands[OperandIndex].encoding);
565 stringForOperandType((OperandType)InstructionSpecifiers[Index]
566 .operands[OperandIndex].type);
567 OperandList.push_back(std::make_pair(Encoding, Type));
569 unsigned &N = OperandSets[OperandList];
570 if (N != 0) continue;
574 o << " { /* " << (OperandSetNum - 1) << " */\n";
575 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
576 o << " { " << OperandList[i].first << ", "
577 << OperandList[i].second << " },\n";
583 o.indent(i * 2) << "static const struct InstructionSpecifier ";
584 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
588 for (unsigned index = 0; index < NumInstructions; ++index) {
589 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
592 OperandListTy OperandList;
593 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
595 const char *Encoding =
596 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
597 .operands[OperandIndex].encoding);
599 stringForOperandType((OperandType)InstructionSpecifiers[index]
600 .operands[OperandIndex].type);
601 OperandList.push_back(std::make_pair(Encoding, Type));
603 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
605 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
609 o.indent(i * 2) << "}";
611 if (index + 1 < NumInstructions)
618 o.indent(i * 2) << "};" << "\n";
621 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
622 const unsigned int tableSize = 16384;
623 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
624 "[" << tableSize << "] = {\n";
627 for (unsigned index = 0; index < tableSize; ++index) {
630 if (index & ATTR_EVEX) {
632 if (index & ATTR_EVEXL2)
634 else if (index & ATTR_EVEXL)
636 if (index & ATTR_REXW)
638 if (index & ATTR_OPSIZE)
640 else if (index & ATTR_XD)
642 else if (index & ATTR_XS)
644 if (index & ATTR_EVEXKZ)
646 else if (index & ATTR_EVEXK)
648 if (index & ATTR_EVEXB)
651 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
652 o << "IC_VEX_L_W_OPSIZE";
653 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
654 o << "IC_VEX_L_W_XD";
655 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
656 o << "IC_VEX_L_W_XS";
657 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
659 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
660 o << "IC_VEX_L_OPSIZE";
661 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
663 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
665 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
666 o << "IC_VEX_W_OPSIZE";
667 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
669 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
671 else if (index & ATTR_VEXL)
673 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
675 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
676 o << "IC_VEX_OPSIZE";
677 else if ((index & ATTR_VEX) && (index & ATTR_XD))
679 else if ((index & ATTR_VEX) && (index & ATTR_XS))
681 else if (index & ATTR_VEX)
683 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
684 o << "IC_64BIT_REXW_XS";
685 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
686 o << "IC_64BIT_REXW_XD";
687 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
688 (index & ATTR_OPSIZE))
689 o << "IC_64BIT_REXW_OPSIZE";
690 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
691 o << "IC_64BIT_XD_OPSIZE";
692 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
693 o << "IC_64BIT_XS_OPSIZE";
694 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
696 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
698 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
699 o << "IC_64BIT_OPSIZE";
700 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
701 o << "IC_64BIT_ADSIZE";
702 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
703 o << "IC_64BIT_REXW";
704 else if ((index & ATTR_64BIT))
706 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
708 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
710 else if (index & ATTR_XS)
712 else if (index & ATTR_XD)
714 else if (index & ATTR_OPSIZE)
716 else if (index & ATTR_ADSIZE)
721 if (index < tableSize - 1)
726 o << " /* " << index << " */";
732 o.indent(i * 2) << "};" << "\n";
735 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
736 unsigned &i1, unsigned &i2,
737 unsigned &ModRMTableNum) const {
738 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
739 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
740 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
741 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
742 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], XOP8_MAP_STR);
743 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], XOP9_MAP_STR);
744 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOPA_MAP_STR);
747 void DisassemblerTables::emit(raw_ostream &o) const {
754 raw_string_ostream o1(s1);
755 raw_string_ostream o2(s2);
757 emitInstructionInfo(o, i2);
760 emitContextTable(o, i2);
763 unsigned ModRMTableNum = 0;
765 o << "static const InstrUID modRMTable[] = {\n";
767 std::vector<unsigned> EmptyTable(1, 0);
768 ModRMTable[EmptyTable] = ModRMTableNum;
769 ModRMTableNum += EmptyTable.size();
770 o1 << "/* EmptyTable */\n";
771 o1.indent(i1 * 2) << "0x0,\n";
773 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
784 void DisassemblerTables::setTableFields(ModRMDecision &decision,
785 const ModRMFilter &filter,
788 for (unsigned index = 0; index < 256; ++index) {
789 if (filter.accepts(index)) {
790 if (decision.instructionIDs[index] == uid)
793 if (decision.instructionIDs[index] != 0) {
794 InstructionSpecifier &newInfo =
795 InstructionSpecifiers[uid];
796 InstructionSpecifier &previousInfo =
797 InstructionSpecifiers[decision.instructionIDs[index]];
799 // Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the
800 // presence of the AdSize prefix. However, the disassembler doesn't
801 // care about that difference in the instruction definition; it
802 // handles 16-bit vs. 32-bit addressing for itself based purely
803 // on the 0x67 prefix and the CPU mode. So there's no need to
804 // disambiguate between them; just let them conflict/coexist.
805 if (previousInfo.name + "_16" == newInfo.name)
808 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
809 newInfo.name == "XCHG32ar" ||
810 newInfo.name == "XCHG32ar64" ||
811 newInfo.name == "XCHG64ar"))
812 continue; // special case for XCHG*ar and NOOP
814 if (outranks(previousInfo.insnContext, newInfo.insnContext))
817 if (previousInfo.insnContext == newInfo.insnContext) {
818 errs() << "Error: Primary decode conflict: ";
819 errs() << newInfo.name << " would overwrite " << previousInfo.name;
821 errs() << "ModRM " << index << "\n";
822 errs() << "Opcode " << (uint16_t)opcode << "\n";
823 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
828 decision.instructionIDs[index] = uid;
833 void DisassemblerTables::setTableFields(OpcodeType type,
834 InstructionContext insnContext,
836 const ModRMFilter &filter,
840 ContextDecision &decision = *Tables[type];
842 for (unsigned index = 0; index < IC_max; ++index) {
843 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
846 if (inheritsFrom((InstructionContext)index,
847 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
848 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],