1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
22 #include "llvm/TableGen/TableGenBackend.h"
26 using namespace X86Disassembler;
28 /// stringForContext - Returns a string containing the name of a particular
29 /// InstructionContext, usually for diagnostic purposes.
31 /// @param insnContext - The instruction class to transform to a string.
32 /// @return - A statically-allocated string constant that contains the
33 /// name of the instruction class.
34 static inline const char* stringForContext(InstructionContext insnContext) {
35 switch (insnContext) {
37 llvm_unreachable("Unhandled instruction class");
38 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
39 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
40 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
41 ENUM_ENTRY(n##_KZ_B, r, d)
48 /// stringForOperandType - Like stringForContext, but for OperandTypes.
49 static inline const char* stringForOperandType(OperandType type) {
52 llvm_unreachable("Unhandled type");
53 #define ENUM_ENTRY(i, d) case i: return #i;
59 /// stringForOperandEncoding - like stringForContext, but for
61 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
64 llvm_unreachable("Unhandled encoding");
65 #define ENUM_ENTRY(i, d) case i: return #i;
71 /// inheritsFrom - Indicates whether all instructions in one class also belong
74 /// @param child - The class that may be the subset
75 /// @param parent - The class that may be the superset
76 /// @return - True if child is a subset of parent, false otherwise.
77 static inline bool inheritsFrom(InstructionContext child,
78 InstructionContext parent,
79 bool VEX_LIG = false) {
85 return(inheritsFrom(child, IC_64BIT) ||
86 inheritsFrom(child, IC_OPSIZE) ||
87 inheritsFrom(child, IC_ADSIZE) ||
88 inheritsFrom(child, IC_XD) ||
89 inheritsFrom(child, IC_XS));
91 return(inheritsFrom(child, IC_64BIT_REXW) ||
92 inheritsFrom(child, IC_64BIT_OPSIZE) ||
93 inheritsFrom(child, IC_64BIT_ADSIZE) ||
94 inheritsFrom(child, IC_64BIT_XD) ||
95 inheritsFrom(child, IC_64BIT_XS));
97 return inheritsFrom(child, IC_64BIT_OPSIZE);
102 return inheritsFrom(child, IC_64BIT_XD);
104 return inheritsFrom(child, IC_64BIT_XS);
106 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
108 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
110 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
111 inheritsFrom(child, IC_64BIT_REXW_XD) ||
112 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
113 case IC_64BIT_OPSIZE:
114 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
116 return(inheritsFrom(child, IC_64BIT_REXW_XD));
118 return(inheritsFrom(child, IC_64BIT_REXW_XS));
119 case IC_64BIT_XD_OPSIZE:
120 case IC_64BIT_XS_OPSIZE:
122 case IC_64BIT_REXW_XD:
123 case IC_64BIT_REXW_XS:
124 case IC_64BIT_REXW_OPSIZE:
127 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
128 inheritsFrom(child, IC_VEX_W) ||
129 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
131 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
132 inheritsFrom(child, IC_VEX_W_XS) ||
133 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
135 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
136 inheritsFrom(child, IC_VEX_W_XD) ||
137 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
139 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
140 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
141 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
143 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
145 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
147 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
148 case IC_VEX_W_OPSIZE:
149 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
151 return inheritsFrom(child, IC_VEX_L_W);
153 return inheritsFrom(child, IC_VEX_L_W_XS);
155 return inheritsFrom(child, IC_VEX_L_W_XD);
156 case IC_VEX_L_OPSIZE:
157 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
161 case IC_VEX_L_W_OPSIZE:
164 return inheritsFrom(child, IC_EVEX_W) ||
165 inheritsFrom(child, IC_EVEX_L_W);
167 return inheritsFrom(child, IC_EVEX_W_XS) ||
168 inheritsFrom(child, IC_EVEX_L_W_XS);
170 return inheritsFrom(child, IC_EVEX_W_XD) ||
171 inheritsFrom(child, IC_EVEX_L_W_XD);
173 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
174 inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
178 case IC_EVEX_W_OPSIZE:
183 case IC_EVEX_L_OPSIZE:
188 case IC_EVEX_L_W_OPSIZE:
193 case IC_EVEX_L2_OPSIZE:
196 case IC_EVEX_L2_W_XS:
197 case IC_EVEX_L2_W_XD:
198 case IC_EVEX_L2_W_OPSIZE:
201 return inheritsFrom(child, IC_EVEX_W_K) ||
202 inheritsFrom(child, IC_EVEX_L_W_K);
204 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
205 inheritsFrom(child, IC_EVEX_L_W_XS_K);
207 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
208 inheritsFrom(child, IC_EVEX_L_W_XD_K);
209 case IC_EVEX_OPSIZE_K:
210 return inheritsFrom(child, IC_EVEX_W_OPSIZE_K) ||
211 inheritsFrom(child, IC_EVEX_W_OPSIZE_K);
215 case IC_EVEX_W_OPSIZE_K:
220 case IC_EVEX_L_OPSIZE_K:
223 case IC_EVEX_W_XS_KZ:
224 case IC_EVEX_W_XD_KZ:
225 case IC_EVEX_W_OPSIZE_KZ:
228 case IC_EVEX_L_XS_KZ:
229 case IC_EVEX_L_XD_KZ:
230 case IC_EVEX_L_OPSIZE_KZ:
233 case IC_EVEX_L_W_XS_K:
234 case IC_EVEX_L_W_XD_K:
235 case IC_EVEX_L_W_OPSIZE_K:
237 case IC_EVEX_L_W_XS_KZ:
238 case IC_EVEX_L_W_XD_KZ:
239 case IC_EVEX_L_W_OPSIZE_KZ:
243 case IC_EVEX_L2_XS_K:
244 case IC_EVEX_L2_XS_B:
245 case IC_EVEX_L2_XD_B:
246 case IC_EVEX_L2_XD_K:
247 case IC_EVEX_L2_OPSIZE_K:
248 case IC_EVEX_L2_OPSIZE_B:
249 case IC_EVEX_L2_OPSIZE_K_B:
251 case IC_EVEX_L2_XS_KZ:
252 case IC_EVEX_L2_XD_KZ:
253 case IC_EVEX_L2_OPSIZE_KZ:
254 case IC_EVEX_L2_OPSIZE_KZ_B:
258 case IC_EVEX_L2_W_XS_K:
259 case IC_EVEX_L2_W_XD_K:
260 case IC_EVEX_L2_W_XD_B:
261 case IC_EVEX_L2_W_OPSIZE_K:
262 case IC_EVEX_L2_W_OPSIZE_B:
263 case IC_EVEX_L2_W_OPSIZE_K_B:
264 case IC_EVEX_L2_W_KZ:
265 case IC_EVEX_L2_W_XS_KZ:
266 case IC_EVEX_L2_W_XD_KZ:
267 case IC_EVEX_L2_W_OPSIZE_KZ:
268 case IC_EVEX_L2_W_OPSIZE_KZ_B:
271 errs() << "Unknown instruction class: " <<
272 stringForContext((InstructionContext)parent) << "\n";
273 llvm_unreachable("Unknown instruction class");
277 /// outranks - Indicates whether, if an instruction has two different applicable
278 /// classes, which class should be preferred when performing decode. This
279 /// imposes a total ordering (ties are resolved toward "lower")
281 /// @param upper - The class that may be preferable
282 /// @param lower - The class that may be less preferable
283 /// @return - True if upper is to be preferred, false otherwise.
284 static inline bool outranks(InstructionContext upper,
285 InstructionContext lower) {
286 assert(upper < IC_max);
287 assert(lower < IC_max);
289 #define ENUM_ENTRY(n, r, d) r,
290 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
291 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \
292 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
293 static int ranks[IC_max] = {
297 #undef ENUM_ENTRY_K_B
299 return (ranks[upper] > ranks[lower]);
302 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
303 /// be compacted by eliminating redundant information.
305 /// @param decision - The decision to be compacted.
306 /// @return - The compactest available representation for the decision.
307 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
308 bool satisfiesOneEntry = true;
309 bool satisfiesSplitRM = true;
310 bool satisfiesSplitReg = true;
311 bool satisfiesSplitMisc = true;
313 for (unsigned index = 0; index < 256; ++index) {
314 if (decision.instructionIDs[index] != decision.instructionIDs[0])
315 satisfiesOneEntry = false;
317 if (((index & 0xc0) == 0xc0) &&
318 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
319 satisfiesSplitRM = false;
321 if (((index & 0xc0) != 0xc0) &&
322 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
323 satisfiesSplitRM = false;
325 if (((index & 0xc0) == 0xc0) &&
326 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
327 satisfiesSplitReg = false;
329 if (((index & 0xc0) != 0xc0) &&
330 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
331 satisfiesSplitMisc = false;
334 if (satisfiesOneEntry)
335 return MODRM_ONEENTRY;
337 if (satisfiesSplitRM)
338 return MODRM_SPLITRM;
340 if (satisfiesSplitReg && satisfiesSplitMisc)
341 return MODRM_SPLITREG;
343 if (satisfiesSplitMisc)
344 return MODRM_SPLITMISC;
349 /// stringForDecisionType - Returns a statically-allocated string corresponding
350 /// to a particular decision type.
352 /// @param dt - The decision type.
353 /// @return - A pointer to the statically-allocated string (e.g.,
354 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
355 static const char* stringForDecisionType(ModRMDecisionType dt) {
356 #define ENUM_ENTRY(n) case n: return #n;
359 llvm_unreachable("Unknown decision type");
365 /// stringForModifierType - Returns a statically-allocated string corresponding
366 /// to an opcode modifier type.
368 /// @param mt - The modifier type.
369 /// @return - A pointer to the statically-allocated string (e.g.,
370 /// "MODIFIER_NONE" for MODIFIER_NONE).
371 static const char* stringForModifierType(ModifierType mt) {
372 #define ENUM_ENTRY(n) case n: return #n;
375 llvm_unreachable("Unknown modifier type");
381 DisassemblerTables::DisassemblerTables() {
384 for (i = 0; i < array_lengthof(Tables); i++) {
385 Tables[i] = new ContextDecision;
386 memset(Tables[i], 0, sizeof(ContextDecision));
389 HasConflicts = false;
392 DisassemblerTables::~DisassemblerTables() {
395 for (i = 0; i < array_lengthof(Tables); i++)
399 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
400 unsigned &i1, unsigned &i2,
401 unsigned &ModRMTableNum,
402 ModRMDecision &decision) const {
403 static uint32_t sTableNumber = 0;
404 static uint32_t sEntryNumber = 1;
405 ModRMDecisionType dt = getDecisionType(decision);
407 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
409 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
412 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
413 o2.indent(i2) << 0 << " /* EmptyTable */\n";
416 o2.indent(i2) << "}";
420 std::vector<unsigned> ModRMDecision;
424 llvm_unreachable("Unknown decision type");
426 ModRMDecision.push_back(decision.instructionIDs[0]);
429 ModRMDecision.push_back(decision.instructionIDs[0x00]);
430 ModRMDecision.push_back(decision.instructionIDs[0xc0]);
433 for (unsigned index = 0; index < 64; index += 8)
434 ModRMDecision.push_back(decision.instructionIDs[index]);
435 for (unsigned index = 0xc0; index < 256; index += 8)
436 ModRMDecision.push_back(decision.instructionIDs[index]);
438 case MODRM_SPLITMISC:
439 for (unsigned index = 0; index < 64; index += 8)
440 ModRMDecision.push_back(decision.instructionIDs[index]);
441 for (unsigned index = 0xc0; index < 256; ++index)
442 ModRMDecision.push_back(decision.instructionIDs[index]);
445 for (unsigned index = 0; index < 256; ++index)
446 ModRMDecision.push_back(decision.instructionIDs[index]);
450 unsigned &EntryNumber = ModRMTable[ModRMDecision];
451 if (EntryNumber == 0) {
452 EntryNumber = ModRMTableNum;
454 ModRMTableNum += ModRMDecision.size();
455 o1 << "/* Table" << EntryNumber << " */\n";
457 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
458 E = ModRMDecision.end(); I != E; ++I) {
459 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* "
460 << InstructionSpecifiers[*I].name << " */\n";
465 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
468 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
469 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n";
472 o2.indent(i2) << "}";
476 llvm_unreachable("Unknown decision type");
486 case MODRM_SPLITMISC:
487 sEntryNumber += 8 + 64;
494 // We assume that the index can fit into uint16_t.
495 assert(sEntryNumber < 65536U &&
496 "Index into ModRMDecision is too large for uint16_t!");
501 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
502 unsigned &i1, unsigned &i2,
503 unsigned &ModRMTableNum,
504 OpcodeDecision &decision) const {
505 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
507 o2.indent(i2) << "{" << "\n";
510 for (unsigned index = 0; index < 256; ++index) {
513 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
515 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
516 decision.modRMDecisions[index]);
525 o2.indent(i2) << "}" << "\n";
527 o2.indent(i2) << "}" << "\n";
530 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
531 unsigned &i1, unsigned &i2,
532 unsigned &ModRMTableNum,
533 ContextDecision &decision,
534 const char* name) const {
535 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
537 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
540 for (unsigned index = 0; index < IC_max; ++index) {
541 o2.indent(i2) << "/* ";
542 o2 << stringForContext((InstructionContext)index);
546 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
547 decision.opcodeDecisions[index]);
549 if (index + 1 < IC_max)
554 o2.indent(i2) << "}" << "\n";
556 o2.indent(i2) << "};" << "\n";
559 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
561 unsigned NumInstructions = InstructionSpecifiers.size();
563 o << "static const struct OperandSpecifier x86OperandSets[]["
564 << X86_MAX_OPERANDS << "] = {\n";
566 typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
567 std::map<OperandListTy, unsigned> OperandSets;
569 unsigned OperandSetNum = 0;
570 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
571 OperandListTy OperandList;
573 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
575 const char *Encoding =
576 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
577 .operands[OperandIndex].encoding);
579 stringForOperandType((OperandType)InstructionSpecifiers[Index]
580 .operands[OperandIndex].type);
581 OperandList.push_back(std::make_pair(Encoding, Type));
583 unsigned &N = OperandSets[OperandList];
584 if (N != 0) continue;
588 o << " { /* " << (OperandSetNum - 1) << " */\n";
589 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
590 o << " { " << OperandList[i].first << ", "
591 << OperandList[i].second << " },\n";
597 o.indent(i * 2) << "static const struct InstructionSpecifier ";
598 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
602 for (unsigned index = 0; index < NumInstructions; ++index) {
603 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
606 o.indent(i * 2) << stringForModifierType(
607 (ModifierType)InstructionSpecifiers[index].modifierType);
610 o.indent(i * 2) << "0x";
611 o << format("%02hhx", (uint16_t)InstructionSpecifiers[index].modifierBase);
614 OperandListTy OperandList;
615 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
617 const char *Encoding =
618 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
619 .operands[OperandIndex].encoding);
621 stringForOperandType((OperandType)InstructionSpecifiers[index]
622 .operands[OperandIndex].type);
623 OperandList.push_back(std::make_pair(Encoding, Type));
625 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
627 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
631 o.indent(i * 2) << "}";
633 if (index + 1 < NumInstructions)
640 o.indent(i * 2) << "};" << "\n";
643 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
644 const unsigned int tableSize = 16384;
645 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
646 "[" << tableSize << "] = {\n";
649 for (unsigned index = 0; index < tableSize; ++index) {
652 if (index & ATTR_EVEX) {
654 if (index & ATTR_EVEXL2)
656 else if (index & ATTR_EVEXL)
658 if (index & ATTR_REXW)
660 if (index & ATTR_OPSIZE)
662 else if (index & ATTR_XD)
664 else if (index & ATTR_XS)
666 if (index & ATTR_EVEXKZ)
668 else if (index & ATTR_EVEXK)
670 if (index & ATTR_EVEXB)
673 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
674 o << "IC_VEX_L_W_OPSIZE";
675 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
676 o << "IC_VEX_L_W_XD";
677 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
678 o << "IC_VEX_L_W_XS";
679 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
681 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
682 o << "IC_VEX_L_OPSIZE";
683 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
685 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
687 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
688 o << "IC_VEX_W_OPSIZE";
689 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
691 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
693 else if (index & ATTR_VEXL)
695 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
697 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
698 o << "IC_VEX_OPSIZE";
699 else if ((index & ATTR_VEX) && (index & ATTR_XD))
701 else if ((index & ATTR_VEX) && (index & ATTR_XS))
703 else if (index & ATTR_VEX)
705 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
706 o << "IC_64BIT_REXW_XS";
707 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
708 o << "IC_64BIT_REXW_XD";
709 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
710 (index & ATTR_OPSIZE))
711 o << "IC_64BIT_REXW_OPSIZE";
712 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
713 o << "IC_64BIT_XD_OPSIZE";
714 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
715 o << "IC_64BIT_XS_OPSIZE";
716 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
718 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
720 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
721 o << "IC_64BIT_OPSIZE";
722 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
723 o << "IC_64BIT_ADSIZE";
724 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
725 o << "IC_64BIT_REXW";
726 else if ((index & ATTR_64BIT))
728 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
730 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
732 else if (index & ATTR_XS)
734 else if (index & ATTR_XD)
736 else if (index & ATTR_OPSIZE)
738 else if (index & ATTR_ADSIZE)
743 if (index < tableSize - 1)
748 o << " /* " << index << " */";
754 o.indent(i * 2) << "};" << "\n";
757 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
758 unsigned &i1, unsigned &i2,
759 unsigned &ModRMTableNum) const {
760 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
761 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
762 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
763 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
764 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], THREEBYTEA6_STR);
765 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], THREEBYTEA7_STR);
766 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOP8_MAP_STR);
767 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[7], XOP9_MAP_STR);
768 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[8], XOPA_MAP_STR);
771 void DisassemblerTables::emit(raw_ostream &o) const {
778 raw_string_ostream o1(s1);
779 raw_string_ostream o2(s2);
781 emitInstructionInfo(o, i2);
784 emitContextTable(o, i2);
787 unsigned ModRMTableNum = 0;
789 o << "static const InstrUID modRMTable[] = {\n";
791 std::vector<unsigned> EmptyTable(1, 0);
792 ModRMTable[EmptyTable] = ModRMTableNum;
793 ModRMTableNum += EmptyTable.size();
794 o1 << "/* EmptyTable */\n";
795 o1.indent(i1 * 2) << "0x0,\n";
797 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
808 void DisassemblerTables::setTableFields(ModRMDecision &decision,
809 const ModRMFilter &filter,
812 for (unsigned index = 0; index < 256; ++index) {
813 if (filter.accepts(index)) {
814 if (decision.instructionIDs[index] == uid)
817 if (decision.instructionIDs[index] != 0) {
818 InstructionSpecifier &newInfo =
819 InstructionSpecifiers[uid];
820 InstructionSpecifier &previousInfo =
821 InstructionSpecifiers[decision.instructionIDs[index]];
824 continue; // filtered instructions get lowest priority
826 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
827 newInfo.name == "XCHG32ar" ||
828 newInfo.name == "XCHG32ar64" ||
829 newInfo.name == "XCHG64ar"))
830 continue; // special case for XCHG*ar and NOOP
832 if (outranks(previousInfo.insnContext, newInfo.insnContext))
835 if (previousInfo.insnContext == newInfo.insnContext &&
836 !previousInfo.filtered) {
837 errs() << "Error: Primary decode conflict: ";
838 errs() << newInfo.name << " would overwrite " << previousInfo.name;
840 errs() << "ModRM " << index << "\n";
841 errs() << "Opcode " << (uint16_t)opcode << "\n";
842 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
847 decision.instructionIDs[index] = uid;
852 void DisassemblerTables::setTableFields(OpcodeType type,
853 InstructionContext insnContext,
855 const ModRMFilter &filter,
859 ContextDecision &decision = *Tables[type];
861 for (unsigned index = 0; index < IC_max; ++index) {
862 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
865 if (inheritsFrom((InstructionContext)index,
866 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
867 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],