1 //===- X86DisassemblerTables.cpp - Disassembler tables ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of the disassembler tables.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerTables.h"
18 #include "X86DisassemblerShared.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "llvm/Support/Format.h"
25 using namespace X86Disassembler;
27 /// stringForContext - Returns a string containing the name of a particular
28 /// InstructionContext, usually for diagnostic purposes.
30 /// @param insnContext - The instruction class to transform to a string.
31 /// @return - A statically-allocated string constant that contains the
32 /// name of the instruction class.
33 static inline const char* stringForContext(InstructionContext insnContext) {
34 switch (insnContext) {
36 llvm_unreachable("Unhandled instruction class");
37 #define ENUM_ENTRY(n, r, d) case n: return #n; break;
38 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) ENUM_ENTRY(n##_K_B, r, d)\
39 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)\
40 ENUM_ENTRY(n##_KZ_B, r, d)
47 /// stringForOperandType - Like stringForContext, but for OperandTypes.
48 static inline const char* stringForOperandType(OperandType type) {
51 llvm_unreachable("Unhandled type");
52 #define ENUM_ENTRY(i, d) case i: return #i;
58 /// stringForOperandEncoding - like stringForContext, but for
60 static inline const char* stringForOperandEncoding(OperandEncoding encoding) {
63 llvm_unreachable("Unhandled encoding");
64 #define ENUM_ENTRY(i, d) case i: return #i;
70 /// inheritsFrom - Indicates whether all instructions in one class also belong
73 /// @param child - The class that may be the subset
74 /// @param parent - The class that may be the superset
75 /// @return - True if child is a subset of parent, false otherwise.
76 static inline bool inheritsFrom(InstructionContext child,
77 InstructionContext parent,
78 bool VEX_LIG = false) {
84 return(inheritsFrom(child, IC_64BIT) ||
85 inheritsFrom(child, IC_OPSIZE) ||
86 inheritsFrom(child, IC_ADSIZE) ||
87 inheritsFrom(child, IC_XD) ||
88 inheritsFrom(child, IC_XS));
90 return(inheritsFrom(child, IC_64BIT_REXW) ||
91 inheritsFrom(child, IC_64BIT_OPSIZE) ||
92 inheritsFrom(child, IC_64BIT_ADSIZE) ||
93 inheritsFrom(child, IC_64BIT_XD) ||
94 inheritsFrom(child, IC_64BIT_XS));
96 return inheritsFrom(child, IC_64BIT_OPSIZE);
101 return inheritsFrom(child, IC_64BIT_XD);
103 return inheritsFrom(child, IC_64BIT_XS);
105 return inheritsFrom(child, IC_64BIT_XD_OPSIZE);
107 return inheritsFrom(child, IC_64BIT_XS_OPSIZE);
109 return(inheritsFrom(child, IC_64BIT_REXW_XS) ||
110 inheritsFrom(child, IC_64BIT_REXW_XD) ||
111 inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
112 case IC_64BIT_OPSIZE:
113 return(inheritsFrom(child, IC_64BIT_REXW_OPSIZE));
115 return(inheritsFrom(child, IC_64BIT_REXW_XD));
117 return(inheritsFrom(child, IC_64BIT_REXW_XS));
118 case IC_64BIT_XD_OPSIZE:
119 case IC_64BIT_XS_OPSIZE:
121 case IC_64BIT_REXW_XD:
122 case IC_64BIT_REXW_XS:
123 case IC_64BIT_REXW_OPSIZE:
126 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W)) ||
127 inheritsFrom(child, IC_VEX_W) ||
128 (VEX_LIG && inheritsFrom(child, IC_VEX_L));
130 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS)) ||
131 inheritsFrom(child, IC_VEX_W_XS) ||
132 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XS));
134 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD)) ||
135 inheritsFrom(child, IC_VEX_W_XD) ||
136 (VEX_LIG && inheritsFrom(child, IC_VEX_L_XD));
138 return (VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE)) ||
139 inheritsFrom(child, IC_VEX_W_OPSIZE) ||
140 (VEX_LIG && inheritsFrom(child, IC_VEX_L_OPSIZE));
142 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W);
144 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XS);
146 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_XD);
147 case IC_VEX_W_OPSIZE:
148 return VEX_LIG && inheritsFrom(child, IC_VEX_L_W_OPSIZE);
150 return inheritsFrom(child, IC_VEX_L_W);
152 return inheritsFrom(child, IC_VEX_L_W_XS);
154 return inheritsFrom(child, IC_VEX_L_W_XD);
155 case IC_VEX_L_OPSIZE:
156 return inheritsFrom(child, IC_VEX_L_W_OPSIZE);
160 case IC_VEX_L_W_OPSIZE:
163 return inheritsFrom(child, IC_EVEX_W) ||
164 inheritsFrom(child, IC_EVEX_L_W);
166 return inheritsFrom(child, IC_EVEX_W_XS) ||
167 inheritsFrom(child, IC_EVEX_L_W_XS);
169 return inheritsFrom(child, IC_EVEX_W_XD) ||
170 inheritsFrom(child, IC_EVEX_L_W_XD);
172 return inheritsFrom(child, IC_EVEX_W_OPSIZE) ||
173 inheritsFrom(child, IC_EVEX_L_W_OPSIZE);
177 case IC_EVEX_W_OPSIZE:
182 case IC_EVEX_L_OPSIZE:
187 case IC_EVEX_L_W_OPSIZE:
192 case IC_EVEX_L2_OPSIZE:
195 case IC_EVEX_L2_W_XS:
196 case IC_EVEX_L2_W_XD:
197 case IC_EVEX_L2_W_OPSIZE:
200 return inheritsFrom(child, IC_EVEX_W_K) ||
201 inheritsFrom(child, IC_EVEX_L_W_K);
203 return inheritsFrom(child, IC_EVEX_W_XS_K) ||
204 inheritsFrom(child, IC_EVEX_L_W_XS_K);
206 return inheritsFrom(child, IC_EVEX_W_XD_K) ||
207 inheritsFrom(child, IC_EVEX_L_W_XD_K);
208 case IC_EVEX_OPSIZE_K:
209 case IC_EVEX_OPSIZE_B:
214 case IC_EVEX_W_OPSIZE_K:
215 case IC_EVEX_W_OPSIZE_B:
220 case IC_EVEX_L_OPSIZE_K:
223 case IC_EVEX_W_XS_KZ:
224 case IC_EVEX_W_XD_KZ:
225 case IC_EVEX_W_OPSIZE_KZ:
228 case IC_EVEX_L_XS_KZ:
229 case IC_EVEX_L_XD_KZ:
230 case IC_EVEX_L_OPSIZE_KZ:
233 case IC_EVEX_L_W_XS_K:
234 case IC_EVEX_L_W_XD_K:
235 case IC_EVEX_L_W_OPSIZE_K:
237 case IC_EVEX_L_W_XS_KZ:
238 case IC_EVEX_L_W_XD_KZ:
239 case IC_EVEX_L_W_OPSIZE_KZ:
243 case IC_EVEX_L2_XS_K:
244 case IC_EVEX_L2_XS_B:
245 case IC_EVEX_L2_XD_B:
246 case IC_EVEX_L2_XD_K:
247 case IC_EVEX_L2_OPSIZE_K:
248 case IC_EVEX_L2_OPSIZE_B:
249 case IC_EVEX_L2_OPSIZE_K_B:
251 case IC_EVEX_L2_XS_KZ:
252 case IC_EVEX_L2_XD_KZ:
253 case IC_EVEX_L2_OPSIZE_KZ:
254 case IC_EVEX_L2_OPSIZE_KZ_B:
258 case IC_EVEX_L2_W_XS_K:
259 case IC_EVEX_L2_W_XD_K:
260 case IC_EVEX_L2_W_XD_B:
261 case IC_EVEX_L2_W_OPSIZE_K:
262 case IC_EVEX_L2_W_OPSIZE_B:
263 case IC_EVEX_L2_W_OPSIZE_K_B:
264 case IC_EVEX_L2_W_KZ:
265 case IC_EVEX_L2_W_XS_KZ:
266 case IC_EVEX_L2_W_XD_KZ:
267 case IC_EVEX_L2_W_OPSIZE_KZ:
268 case IC_EVEX_L2_W_OPSIZE_KZ_B:
271 errs() << "Unknown instruction class: " <<
272 stringForContext((InstructionContext)parent) << "\n";
273 llvm_unreachable("Unknown instruction class");
277 /// outranks - Indicates whether, if an instruction has two different applicable
278 /// classes, which class should be preferred when performing decode. This
279 /// imposes a total ordering (ties are resolved toward "lower")
281 /// @param upper - The class that may be preferable
282 /// @param lower - The class that may be less preferable
283 /// @return - True if upper is to be preferred, false otherwise.
284 static inline bool outranks(InstructionContext upper,
285 InstructionContext lower) {
286 assert(upper < IC_max);
287 assert(lower < IC_max);
289 #define ENUM_ENTRY(n, r, d) r,
290 #define ENUM_ENTRY_K_B(n, r, d) ENUM_ENTRY(n, r, d) \
291 ENUM_ENTRY(n##_K_B, r, d) ENUM_ENTRY(n##_KZ_B, r, d) \
292 ENUM_ENTRY(n##_KZ, r, d) ENUM_ENTRY(n##_K, r, d) ENUM_ENTRY(n##_B, r, d)
293 static int ranks[IC_max] = {
297 #undef ENUM_ENTRY_K_B
299 return (ranks[upper] > ranks[lower]);
302 /// getDecisionType - Determines whether a ModRM decision with 255 entries can
303 /// be compacted by eliminating redundant information.
305 /// @param decision - The decision to be compacted.
306 /// @return - The compactest available representation for the decision.
307 static ModRMDecisionType getDecisionType(ModRMDecision &decision) {
308 bool satisfiesOneEntry = true;
309 bool satisfiesSplitRM = true;
310 bool satisfiesSplitReg = true;
311 bool satisfiesSplitMisc = true;
313 for (unsigned index = 0; index < 256; ++index) {
314 if (decision.instructionIDs[index] != decision.instructionIDs[0])
315 satisfiesOneEntry = false;
317 if (((index & 0xc0) == 0xc0) &&
318 (decision.instructionIDs[index] != decision.instructionIDs[0xc0]))
319 satisfiesSplitRM = false;
321 if (((index & 0xc0) != 0xc0) &&
322 (decision.instructionIDs[index] != decision.instructionIDs[0x00]))
323 satisfiesSplitRM = false;
325 if (((index & 0xc0) == 0xc0) &&
326 (decision.instructionIDs[index] != decision.instructionIDs[index&0xf8]))
327 satisfiesSplitReg = false;
329 if (((index & 0xc0) != 0xc0) &&
330 (decision.instructionIDs[index] != decision.instructionIDs[index&0x38]))
331 satisfiesSplitMisc = false;
334 if (satisfiesOneEntry)
335 return MODRM_ONEENTRY;
337 if (satisfiesSplitRM)
338 return MODRM_SPLITRM;
340 if (satisfiesSplitReg && satisfiesSplitMisc)
341 return MODRM_SPLITREG;
343 if (satisfiesSplitMisc)
344 return MODRM_SPLITMISC;
349 /// stringForDecisionType - Returns a statically-allocated string corresponding
350 /// to a particular decision type.
352 /// @param dt - The decision type.
353 /// @return - A pointer to the statically-allocated string (e.g.,
354 /// "MODRM_ONEENTRY" for MODRM_ONEENTRY).
355 static const char* stringForDecisionType(ModRMDecisionType dt) {
356 #define ENUM_ENTRY(n) case n: return #n;
359 llvm_unreachable("Unknown decision type");
365 DisassemblerTables::DisassemblerTables() {
368 for (i = 0; i < array_lengthof(Tables); i++) {
369 Tables[i] = new ContextDecision;
370 memset(Tables[i], 0, sizeof(ContextDecision));
373 HasConflicts = false;
376 DisassemblerTables::~DisassemblerTables() {
379 for (i = 0; i < array_lengthof(Tables); i++)
383 void DisassemblerTables::emitModRMDecision(raw_ostream &o1, raw_ostream &o2,
384 unsigned &i1, unsigned &i2,
385 unsigned &ModRMTableNum,
386 ModRMDecision &decision) const {
387 static uint32_t sTableNumber = 0;
388 static uint32_t sEntryNumber = 1;
389 ModRMDecisionType dt = getDecisionType(decision);
391 if (dt == MODRM_ONEENTRY && decision.instructionIDs[0] == 0)
393 o2.indent(i2) << "{ /* ModRMDecision */" << "\n";
396 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
397 o2.indent(i2) << 0 << " /* EmptyTable */\n";
400 o2.indent(i2) << "}";
404 std::vector<unsigned> ModRMDecision;
408 llvm_unreachable("Unknown decision type");
410 ModRMDecision.push_back(decision.instructionIDs[0]);
413 ModRMDecision.push_back(decision.instructionIDs[0x00]);
414 ModRMDecision.push_back(decision.instructionIDs[0xc0]);
417 for (unsigned index = 0; index < 64; index += 8)
418 ModRMDecision.push_back(decision.instructionIDs[index]);
419 for (unsigned index = 0xc0; index < 256; index += 8)
420 ModRMDecision.push_back(decision.instructionIDs[index]);
422 case MODRM_SPLITMISC:
423 for (unsigned index = 0; index < 64; index += 8)
424 ModRMDecision.push_back(decision.instructionIDs[index]);
425 for (unsigned index = 0xc0; index < 256; ++index)
426 ModRMDecision.push_back(decision.instructionIDs[index]);
429 for (unsigned index = 0; index < 256; ++index)
430 ModRMDecision.push_back(decision.instructionIDs[index]);
434 unsigned &EntryNumber = ModRMTable[ModRMDecision];
435 if (EntryNumber == 0) {
436 EntryNumber = ModRMTableNum;
438 ModRMTableNum += ModRMDecision.size();
439 o1 << "/* Table" << EntryNumber << " */\n";
441 for (std::vector<unsigned>::const_iterator I = ModRMDecision.begin(),
442 E = ModRMDecision.end(); I != E; ++I) {
443 o1.indent(i1 * 2) << format("0x%hx", *I) << ", /* "
444 << InstructionSpecifiers[*I].name << " */\n";
449 o2.indent(i2) << "{ /* struct ModRMDecision */" << "\n";
452 o2.indent(i2) << stringForDecisionType(dt) << "," << "\n";
453 o2.indent(i2) << EntryNumber << " /* Table" << EntryNumber << " */\n";
456 o2.indent(i2) << "}";
460 llvm_unreachable("Unknown decision type");
470 case MODRM_SPLITMISC:
471 sEntryNumber += 8 + 64;
478 // We assume that the index can fit into uint16_t.
479 assert(sEntryNumber < 65536U &&
480 "Index into ModRMDecision is too large for uint16_t!");
485 void DisassemblerTables::emitOpcodeDecision(raw_ostream &o1, raw_ostream &o2,
486 unsigned &i1, unsigned &i2,
487 unsigned &ModRMTableNum,
488 OpcodeDecision &decision) const {
489 o2.indent(i2) << "{ /* struct OpcodeDecision */" << "\n";
491 o2.indent(i2) << "{" << "\n";
494 for (unsigned index = 0; index < 256; ++index) {
497 o2 << "/* 0x" << format("%02hhx", index) << " */" << "\n";
499 emitModRMDecision(o1, o2, i1, i2, ModRMTableNum,
500 decision.modRMDecisions[index]);
509 o2.indent(i2) << "}" << "\n";
511 o2.indent(i2) << "}" << "\n";
514 void DisassemblerTables::emitContextDecision(raw_ostream &o1, raw_ostream &o2,
515 unsigned &i1, unsigned &i2,
516 unsigned &ModRMTableNum,
517 ContextDecision &decision,
518 const char* name) const {
519 o2.indent(i2) << "static const struct ContextDecision " << name << " = {\n";
521 o2.indent(i2) << "{ /* opcodeDecisions */" << "\n";
524 for (unsigned index = 0; index < IC_max; ++index) {
525 o2.indent(i2) << "/* ";
526 o2 << stringForContext((InstructionContext)index);
530 emitOpcodeDecision(o1, o2, i1, i2, ModRMTableNum,
531 decision.opcodeDecisions[index]);
533 if (index + 1 < IC_max)
538 o2.indent(i2) << "}" << "\n";
540 o2.indent(i2) << "};" << "\n";
543 void DisassemblerTables::emitInstructionInfo(raw_ostream &o,
545 unsigned NumInstructions = InstructionSpecifiers.size();
547 o << "static const struct OperandSpecifier x86OperandSets[]["
548 << X86_MAX_OPERANDS << "] = {\n";
550 typedef std::vector<std::pair<const char *, const char *> > OperandListTy;
551 std::map<OperandListTy, unsigned> OperandSets;
553 unsigned OperandSetNum = 0;
554 for (unsigned Index = 0; Index < NumInstructions; ++Index) {
555 OperandListTy OperandList;
557 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
559 const char *Encoding =
560 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[Index]
561 .operands[OperandIndex].encoding);
563 stringForOperandType((OperandType)InstructionSpecifiers[Index]
564 .operands[OperandIndex].type);
565 OperandList.push_back(std::make_pair(Encoding, Type));
567 unsigned &N = OperandSets[OperandList];
568 if (N != 0) continue;
572 o << " { /* " << (OperandSetNum - 1) << " */\n";
573 for (unsigned i = 0, e = OperandList.size(); i != e; ++i) {
574 o << " { " << OperandList[i].first << ", "
575 << OperandList[i].second << " },\n";
581 o.indent(i * 2) << "static const struct InstructionSpecifier ";
582 o << INSTRUCTIONS_STR "[" << InstructionSpecifiers.size() << "] = {\n";
586 for (unsigned index = 0; index < NumInstructions; ++index) {
587 o.indent(i * 2) << "{ /* " << index << " */" << "\n";
590 OperandListTy OperandList;
591 for (unsigned OperandIndex = 0; OperandIndex < X86_MAX_OPERANDS;
593 const char *Encoding =
594 stringForOperandEncoding((OperandEncoding)InstructionSpecifiers[index]
595 .operands[OperandIndex].encoding);
597 stringForOperandType((OperandType)InstructionSpecifiers[index]
598 .operands[OperandIndex].type);
599 OperandList.push_back(std::make_pair(Encoding, Type));
601 o.indent(i * 2) << (OperandSets[OperandList] - 1) << ",\n";
603 o.indent(i * 2) << "/* " << InstructionSpecifiers[index].name << " */";
607 o.indent(i * 2) << "}";
609 if (index + 1 < NumInstructions)
616 o.indent(i * 2) << "};" << "\n";
619 void DisassemblerTables::emitContextTable(raw_ostream &o, unsigned &i) const {
620 const unsigned int tableSize = 16384;
621 o.indent(i * 2) << "static const uint8_t " CONTEXTS_STR
622 "[" << tableSize << "] = {\n";
625 for (unsigned index = 0; index < tableSize; ++index) {
628 if (index & ATTR_EVEX) {
630 if (index & ATTR_EVEXL2)
632 else if (index & ATTR_EVEXL)
634 if (index & ATTR_REXW)
636 if (index & ATTR_OPSIZE)
638 else if (index & ATTR_XD)
640 else if (index & ATTR_XS)
642 if (index & ATTR_EVEXKZ)
644 else if (index & ATTR_EVEXK)
646 if (index & ATTR_EVEXB)
649 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
650 o << "IC_VEX_L_W_OPSIZE";
651 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XD))
652 o << "IC_VEX_L_W_XD";
653 else if ((index & ATTR_VEXL) && (index & ATTR_REXW) && (index & ATTR_XS))
654 o << "IC_VEX_L_W_XS";
655 else if ((index & ATTR_VEXL) && (index & ATTR_REXW))
657 else if ((index & ATTR_VEXL) && (index & ATTR_OPSIZE))
658 o << "IC_VEX_L_OPSIZE";
659 else if ((index & ATTR_VEXL) && (index & ATTR_XD))
661 else if ((index & ATTR_VEXL) && (index & ATTR_XS))
663 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_OPSIZE))
664 o << "IC_VEX_W_OPSIZE";
665 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XD))
667 else if ((index & ATTR_VEX) && (index & ATTR_REXW) && (index & ATTR_XS))
669 else if (index & ATTR_VEXL)
671 else if ((index & ATTR_VEX) && (index & ATTR_REXW))
673 else if ((index & ATTR_VEX) && (index & ATTR_OPSIZE))
674 o << "IC_VEX_OPSIZE";
675 else if ((index & ATTR_VEX) && (index & ATTR_XD))
677 else if ((index & ATTR_VEX) && (index & ATTR_XS))
679 else if (index & ATTR_VEX)
681 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XS))
682 o << "IC_64BIT_REXW_XS";
683 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) && (index & ATTR_XD))
684 o << "IC_64BIT_REXW_XD";
685 else if ((index & ATTR_64BIT) && (index & ATTR_REXW) &&
686 (index & ATTR_OPSIZE))
687 o << "IC_64BIT_REXW_OPSIZE";
688 else if ((index & ATTR_64BIT) && (index & ATTR_XD) && (index & ATTR_OPSIZE))
689 o << "IC_64BIT_XD_OPSIZE";
690 else if ((index & ATTR_64BIT) && (index & ATTR_XS) && (index & ATTR_OPSIZE))
691 o << "IC_64BIT_XS_OPSIZE";
692 else if ((index & ATTR_64BIT) && (index & ATTR_XS))
694 else if ((index & ATTR_64BIT) && (index & ATTR_XD))
696 else if ((index & ATTR_64BIT) && (index & ATTR_OPSIZE))
697 o << "IC_64BIT_OPSIZE";
698 else if ((index & ATTR_64BIT) && (index & ATTR_ADSIZE))
699 o << "IC_64BIT_ADSIZE";
700 else if ((index & ATTR_64BIT) && (index & ATTR_REXW))
701 o << "IC_64BIT_REXW";
702 else if ((index & ATTR_64BIT))
704 else if ((index & ATTR_XS) && (index & ATTR_OPSIZE))
706 else if ((index & ATTR_XD) && (index & ATTR_OPSIZE))
708 else if (index & ATTR_XS)
710 else if (index & ATTR_XD)
712 else if (index & ATTR_OPSIZE)
714 else if (index & ATTR_ADSIZE)
719 if (index < tableSize - 1)
724 o << " /* " << index << " */";
730 o.indent(i * 2) << "};" << "\n";
733 void DisassemblerTables::emitContextDecisions(raw_ostream &o1, raw_ostream &o2,
734 unsigned &i1, unsigned &i2,
735 unsigned &ModRMTableNum) const {
736 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[0], ONEBYTE_STR);
737 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[1], TWOBYTE_STR);
738 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[2], THREEBYTE38_STR);
739 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[3], THREEBYTE3A_STR);
740 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[4], THREEBYTEA6_STR);
741 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[5], THREEBYTEA7_STR);
742 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[6], XOP8_MAP_STR);
743 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[7], XOP9_MAP_STR);
744 emitContextDecision(o1, o2, i1, i2, ModRMTableNum, *Tables[8], XOPA_MAP_STR);
747 void DisassemblerTables::emit(raw_ostream &o) const {
754 raw_string_ostream o1(s1);
755 raw_string_ostream o2(s2);
757 emitInstructionInfo(o, i2);
760 emitContextTable(o, i2);
763 unsigned ModRMTableNum = 0;
765 o << "static const InstrUID modRMTable[] = {\n";
767 std::vector<unsigned> EmptyTable(1, 0);
768 ModRMTable[EmptyTable] = ModRMTableNum;
769 ModRMTableNum += EmptyTable.size();
770 o1 << "/* EmptyTable */\n";
771 o1.indent(i1 * 2) << "0x0,\n";
773 emitContextDecisions(o1, o2, i1, i2, ModRMTableNum);
784 void DisassemblerTables::setTableFields(ModRMDecision &decision,
785 const ModRMFilter &filter,
788 for (unsigned index = 0; index < 256; ++index) {
789 if (filter.accepts(index)) {
790 if (decision.instructionIDs[index] == uid)
793 if (decision.instructionIDs[index] != 0) {
794 InstructionSpecifier &newInfo =
795 InstructionSpecifiers[uid];
796 InstructionSpecifier &previousInfo =
797 InstructionSpecifiers[decision.instructionIDs[index]];
800 continue; // filtered instructions get lowest priority
802 // Instructions such as MOV8ao8 and MOV8ao8_16 differ only in the
803 // presence of the AdSize prefix. However, the disassembler doesn't
804 // care about that difference in the instruction definition; it
805 // handles 16-bit vs. 32-bit addressing for itself based purely
806 // on the 0x67 prefix and the CPU mode. So there's no need to
807 // disambiguate between them; just let them conflict/coexist.
808 if (previousInfo.name + "_16" == newInfo.name)
811 if(previousInfo.name == "NOOP" && (newInfo.name == "XCHG16ar" ||
812 newInfo.name == "XCHG32ar" ||
813 newInfo.name == "XCHG32ar64" ||
814 newInfo.name == "XCHG64ar"))
815 continue; // special case for XCHG*ar and NOOP
817 if (outranks(previousInfo.insnContext, newInfo.insnContext))
820 if (previousInfo.insnContext == newInfo.insnContext &&
821 !previousInfo.filtered) {
822 errs() << "Error: Primary decode conflict: ";
823 errs() << newInfo.name << " would overwrite " << previousInfo.name;
825 errs() << "ModRM " << index << "\n";
826 errs() << "Opcode " << (uint16_t)opcode << "\n";
827 errs() << "Context " << stringForContext(newInfo.insnContext) << "\n";
832 decision.instructionIDs[index] = uid;
837 void DisassemblerTables::setTableFields(OpcodeType type,
838 InstructionContext insnContext,
840 const ModRMFilter &filter,
844 ContextDecision &decision = *Tables[type];
846 for (unsigned index = 0; index < IC_max; ++index) {
847 if (is32bit && inheritsFrom((InstructionContext)index, IC_64BIT))
850 if (inheritsFrom((InstructionContext)index,
851 InstructionSpecifiers[uid].insnContext, ignoresVEX_L))
852 setTableFields(decision.opcodeDecisions[index].modRMDecisions[opcode],