1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
78 // A clone of X86 since we can't depend on something that is generated.
94 MRMXr = 14, MRMXm = 15,
95 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
96 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
97 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
98 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
99 #define MAP(from, to) MRM_##from = to,
106 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6
110 PS = 1, PD = 2, XS = 3, XD = 4
114 VEX = 1, XOP = 2, EVEX = 3
118 OpSize16 = 1, OpSize32 = 2
122 using namespace X86Disassembler;
124 /// isRegFormat - Indicates whether a particular form requires the Mod field of
125 /// the ModR/M byte to be 0b11.
127 /// @param form - The form of the instruction.
128 /// @return - true if the form implies that Mod must be 0b11, false
130 static bool isRegFormat(uint8_t form) {
131 return (form == X86Local::MRMDestReg ||
132 form == X86Local::MRMSrcReg ||
133 form == X86Local::MRMXr ||
134 (form >= X86Local::MRM0r && form <= X86Local::MRM7r));
137 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
138 /// Useful for switch statements and the like.
140 /// @param init - A reference to the BitsInit to be decoded.
141 /// @return - The field, with the first bit in the BitsInit as the lowest
143 static uint8_t byteFromBitsInit(BitsInit &init) {
144 int width = init.getNumBits();
146 assert(width <= 8 && "Field is too large for uint8_t!");
153 for (index = 0; index < width; index++) {
154 if (static_cast<BitInit*>(init.getBit(index))->getValue())
163 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
164 /// name of the field.
166 /// @param rec - The record from which to extract the value.
167 /// @param name - The name of the field in the record.
168 /// @return - The field, as translated by byteFromBitsInit().
169 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
170 BitsInit* bits = rec->getValueAsBitsInit(name);
171 return byteFromBitsInit(*bits);
174 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
175 const CodeGenInstruction &insn,
180 Name = Rec->getName();
181 Spec = &tables.specForUID(UID);
183 if (!Rec->isSubClassOf("X86Inst")) {
184 ShouldBeEmitted = false;
188 OpPrefix = byteFromRec(Rec->getValueAsDef("OpPrefix"), "Value");
189 OpMap = byteFromRec(Rec->getValueAsDef("OpMap"), "Value");
190 Opcode = byteFromRec(Rec, "Opcode");
191 Form = byteFromRec(Rec, "FormBits");
192 Encoding = byteFromRec(Rec->getValueAsDef("OpEnc"), "Value");
194 OpSize = byteFromRec(Rec->getValueAsDef("OpSize"), "Value");
195 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
196 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
197 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
198 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
199 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
200 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
201 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
202 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
203 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
204 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
205 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
206 HasREPPrefix = Rec->getValueAsBit("hasREPPrefix");
207 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
208 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
210 Name = Rec->getName();
211 AsmString = Rec->getValueAsString("AsmString");
213 Operands = &insn.Operands.OperandList;
215 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
217 // Check for 64-bit inst which does not require REX
220 // FIXME: Is there some better way to check for In64BitMode?
221 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
222 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
223 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
224 Predicates[i]->getName().find("In32Bit") != Name.npos) {
228 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
234 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
235 ShouldBeEmitted = false;
239 // Special case since there is no attribute class for 64-bit and VEX
240 if (Name == "VMASKMOVDQU64") {
241 ShouldBeEmitted = false;
245 ShouldBeEmitted = true;
248 void RecognizableInstr::processInstr(DisassemblerTables &tables,
249 const CodeGenInstruction &insn,
252 // Ignore "asm parser only" instructions.
253 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
256 RecognizableInstr recogInstr(tables, insn, uid);
258 if (recogInstr.shouldBeEmitted()) {
259 recogInstr.emitInstructionSpecifier();
260 recogInstr.emitDecodePath(tables);
264 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
265 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
266 (HasEVEX_KZ ? n##_KZ : \
267 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
269 InstructionContext RecognizableInstr::insnContext() const {
270 InstructionContext insnContext;
272 if (Encoding == X86Local::EVEX) {
273 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
274 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
275 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
278 if (HasVEX_LPrefix && HasVEX_WPrefix) {
279 if (OpPrefix == X86Local::PD)
280 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
281 else if (OpPrefix == X86Local::XS)
282 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
283 else if (OpPrefix == X86Local::XD)
284 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
285 else if (OpPrefix == X86Local::PS)
286 insnContext = EVEX_KB(IC_EVEX_L_W);
288 errs() << "Instruction does not use a prefix: " << Name << "\n";
289 llvm_unreachable("Invalid prefix");
291 } else if (HasVEX_LPrefix) {
293 if (OpPrefix == X86Local::PD)
294 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
295 else if (OpPrefix == X86Local::XS)
296 insnContext = EVEX_KB(IC_EVEX_L_XS);
297 else if (OpPrefix == X86Local::XD)
298 insnContext = EVEX_KB(IC_EVEX_L_XD);
299 else if (OpPrefix == X86Local::PS)
300 insnContext = EVEX_KB(IC_EVEX_L);
302 errs() << "Instruction does not use a prefix: " << Name << "\n";
303 llvm_unreachable("Invalid prefix");
306 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
308 if (OpPrefix == X86Local::PD)
309 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
310 else if (OpPrefix == X86Local::XS)
311 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
312 else if (OpPrefix == X86Local::XD)
313 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
314 else if (OpPrefix == X86Local::PS)
315 insnContext = EVEX_KB(IC_EVEX_L2_W);
317 errs() << "Instruction does not use a prefix: " << Name << "\n";
318 llvm_unreachable("Invalid prefix");
320 } else if (HasEVEX_L2Prefix) {
322 if (OpPrefix == X86Local::PD)
323 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
324 else if (OpPrefix == X86Local::XD)
325 insnContext = EVEX_KB(IC_EVEX_L2_XD);
326 else if (OpPrefix == X86Local::XS)
327 insnContext = EVEX_KB(IC_EVEX_L2_XS);
328 else if (OpPrefix == X86Local::PS)
329 insnContext = EVEX_KB(IC_EVEX_L2);
331 errs() << "Instruction does not use a prefix: " << Name << "\n";
332 llvm_unreachable("Invalid prefix");
335 else if (HasVEX_WPrefix) {
337 if (OpPrefix == X86Local::PD)
338 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
339 else if (OpPrefix == X86Local::XS)
340 insnContext = EVEX_KB(IC_EVEX_W_XS);
341 else if (OpPrefix == X86Local::XD)
342 insnContext = EVEX_KB(IC_EVEX_W_XD);
343 else if (OpPrefix == X86Local::PS)
344 insnContext = EVEX_KB(IC_EVEX_W);
346 errs() << "Instruction does not use a prefix: " << Name << "\n";
347 llvm_unreachable("Invalid prefix");
351 else if (OpPrefix == X86Local::PD)
352 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
353 else if (OpPrefix == X86Local::XD)
354 insnContext = EVEX_KB(IC_EVEX_XD);
355 else if (OpPrefix == X86Local::XS)
356 insnContext = EVEX_KB(IC_EVEX_XS);
358 insnContext = EVEX_KB(IC_EVEX);
360 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
361 if (HasVEX_LPrefix && HasVEX_WPrefix) {
362 if (OpPrefix == X86Local::PD)
363 insnContext = IC_VEX_L_W_OPSIZE;
364 else if (OpPrefix == X86Local::XS)
365 insnContext = IC_VEX_L_W_XS;
366 else if (OpPrefix == X86Local::XD)
367 insnContext = IC_VEX_L_W_XD;
368 else if (OpPrefix == X86Local::PS)
369 insnContext = IC_VEX_L_W;
371 errs() << "Instruction does not use a prefix: " << Name << "\n";
372 llvm_unreachable("Invalid prefix");
374 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
375 insnContext = IC_VEX_L_OPSIZE;
376 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix)
377 insnContext = IC_VEX_W_OPSIZE;
378 else if (OpPrefix == X86Local::PD)
379 insnContext = IC_VEX_OPSIZE;
380 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
381 insnContext = IC_VEX_L_XS;
382 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
383 insnContext = IC_VEX_L_XD;
384 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS)
385 insnContext = IC_VEX_W_XS;
386 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD)
387 insnContext = IC_VEX_W_XD;
388 else if (HasVEX_WPrefix && OpPrefix == X86Local::PS)
389 insnContext = IC_VEX_W;
390 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
391 insnContext = IC_VEX_L;
392 else if (OpPrefix == X86Local::XD)
393 insnContext = IC_VEX_XD;
394 else if (OpPrefix == X86Local::XS)
395 insnContext = IC_VEX_XS;
396 else if (OpPrefix == X86Local::PS)
397 insnContext = IC_VEX;
399 errs() << "Instruction does not use a prefix: " << Name << "\n";
400 llvm_unreachable("Invalid prefix");
402 } else if (Is64Bit || HasREX_WPrefix) {
403 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
404 insnContext = IC_64BIT_REXW_OPSIZE;
405 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
406 insnContext = IC_64BIT_XD_OPSIZE;
407 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
408 insnContext = IC_64BIT_XS_OPSIZE;
409 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
410 insnContext = IC_64BIT_OPSIZE;
411 else if (HasAdSizePrefix)
412 insnContext = IC_64BIT_ADSIZE;
413 else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
414 insnContext = IC_64BIT_REXW_XS;
415 else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
416 insnContext = IC_64BIT_REXW_XD;
417 else if (OpPrefix == X86Local::XD)
418 insnContext = IC_64BIT_XD;
419 else if (OpPrefix == X86Local::XS)
420 insnContext = IC_64BIT_XS;
421 else if (HasREX_WPrefix)
422 insnContext = IC_64BIT_REXW;
424 insnContext = IC_64BIT;
426 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
427 insnContext = IC_XD_OPSIZE;
428 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
429 insnContext = IC_XS_OPSIZE;
430 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
431 insnContext = IC_OPSIZE;
432 else if (HasAdSizePrefix)
433 insnContext = IC_ADSIZE;
434 else if (OpPrefix == X86Local::XD)
436 else if (OpPrefix == X86Local::XS || HasREPPrefix)
445 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
446 unsigned &physicalOperandIndex,
447 unsigned &numPhysicalOperands,
448 const unsigned *operandMapping,
449 OperandEncoding (*encodingFromString)
453 if (physicalOperandIndex >= numPhysicalOperands)
456 assert(physicalOperandIndex < numPhysicalOperands);
459 while (operandMapping[operandIndex] != operandIndex) {
460 Spec->operands[operandIndex].encoding = ENCODING_DUP;
461 Spec->operands[operandIndex].type =
462 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
466 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
468 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
470 Spec->operands[operandIndex].type = typeFromString(typeName,
471 HasREX_WPrefix, OpSize);
474 ++physicalOperandIndex;
477 void RecognizableInstr::emitInstructionSpecifier() {
480 Spec->insnContext = insnContext();
482 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
484 unsigned numOperands = OperandList.size();
485 unsigned numPhysicalOperands = 0;
487 // operandMapping maps from operands in OperandList to their originals.
488 // If operandMapping[i] != i, then the entry is a duplicate.
489 unsigned operandMapping[X86_MAX_OPERANDS];
490 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
492 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
493 if (OperandList[operandIndex].Constraints.size()) {
494 const CGIOperandList::ConstraintInfo &Constraint =
495 OperandList[operandIndex].Constraints[0];
496 if (Constraint.isTied()) {
497 operandMapping[operandIndex] = operandIndex;
498 operandMapping[Constraint.getTiedOperand()] = operandIndex;
500 ++numPhysicalOperands;
501 operandMapping[operandIndex] = operandIndex;
504 ++numPhysicalOperands;
505 operandMapping[operandIndex] = operandIndex;
509 #define HANDLE_OPERAND(class) \
510 handleOperand(false, \
512 physicalOperandIndex, \
513 numPhysicalOperands, \
515 class##EncodingFromString);
517 #define HANDLE_OPTIONAL(class) \
518 handleOperand(true, \
520 physicalOperandIndex, \
521 numPhysicalOperands, \
523 class##EncodingFromString);
525 // operandIndex should always be < numOperands
526 unsigned operandIndex = 0;
527 // physicalOperandIndex should always be < numPhysicalOperands
528 unsigned physicalOperandIndex = 0;
531 default: llvm_unreachable("Unhandled form");
532 case X86Local::RawFrmSrc:
533 HANDLE_OPERAND(relocation);
535 case X86Local::RawFrmDst:
536 HANDLE_OPERAND(relocation);
538 case X86Local::RawFrmDstSrc:
539 HANDLE_OPERAND(relocation);
540 HANDLE_OPERAND(relocation);
542 case X86Local::RawFrm:
543 // Operand 1 (optional) is an address or immediate.
544 // Operand 2 (optional) is an immediate.
545 assert(numPhysicalOperands <= 2 &&
546 "Unexpected number of operands for RawFrm");
547 HANDLE_OPTIONAL(relocation)
548 HANDLE_OPTIONAL(immediate)
550 case X86Local::RawFrmMemOffs:
551 // Operand 1 is an address.
552 HANDLE_OPERAND(relocation);
554 case X86Local::AddRegFrm:
555 // Operand 1 is added to the opcode.
556 // Operand 2 (optional) is an address.
557 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
558 "Unexpected number of operands for AddRegFrm");
559 HANDLE_OPERAND(opcodeModifier)
560 HANDLE_OPTIONAL(relocation)
562 case X86Local::MRMDestReg:
563 // Operand 1 is a register operand in the R/M field.
564 // Operand 2 is a register operand in the Reg/Opcode field.
565 // - In AVX, there is a register operand in the VEX.vvvv field here -
566 // Operand 3 (optional) is an immediate.
568 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
569 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
571 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
572 "Unexpected number of operands for MRMDestRegFrm");
574 HANDLE_OPERAND(rmRegister)
577 // FIXME: In AVX, the register below becomes the one encoded
578 // in ModRMVEX and the one above the one in the VEX.VVVV field
579 HANDLE_OPERAND(vvvvRegister)
581 HANDLE_OPERAND(roRegister)
582 HANDLE_OPTIONAL(immediate)
584 case X86Local::MRMDestMem:
585 // Operand 1 is a memory operand (possibly SIB-extended)
586 // Operand 2 is a register operand in the Reg/Opcode field.
587 // - In AVX, there is a register operand in the VEX.vvvv field here -
588 // Operand 3 (optional) is an immediate.
590 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
591 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
593 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
594 "Unexpected number of operands for MRMDestMemFrm");
595 HANDLE_OPERAND(memory)
598 HANDLE_OPERAND(writemaskRegister)
601 // FIXME: In AVX, the register below becomes the one encoded
602 // in ModRMVEX and the one above the one in the VEX.VVVV field
603 HANDLE_OPERAND(vvvvRegister)
605 HANDLE_OPERAND(roRegister)
606 HANDLE_OPTIONAL(immediate)
608 case X86Local::MRMSrcReg:
609 // Operand 1 is a register operand in the Reg/Opcode field.
610 // Operand 2 is a register operand in the R/M field.
611 // - In AVX, there is a register operand in the VEX.vvvv field here -
612 // Operand 3 (optional) is an immediate.
613 // Operand 4 (optional) is an immediate.
615 if (HasVEX_4V || HasVEX_4VOp3)
616 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
617 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
619 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
620 "Unexpected number of operands for MRMSrcRegFrm");
622 HANDLE_OPERAND(roRegister)
625 HANDLE_OPERAND(writemaskRegister)
628 // FIXME: In AVX, the register below becomes the one encoded
629 // in ModRMVEX and the one above the one in the VEX.VVVV field
630 HANDLE_OPERAND(vvvvRegister)
633 HANDLE_OPERAND(immediate)
635 HANDLE_OPERAND(rmRegister)
638 HANDLE_OPERAND(vvvvRegister)
640 if (!HasMemOp4Prefix)
641 HANDLE_OPTIONAL(immediate)
642 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
643 HANDLE_OPTIONAL(immediate)
645 case X86Local::MRMSrcMem:
646 // Operand 1 is a register operand in the Reg/Opcode field.
647 // Operand 2 is a memory operand (possibly SIB-extended)
648 // - In AVX, there is a register operand in the VEX.vvvv field here -
649 // Operand 3 (optional) is an immediate.
651 if (HasVEX_4V || HasVEX_4VOp3)
652 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
653 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
655 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
656 "Unexpected number of operands for MRMSrcMemFrm");
658 HANDLE_OPERAND(roRegister)
661 HANDLE_OPERAND(writemaskRegister)
664 // FIXME: In AVX, the register below becomes the one encoded
665 // in ModRMVEX and the one above the one in the VEX.VVVV field
666 HANDLE_OPERAND(vvvvRegister)
669 HANDLE_OPERAND(immediate)
671 HANDLE_OPERAND(memory)
674 HANDLE_OPERAND(vvvvRegister)
676 if (!HasMemOp4Prefix)
677 HANDLE_OPTIONAL(immediate)
678 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
680 case X86Local::MRMXr:
681 case X86Local::MRM0r:
682 case X86Local::MRM1r:
683 case X86Local::MRM2r:
684 case X86Local::MRM3r:
685 case X86Local::MRM4r:
686 case X86Local::MRM5r:
687 case X86Local::MRM6r:
688 case X86Local::MRM7r:
690 // Operand 1 is a register operand in the R/M field.
691 // Operand 2 (optional) is an immediate or relocation.
692 // Operand 3 (optional) is an immediate.
693 unsigned kOp = (HasEVEX_K) ? 1:0;
694 unsigned Op4v = (HasVEX_4V) ? 1:0;
695 if (numPhysicalOperands > 3 + kOp + Op4v)
696 llvm_unreachable("Unexpected number of operands for MRMnr");
699 HANDLE_OPERAND(vvvvRegister)
702 HANDLE_OPERAND(writemaskRegister)
703 HANDLE_OPTIONAL(rmRegister)
704 HANDLE_OPTIONAL(relocation)
705 HANDLE_OPTIONAL(immediate)
707 case X86Local::MRMXm:
708 case X86Local::MRM0m:
709 case X86Local::MRM1m:
710 case X86Local::MRM2m:
711 case X86Local::MRM3m:
712 case X86Local::MRM4m:
713 case X86Local::MRM5m:
714 case X86Local::MRM6m:
715 case X86Local::MRM7m:
717 // Operand 1 is a memory operand (possibly SIB-extended)
718 // Operand 2 (optional) is an immediate or relocation.
719 unsigned kOp = (HasEVEX_K) ? 1:0;
720 unsigned Op4v = (HasVEX_4V) ? 1:0;
721 if (numPhysicalOperands < 1 + kOp + Op4v ||
722 numPhysicalOperands > 2 + kOp + Op4v)
723 llvm_unreachable("Unexpected number of operands for MRMnm");
726 HANDLE_OPERAND(vvvvRegister)
728 HANDLE_OPERAND(writemaskRegister)
729 HANDLE_OPERAND(memory)
730 HANDLE_OPTIONAL(relocation)
732 case X86Local::RawFrmImm8:
733 // operand 1 is a 16-bit immediate
734 // operand 2 is an 8-bit immediate
735 assert(numPhysicalOperands == 2 &&
736 "Unexpected number of operands for X86Local::RawFrmImm8");
737 HANDLE_OPERAND(immediate)
738 HANDLE_OPERAND(immediate)
740 case X86Local::RawFrmImm16:
741 // operand 1 is a 16-bit immediate
742 // operand 2 is a 16-bit immediate
743 HANDLE_OPERAND(immediate)
744 HANDLE_OPERAND(immediate)
746 case X86Local::MRM_F8:
747 if (Opcode == 0xc6) {
748 assert(numPhysicalOperands == 1 &&
749 "Unexpected number of operands for X86Local::MRM_F8");
750 HANDLE_OPERAND(immediate)
751 } else if (Opcode == 0xc7) {
752 assert(numPhysicalOperands == 1 &&
753 "Unexpected number of operands for X86Local::MRM_F8");
754 HANDLE_OPERAND(relocation)
757 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2:
758 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8:
759 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB:
760 case X86Local::MRM_D0: case X86Local::MRM_D1: case X86Local::MRM_D4:
761 case X86Local::MRM_D5: case X86Local::MRM_D6: case X86Local::MRM_D8:
762 case X86Local::MRM_D9: case X86Local::MRM_DA: case X86Local::MRM_DB:
763 case X86Local::MRM_DC: case X86Local::MRM_DD: case X86Local::MRM_DE:
764 case X86Local::MRM_DF: case X86Local::MRM_E0: case X86Local::MRM_E1:
765 case X86Local::MRM_E2: case X86Local::MRM_E3: case X86Local::MRM_E4:
766 case X86Local::MRM_E5: case X86Local::MRM_E8: case X86Local::MRM_E9:
767 case X86Local::MRM_EA: case X86Local::MRM_EB: case X86Local::MRM_EC:
768 case X86Local::MRM_ED: case X86Local::MRM_EE: case X86Local::MRM_F0:
769 case X86Local::MRM_F1: case X86Local::MRM_F2: case X86Local::MRM_F3:
770 case X86Local::MRM_F4: case X86Local::MRM_F5: case X86Local::MRM_F6:
771 case X86Local::MRM_F7: case X86Local::MRM_F9: case X86Local::MRM_FA:
772 case X86Local::MRM_FB: case X86Local::MRM_FC: case X86Local::MRM_FD:
773 case X86Local::MRM_FE: case X86Local::MRM_FF:
778 #undef HANDLE_OPERAND
779 #undef HANDLE_OPTIONAL
782 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
783 // Special cases where the LLVM tables are not complete
785 #define MAP(from, to) \
786 case X86Local::MRM_##from: \
787 filter = new ExactFilter(0x##from); \
790 OpcodeType opcodeType = (OpcodeType)-1;
792 ModRMFilter* filter = NULL;
793 uint8_t opcodeToSet = 0;
796 default: llvm_unreachable("Invalid map!");
805 default: llvm_unreachable("Unexpected map!");
806 case X86Local::OB: opcodeType = ONEBYTE; break;
807 case X86Local::TB: opcodeType = TWOBYTE; break;
808 case X86Local::T8: opcodeType = THREEBYTE_38; break;
809 case X86Local::TA: opcodeType = THREEBYTE_3A; break;
810 case X86Local::XOP8: opcodeType = XOP8_MAP; break;
811 case X86Local::XOP9: opcodeType = XOP9_MAP; break;
812 case X86Local::XOPA: opcodeType = XOPA_MAP; break;
817 filter = new DumbFilter();
819 case X86Local::MRMDestReg: case X86Local::MRMDestMem:
820 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem:
821 case X86Local::MRMXr: case X86Local::MRMXm:
822 filter = new ModFilter(isRegFormat(Form));
824 case X86Local::MRM0r: case X86Local::MRM1r:
825 case X86Local::MRM2r: case X86Local::MRM3r:
826 case X86Local::MRM4r: case X86Local::MRM5r:
827 case X86Local::MRM6r: case X86Local::MRM7r:
828 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
830 case X86Local::MRM0m: case X86Local::MRM1m:
831 case X86Local::MRM2m: case X86Local::MRM3m:
832 case X86Local::MRM4m: case X86Local::MRM5m:
833 case X86Local::MRM6m: case X86Local::MRM7m:
834 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
839 opcodeToSet = Opcode;
843 assert(opcodeType != (OpcodeType)-1 &&
844 "Opcode type not set");
845 assert(filter && "Filter not set");
847 if (Form == X86Local::AddRegFrm) {
848 assert(((opcodeToSet & 7) == 0) &&
849 "ADDREG_FRM opcode not aligned");
851 uint8_t currentOpcode;
853 for (currentOpcode = opcodeToSet;
854 currentOpcode < opcodeToSet + 8;
856 tables.setTableFields(opcodeType,
860 UID, Is32Bit, IgnoresVEX_L);
862 tables.setTableFields(opcodeType,
866 UID, Is32Bit, IgnoresVEX_L);
874 #define TYPE(str, type) if (s == str) return type;
875 OperandType RecognizableInstr::typeFromString(const std::string &s,
879 // For instructions with a REX_W prefix, a declared 32-bit register encoding
881 TYPE("GR32", TYPE_R32)
883 if(OpSize == X86Local::OpSize16) {
884 // For OpSize16 instructions, a declared 16-bit register or
885 // immediate encoding is special.
886 TYPE("GR16", TYPE_Rv)
887 TYPE("i16imm", TYPE_IMMv)
888 } else if(OpSize == X86Local::OpSize32) {
889 // For OpSize32 instructions, a declared 32-bit register or
890 // immediate encoding is special.
891 TYPE("GR32", TYPE_Rv)
893 TYPE("i16mem", TYPE_Mv)
894 TYPE("i16imm", TYPE_IMM16)
895 TYPE("i16i8imm", TYPE_IMMv)
896 TYPE("GR16", TYPE_R16)
897 TYPE("i32mem", TYPE_Mv)
898 TYPE("i32imm", TYPE_IMMv)
899 TYPE("i32i8imm", TYPE_IMM32)
900 TYPE("u32u8imm", TYPE_IMM32)
901 TYPE("GR32", TYPE_R32)
902 TYPE("GR32orGR64", TYPE_R32)
903 TYPE("i64mem", TYPE_Mv)
904 TYPE("i64i32imm", TYPE_IMM64)
905 TYPE("i64i8imm", TYPE_IMM64)
906 TYPE("GR64", TYPE_R64)
907 TYPE("i8mem", TYPE_M8)
908 TYPE("i8imm", TYPE_IMM8)
910 TYPE("VR128", TYPE_XMM128)
911 TYPE("VR128X", TYPE_XMM128)
912 TYPE("f128mem", TYPE_M128)
913 TYPE("f256mem", TYPE_M256)
914 TYPE("f512mem", TYPE_M512)
915 TYPE("FR64", TYPE_XMM64)
916 TYPE("FR64X", TYPE_XMM64)
917 TYPE("f64mem", TYPE_M64FP)
918 TYPE("sdmem", TYPE_M64FP)
919 TYPE("FR32", TYPE_XMM32)
920 TYPE("FR32X", TYPE_XMM32)
921 TYPE("f32mem", TYPE_M32FP)
922 TYPE("ssmem", TYPE_M32FP)
924 TYPE("i128mem", TYPE_M128)
925 TYPE("i256mem", TYPE_M256)
926 TYPE("i512mem", TYPE_M512)
927 TYPE("i64i32imm_pcrel", TYPE_REL64)
928 TYPE("i16imm_pcrel", TYPE_REL16)
929 TYPE("i32imm_pcrel", TYPE_REL32)
930 TYPE("SSECC", TYPE_IMM3)
931 TYPE("AVXCC", TYPE_IMM5)
932 TYPE("AVX512RC", TYPE_IMM32)
933 TYPE("brtarget", TYPE_RELv)
934 TYPE("uncondbrtarget", TYPE_RELv)
935 TYPE("brtarget8", TYPE_REL8)
936 TYPE("f80mem", TYPE_M80FP)
937 TYPE("lea32mem", TYPE_LEA)
938 TYPE("lea64_32mem", TYPE_LEA)
939 TYPE("lea64mem", TYPE_LEA)
940 TYPE("VR64", TYPE_MM64)
941 TYPE("i64imm", TYPE_IMMv)
942 TYPE("opaque32mem", TYPE_M1616)
943 TYPE("opaque48mem", TYPE_M1632)
944 TYPE("opaque80mem", TYPE_M1664)
945 TYPE("opaque512mem", TYPE_M512)
946 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
947 TYPE("DEBUG_REG", TYPE_DEBUGREG)
948 TYPE("CONTROL_REG", TYPE_CONTROLREG)
949 TYPE("srcidx8", TYPE_SRCIDX8)
950 TYPE("srcidx16", TYPE_SRCIDX16)
951 TYPE("srcidx32", TYPE_SRCIDX32)
952 TYPE("srcidx64", TYPE_SRCIDX64)
953 TYPE("dstidx8", TYPE_DSTIDX8)
954 TYPE("dstidx16", TYPE_DSTIDX16)
955 TYPE("dstidx32", TYPE_DSTIDX32)
956 TYPE("dstidx64", TYPE_DSTIDX64)
957 TYPE("offset8", TYPE_MOFFS8)
958 TYPE("offset16", TYPE_MOFFS16)
959 TYPE("offset32", TYPE_MOFFS32)
960 TYPE("offset64", TYPE_MOFFS64)
961 TYPE("VR256", TYPE_XMM256)
962 TYPE("VR256X", TYPE_XMM256)
963 TYPE("VR512", TYPE_XMM512)
964 TYPE("VK1", TYPE_VK1)
965 TYPE("VK1WM", TYPE_VK1)
966 TYPE("VK8", TYPE_VK8)
967 TYPE("VK8WM", TYPE_VK8)
968 TYPE("VK16", TYPE_VK16)
969 TYPE("VK16WM", TYPE_VK16)
970 TYPE("GR16_NOAX", TYPE_Rv)
971 TYPE("GR32_NOAX", TYPE_Rv)
972 TYPE("GR64_NOAX", TYPE_R64)
973 TYPE("vx32mem", TYPE_M32)
974 TYPE("vy32mem", TYPE_M32)
975 TYPE("vz32mem", TYPE_M32)
976 TYPE("vx64mem", TYPE_M64)
977 TYPE("vy64mem", TYPE_M64)
978 TYPE("vy64xmem", TYPE_M64)
979 TYPE("vz64mem", TYPE_M64)
980 errs() << "Unhandled type string " << s << "\n";
981 llvm_unreachable("Unhandled type string");
985 #define ENCODING(str, encoding) if (s == str) return encoding;
987 RecognizableInstr::immediateEncodingFromString(const std::string &s,
989 if(OpSize != X86Local::OpSize16) {
990 // For instructions without an OpSize prefix, a declared 16-bit register or
991 // immediate encoding is special.
992 ENCODING("i16imm", ENCODING_IW)
994 ENCODING("i32i8imm", ENCODING_IB)
995 ENCODING("u32u8imm", ENCODING_IB)
996 ENCODING("SSECC", ENCODING_IB)
997 ENCODING("AVXCC", ENCODING_IB)
998 ENCODING("AVX512RC", ENCODING_IB)
999 ENCODING("i16imm", ENCODING_Iv)
1000 ENCODING("i16i8imm", ENCODING_IB)
1001 ENCODING("i32imm", ENCODING_Iv)
1002 ENCODING("i64i32imm", ENCODING_ID)
1003 ENCODING("i64i8imm", ENCODING_IB)
1004 ENCODING("i8imm", ENCODING_IB)
1005 // This is not a typo. Instructions like BLENDVPD put
1006 // register IDs in 8-bit immediates nowadays.
1007 ENCODING("FR32", ENCODING_IB)
1008 ENCODING("FR64", ENCODING_IB)
1009 ENCODING("VR128", ENCODING_IB)
1010 ENCODING("VR256", ENCODING_IB)
1011 ENCODING("FR32X", ENCODING_IB)
1012 ENCODING("FR64X", ENCODING_IB)
1013 ENCODING("VR128X", ENCODING_IB)
1014 ENCODING("VR256X", ENCODING_IB)
1015 ENCODING("VR512", ENCODING_IB)
1016 errs() << "Unhandled immediate encoding " << s << "\n";
1017 llvm_unreachable("Unhandled immediate encoding");
1021 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1023 ENCODING("RST", ENCODING_FP)
1024 ENCODING("GR16", ENCODING_RM)
1025 ENCODING("GR32", ENCODING_RM)
1026 ENCODING("GR32orGR64", ENCODING_RM)
1027 ENCODING("GR64", ENCODING_RM)
1028 ENCODING("GR8", ENCODING_RM)
1029 ENCODING("VR128", ENCODING_RM)
1030 ENCODING("VR128X", ENCODING_RM)
1031 ENCODING("FR64", ENCODING_RM)
1032 ENCODING("FR32", ENCODING_RM)
1033 ENCODING("FR64X", ENCODING_RM)
1034 ENCODING("FR32X", ENCODING_RM)
1035 ENCODING("VR64", ENCODING_RM)
1036 ENCODING("VR256", ENCODING_RM)
1037 ENCODING("VR256X", ENCODING_RM)
1038 ENCODING("VR512", ENCODING_RM)
1039 ENCODING("VK1", ENCODING_RM)
1040 ENCODING("VK8", ENCODING_RM)
1041 ENCODING("VK16", ENCODING_RM)
1042 errs() << "Unhandled R/M register encoding " << s << "\n";
1043 llvm_unreachable("Unhandled R/M register encoding");
1047 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1049 ENCODING("GR16", ENCODING_REG)
1050 ENCODING("GR32", ENCODING_REG)
1051 ENCODING("GR32orGR64", ENCODING_REG)
1052 ENCODING("GR64", ENCODING_REG)
1053 ENCODING("GR8", ENCODING_REG)
1054 ENCODING("VR128", ENCODING_REG)
1055 ENCODING("FR64", ENCODING_REG)
1056 ENCODING("FR32", ENCODING_REG)
1057 ENCODING("VR64", ENCODING_REG)
1058 ENCODING("SEGMENT_REG", ENCODING_REG)
1059 ENCODING("DEBUG_REG", ENCODING_REG)
1060 ENCODING("CONTROL_REG", ENCODING_REG)
1061 ENCODING("VR256", ENCODING_REG)
1062 ENCODING("VR256X", ENCODING_REG)
1063 ENCODING("VR128X", ENCODING_REG)
1064 ENCODING("FR64X", ENCODING_REG)
1065 ENCODING("FR32X", ENCODING_REG)
1066 ENCODING("VR512", ENCODING_REG)
1067 ENCODING("VK1", ENCODING_REG)
1068 ENCODING("VK8", ENCODING_REG)
1069 ENCODING("VK16", ENCODING_REG)
1070 ENCODING("VK1WM", ENCODING_REG)
1071 ENCODING("VK8WM", ENCODING_REG)
1072 ENCODING("VK16WM", ENCODING_REG)
1073 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1074 llvm_unreachable("Unhandled reg/opcode register encoding");
1078 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1080 ENCODING("GR32", ENCODING_VVVV)
1081 ENCODING("GR64", ENCODING_VVVV)
1082 ENCODING("FR32", ENCODING_VVVV)
1083 ENCODING("FR64", ENCODING_VVVV)
1084 ENCODING("VR128", ENCODING_VVVV)
1085 ENCODING("VR256", ENCODING_VVVV)
1086 ENCODING("FR32X", ENCODING_VVVV)
1087 ENCODING("FR64X", ENCODING_VVVV)
1088 ENCODING("VR128X", ENCODING_VVVV)
1089 ENCODING("VR256X", ENCODING_VVVV)
1090 ENCODING("VR512", ENCODING_VVVV)
1091 ENCODING("VK1", ENCODING_VVVV)
1092 ENCODING("VK8", ENCODING_VVVV)
1093 ENCODING("VK16", ENCODING_VVVV)
1094 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1095 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1099 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1101 ENCODING("VK1WM", ENCODING_WRITEMASK)
1102 ENCODING("VK8WM", ENCODING_WRITEMASK)
1103 ENCODING("VK16WM", ENCODING_WRITEMASK)
1104 errs() << "Unhandled mask register encoding " << s << "\n";
1105 llvm_unreachable("Unhandled mask register encoding");
1109 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1111 ENCODING("i16mem", ENCODING_RM)
1112 ENCODING("i32mem", ENCODING_RM)
1113 ENCODING("i64mem", ENCODING_RM)
1114 ENCODING("i8mem", ENCODING_RM)
1115 ENCODING("ssmem", ENCODING_RM)
1116 ENCODING("sdmem", ENCODING_RM)
1117 ENCODING("f128mem", ENCODING_RM)
1118 ENCODING("f256mem", ENCODING_RM)
1119 ENCODING("f512mem", ENCODING_RM)
1120 ENCODING("f64mem", ENCODING_RM)
1121 ENCODING("f32mem", ENCODING_RM)
1122 ENCODING("i128mem", ENCODING_RM)
1123 ENCODING("i256mem", ENCODING_RM)
1124 ENCODING("i512mem", ENCODING_RM)
1125 ENCODING("f80mem", ENCODING_RM)
1126 ENCODING("lea32mem", ENCODING_RM)
1127 ENCODING("lea64_32mem", ENCODING_RM)
1128 ENCODING("lea64mem", ENCODING_RM)
1129 ENCODING("opaque32mem", ENCODING_RM)
1130 ENCODING("opaque48mem", ENCODING_RM)
1131 ENCODING("opaque80mem", ENCODING_RM)
1132 ENCODING("opaque512mem", ENCODING_RM)
1133 ENCODING("vx32mem", ENCODING_RM)
1134 ENCODING("vy32mem", ENCODING_RM)
1135 ENCODING("vz32mem", ENCODING_RM)
1136 ENCODING("vx64mem", ENCODING_RM)
1137 ENCODING("vy64mem", ENCODING_RM)
1138 ENCODING("vy64xmem", ENCODING_RM)
1139 ENCODING("vz64mem", ENCODING_RM)
1140 errs() << "Unhandled memory encoding " << s << "\n";
1141 llvm_unreachable("Unhandled memory encoding");
1145 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1147 if(OpSize != X86Local::OpSize16) {
1148 // For instructions without an OpSize prefix, a declared 16-bit register or
1149 // immediate encoding is special.
1150 ENCODING("i16imm", ENCODING_IW)
1152 ENCODING("i16imm", ENCODING_Iv)
1153 ENCODING("i16i8imm", ENCODING_IB)
1154 ENCODING("i32imm", ENCODING_Iv)
1155 ENCODING("i32i8imm", ENCODING_IB)
1156 ENCODING("i64i32imm", ENCODING_ID)
1157 ENCODING("i64i8imm", ENCODING_IB)
1158 ENCODING("i8imm", ENCODING_IB)
1159 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1160 ENCODING("i16imm_pcrel", ENCODING_IW)
1161 ENCODING("i32imm_pcrel", ENCODING_ID)
1162 ENCODING("brtarget", ENCODING_Iv)
1163 ENCODING("brtarget8", ENCODING_IB)
1164 ENCODING("i64imm", ENCODING_IO)
1165 ENCODING("offset8", ENCODING_Ia)
1166 ENCODING("offset16", ENCODING_Ia)
1167 ENCODING("offset32", ENCODING_Ia)
1168 ENCODING("offset64", ENCODING_Ia)
1169 ENCODING("srcidx8", ENCODING_SI)
1170 ENCODING("srcidx16", ENCODING_SI)
1171 ENCODING("srcidx32", ENCODING_SI)
1172 ENCODING("srcidx64", ENCODING_SI)
1173 ENCODING("dstidx8", ENCODING_DI)
1174 ENCODING("dstidx16", ENCODING_DI)
1175 ENCODING("dstidx32", ENCODING_DI)
1176 ENCODING("dstidx64", ENCODING_DI)
1177 errs() << "Unhandled relocation encoding " << s << "\n";
1178 llvm_unreachable("Unhandled relocation encoding");
1182 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1184 ENCODING("GR32", ENCODING_Rv)
1185 ENCODING("GR64", ENCODING_RO)
1186 ENCODING("GR16", ENCODING_Rv)
1187 ENCODING("GR8", ENCODING_RB)
1188 ENCODING("GR16_NOAX", ENCODING_Rv)
1189 ENCODING("GR32_NOAX", ENCODING_Rv)
1190 ENCODING("GR64_NOAX", ENCODING_RO)
1191 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1192 llvm_unreachable("Unhandled opcode modifier encoding");