1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
135 #define THREE_BYTE_38_EXTENSION_TABLES \
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
233 SegOvr = byteFromRec(Rec, "SegOvrBits");
235 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
236 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
237 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
238 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
239 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
240 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
242 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
243 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
244 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
245 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
247 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
248 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
249 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
250 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
252 Name = Rec->getName();
253 AsmString = Rec->getValueAsString("AsmString");
255 Operands = &insn.Operands.OperandList;
257 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
258 (Name.find("CRC32") != Name.npos);
259 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
261 // Check for 64-bit inst which does not require REX
264 // FIXME: Is there some better way to check for In64BitMode?
265 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
266 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
267 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
268 Predicates[i]->getName().find("In32Bit") != Name.npos) {
272 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
277 // FIXME: These instructions aren't marked as 64-bit in any way
278 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
279 Rec->getName().find("MOV64") != Name.npos ||
280 Rec->getName().find("PUSH64") != Name.npos ||
281 Rec->getName().find("POP64") != Name.npos;
283 ShouldBeEmitted = true;
286 void RecognizableInstr::processInstr(DisassemblerTables &tables,
287 const CodeGenInstruction &insn,
290 // Ignore "asm parser only" instructions.
291 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
294 RecognizableInstr recogInstr(tables, insn, uid);
296 recogInstr.emitInstructionSpecifier();
298 if (recogInstr.shouldBeEmitted())
299 recogInstr.emitDecodePath(tables);
302 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
303 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
304 (HasEVEX_KZ ? n##_KZ : \
305 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
307 InstructionContext RecognizableInstr::insnContext() const {
308 InstructionContext insnContext;
311 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
312 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
313 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
316 if (HasVEX_LPrefix && HasVEX_WPrefix) {
318 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
319 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
320 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
321 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
322 Prefix == X86Local::TAXD)
323 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
325 insnContext = EVEX_KB(IC_EVEX_L_W);
326 } else if (HasVEX_LPrefix) {
329 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
330 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
331 insnContext = EVEX_KB(IC_EVEX_L_XS);
332 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
333 Prefix == X86Local::TAXD)
334 insnContext = EVEX_KB(IC_EVEX_L_XD);
336 insnContext = EVEX_KB(IC_EVEX_L);
338 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
341 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
342 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
343 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
344 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
345 Prefix == X86Local::TAXD)
346 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
348 insnContext = EVEX_KB(IC_EVEX_L2_W);
349 } else if (HasEVEX_L2Prefix) {
352 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
353 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
354 Prefix == X86Local::TAXD)
355 insnContext = EVEX_KB(IC_EVEX_L2_XD);
356 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
357 insnContext = EVEX_KB(IC_EVEX_L2_XS);
359 insnContext = EVEX_KB(IC_EVEX_L2);
361 else if (HasVEX_WPrefix) {
364 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
365 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
366 insnContext = EVEX_KB(IC_EVEX_W_XS);
367 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
368 Prefix == X86Local::TAXD)
369 insnContext = EVEX_KB(IC_EVEX_W_XD);
371 insnContext = EVEX_KB(IC_EVEX_W);
374 else if (HasOpSizePrefix)
375 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
376 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
377 Prefix == X86Local::TAXD)
378 insnContext = EVEX_KB(IC_EVEX_XD);
379 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
380 insnContext = EVEX_KB(IC_EVEX_XS);
382 insnContext = EVEX_KB(IC_EVEX);
384 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
385 if (HasVEX_LPrefix && HasVEX_WPrefix) {
387 insnContext = IC_VEX_L_W_OPSIZE;
388 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
389 insnContext = IC_VEX_L_W_XS;
390 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
391 Prefix == X86Local::TAXD)
392 insnContext = IC_VEX_L_W_XD;
394 insnContext = IC_VEX_L_W;
395 } else if (HasOpSizePrefix && HasVEX_LPrefix)
396 insnContext = IC_VEX_L_OPSIZE;
397 else if (HasOpSizePrefix && HasVEX_WPrefix)
398 insnContext = IC_VEX_W_OPSIZE;
399 else if (HasOpSizePrefix)
400 insnContext = IC_VEX_OPSIZE;
401 else if (HasVEX_LPrefix &&
402 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
403 insnContext = IC_VEX_L_XS;
404 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
405 Prefix == X86Local::T8XD ||
406 Prefix == X86Local::TAXD))
407 insnContext = IC_VEX_L_XD;
408 else if (HasVEX_WPrefix &&
409 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
410 insnContext = IC_VEX_W_XS;
411 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
412 Prefix == X86Local::T8XD ||
413 Prefix == X86Local::TAXD))
414 insnContext = IC_VEX_W_XD;
415 else if (HasVEX_WPrefix)
416 insnContext = IC_VEX_W;
417 else if (HasVEX_LPrefix)
418 insnContext = IC_VEX_L;
419 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
420 Prefix == X86Local::TAXD)
421 insnContext = IC_VEX_XD;
422 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
423 insnContext = IC_VEX_XS;
425 insnContext = IC_VEX;
426 } else if (Is64Bit || HasREX_WPrefix) {
427 if (HasREX_WPrefix && HasOpSizePrefix)
428 insnContext = IC_64BIT_REXW_OPSIZE;
429 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
430 Prefix == X86Local::T8XD ||
431 Prefix == X86Local::TAXD))
432 insnContext = IC_64BIT_XD_OPSIZE;
433 else if (HasOpSizePrefix &&
434 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
435 insnContext = IC_64BIT_XS_OPSIZE;
436 else if (HasOpSizePrefix)
437 insnContext = IC_64BIT_OPSIZE;
438 else if (HasAdSizePrefix)
439 insnContext = IC_64BIT_ADSIZE;
440 else if (HasREX_WPrefix &&
441 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
442 insnContext = IC_64BIT_REXW_XS;
443 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
444 Prefix == X86Local::T8XD ||
445 Prefix == X86Local::TAXD))
446 insnContext = IC_64BIT_REXW_XD;
447 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
448 Prefix == X86Local::TAXD)
449 insnContext = IC_64BIT_XD;
450 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
451 insnContext = IC_64BIT_XS;
452 else if (HasREX_WPrefix)
453 insnContext = IC_64BIT_REXW;
455 insnContext = IC_64BIT;
457 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
458 Prefix == X86Local::T8XD ||
459 Prefix == X86Local::TAXD))
460 insnContext = IC_XD_OPSIZE;
461 else if (HasOpSizePrefix &&
462 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
463 insnContext = IC_XS_OPSIZE;
464 else if (HasOpSizePrefix)
465 insnContext = IC_OPSIZE;
466 else if (HasAdSizePrefix)
467 insnContext = IC_ADSIZE;
468 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
469 Prefix == X86Local::TAXD)
471 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
472 Prefix == X86Local::REP)
481 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
486 // Filter out intrinsics
488 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
490 if (Form == X86Local::Pseudo ||
491 (IsCodeGenOnly && Name.find("_REV") == Name.npos &&
492 Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos))
493 return FILTER_STRONG;
496 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
497 // printed as a separate "instruction".
499 // Filter out instructions with segment override prefixes.
500 // They're too messy to handle now and we'll special case them if needed.
503 return FILTER_STRONG;
511 // Filter out instructions with a LOCK prefix;
512 // prefer forms that do not have the prefix
516 // Filter out alternate forms of AVX instructions
517 if (Name.find("_alt") != Name.npos ||
518 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
519 Name.find("_64mr") != Name.npos ||
520 Name.find("rr64") != Name.npos)
525 if (Name == "PUSH64i16" ||
526 Name == "MOVPQI2QImr" ||
527 Name == "VMOVPQI2QImr" ||
528 Name == "VMASKMOVDQU64")
531 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
532 // For now, just prefer the REP versions.
533 if (Name == "XACQUIRE_PREFIX" ||
534 Name == "XRELEASE_PREFIX")
537 return FILTER_NORMAL;
540 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
541 unsigned &physicalOperandIndex,
542 unsigned &numPhysicalOperands,
543 const unsigned *operandMapping,
544 OperandEncoding (*encodingFromString)
546 bool hasOpSizePrefix)) {
548 if (physicalOperandIndex >= numPhysicalOperands)
551 assert(physicalOperandIndex < numPhysicalOperands);
554 while (operandMapping[operandIndex] != operandIndex) {
555 Spec->operands[operandIndex].encoding = ENCODING_DUP;
556 Spec->operands[operandIndex].type =
557 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
561 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
563 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
565 Spec->operands[operandIndex].type = typeFromString(typeName,
571 ++physicalOperandIndex;
574 void RecognizableInstr::emitInstructionSpecifier() {
577 if (!ShouldBeEmitted)
582 Spec->filtered = true;
585 ShouldBeEmitted = false;
591 Spec->insnContext = insnContext();
593 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
595 unsigned numOperands = OperandList.size();
596 unsigned numPhysicalOperands = 0;
598 // operandMapping maps from operands in OperandList to their originals.
599 // If operandMapping[i] != i, then the entry is a duplicate.
600 unsigned operandMapping[X86_MAX_OPERANDS];
601 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
603 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
604 if (OperandList[operandIndex].Constraints.size()) {
605 const CGIOperandList::ConstraintInfo &Constraint =
606 OperandList[operandIndex].Constraints[0];
607 if (Constraint.isTied()) {
608 operandMapping[operandIndex] = operandIndex;
609 operandMapping[Constraint.getTiedOperand()] = operandIndex;
611 ++numPhysicalOperands;
612 operandMapping[operandIndex] = operandIndex;
615 ++numPhysicalOperands;
616 operandMapping[operandIndex] = operandIndex;
620 #define HANDLE_OPERAND(class) \
621 handleOperand(false, \
623 physicalOperandIndex, \
624 numPhysicalOperands, \
626 class##EncodingFromString);
628 #define HANDLE_OPTIONAL(class) \
629 handleOperand(true, \
631 physicalOperandIndex, \
632 numPhysicalOperands, \
634 class##EncodingFromString);
636 // operandIndex should always be < numOperands
637 unsigned operandIndex = 0;
638 // physicalOperandIndex should always be < numPhysicalOperands
639 unsigned physicalOperandIndex = 0;
642 case X86Local::RawFrm:
643 // Operand 1 (optional) is an address or immediate.
644 // Operand 2 (optional) is an immediate.
645 assert(numPhysicalOperands <= 2 &&
646 "Unexpected number of operands for RawFrm");
647 HANDLE_OPTIONAL(relocation)
648 HANDLE_OPTIONAL(immediate)
650 case X86Local::AddRegFrm:
651 // Operand 1 is added to the opcode.
652 // Operand 2 (optional) is an address.
653 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
654 "Unexpected number of operands for AddRegFrm");
655 HANDLE_OPERAND(opcodeModifier)
656 HANDLE_OPTIONAL(relocation)
658 case X86Local::MRMDestReg:
659 // Operand 1 is a register operand in the R/M field.
660 // Operand 2 is a register operand in the Reg/Opcode field.
661 // - In AVX, there is a register operand in the VEX.vvvv field here -
662 // Operand 3 (optional) is an immediate.
664 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
665 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
667 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
668 "Unexpected number of operands for MRMDestRegFrm");
670 HANDLE_OPERAND(rmRegister)
673 // FIXME: In AVX, the register below becomes the one encoded
674 // in ModRMVEX and the one above the one in the VEX.VVVV field
675 HANDLE_OPERAND(vvvvRegister)
677 HANDLE_OPERAND(roRegister)
678 HANDLE_OPTIONAL(immediate)
680 case X86Local::MRMDestMem:
681 // Operand 1 is a memory operand (possibly SIB-extended)
682 // Operand 2 is a register operand in the Reg/Opcode field.
683 // - In AVX, there is a register operand in the VEX.vvvv field here -
684 // Operand 3 (optional) is an immediate.
686 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
687 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
689 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
690 "Unexpected number of operands for MRMDestMemFrm");
691 HANDLE_OPERAND(memory)
694 HANDLE_OPERAND(writemaskRegister)
697 // FIXME: In AVX, the register below becomes the one encoded
698 // in ModRMVEX and the one above the one in the VEX.VVVV field
699 HANDLE_OPERAND(vvvvRegister)
701 HANDLE_OPERAND(roRegister)
702 HANDLE_OPTIONAL(immediate)
704 case X86Local::MRMSrcReg:
705 // Operand 1 is a register operand in the Reg/Opcode field.
706 // Operand 2 is a register operand in the R/M field.
707 // - In AVX, there is a register operand in the VEX.vvvv field here -
708 // Operand 3 (optional) is an immediate.
709 // Operand 4 (optional) is an immediate.
711 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
712 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
713 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
715 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
716 "Unexpected number of operands for MRMSrcRegFrm");
718 HANDLE_OPERAND(roRegister)
721 HANDLE_OPERAND(writemaskRegister)
724 // FIXME: In AVX, the register below becomes the one encoded
725 // in ModRMVEX and the one above the one in the VEX.VVVV field
726 HANDLE_OPERAND(vvvvRegister)
729 HANDLE_OPERAND(immediate)
731 HANDLE_OPERAND(rmRegister)
733 if (HasVEX_4VOp3Prefix)
734 HANDLE_OPERAND(vvvvRegister)
736 if (!HasMemOp4Prefix)
737 HANDLE_OPTIONAL(immediate)
738 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
739 HANDLE_OPTIONAL(immediate)
741 case X86Local::MRMSrcMem:
742 // Operand 1 is a register operand in the Reg/Opcode field.
743 // Operand 2 is a memory operand (possibly SIB-extended)
744 // - In AVX, there is a register operand in the VEX.vvvv field here -
745 // Operand 3 (optional) is an immediate.
747 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
748 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
749 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
751 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
752 "Unexpected number of operands for MRMSrcMemFrm");
754 HANDLE_OPERAND(roRegister)
757 HANDLE_OPERAND(writemaskRegister)
760 // FIXME: In AVX, the register below becomes the one encoded
761 // in ModRMVEX and the one above the one in the VEX.VVVV field
762 HANDLE_OPERAND(vvvvRegister)
765 HANDLE_OPERAND(immediate)
767 HANDLE_OPERAND(memory)
769 if (HasVEX_4VOp3Prefix)
770 HANDLE_OPERAND(vvvvRegister)
772 if (!HasMemOp4Prefix)
773 HANDLE_OPTIONAL(immediate)
774 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
776 case X86Local::MRM0r:
777 case X86Local::MRM1r:
778 case X86Local::MRM2r:
779 case X86Local::MRM3r:
780 case X86Local::MRM4r:
781 case X86Local::MRM5r:
782 case X86Local::MRM6r:
783 case X86Local::MRM7r:
785 // Operand 1 is a register operand in the R/M field.
786 // Operand 2 (optional) is an immediate or relocation.
787 // Operand 3 (optional) is an immediate.
788 unsigned kOp = (HasEVEX_K) ? 1:0;
789 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
790 if (numPhysicalOperands > 3 + kOp + Op4v)
791 llvm_unreachable("Unexpected number of operands for MRMnr");
794 HANDLE_OPERAND(vvvvRegister)
797 HANDLE_OPERAND(writemaskRegister)
798 HANDLE_OPTIONAL(rmRegister)
799 HANDLE_OPTIONAL(relocation)
800 HANDLE_OPTIONAL(immediate)
802 case X86Local::MRM0m:
803 case X86Local::MRM1m:
804 case X86Local::MRM2m:
805 case X86Local::MRM3m:
806 case X86Local::MRM4m:
807 case X86Local::MRM5m:
808 case X86Local::MRM6m:
809 case X86Local::MRM7m:
811 // Operand 1 is a memory operand (possibly SIB-extended)
812 // Operand 2 (optional) is an immediate or relocation.
813 unsigned kOp = (HasEVEX_K) ? 1:0;
814 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
815 if (numPhysicalOperands < 1 + kOp + Op4v ||
816 numPhysicalOperands > 2 + kOp + Op4v)
817 llvm_unreachable("Unexpected number of operands for MRMnm");
820 HANDLE_OPERAND(vvvvRegister)
822 HANDLE_OPERAND(writemaskRegister)
823 HANDLE_OPERAND(memory)
824 HANDLE_OPTIONAL(relocation)
826 case X86Local::RawFrmImm8:
827 // operand 1 is a 16-bit immediate
828 // operand 2 is an 8-bit immediate
829 assert(numPhysicalOperands == 2 &&
830 "Unexpected number of operands for X86Local::RawFrmImm8");
831 HANDLE_OPERAND(immediate)
832 HANDLE_OPERAND(immediate)
834 case X86Local::RawFrmImm16:
835 // operand 1 is a 16-bit immediate
836 // operand 2 is a 16-bit immediate
837 HANDLE_OPERAND(immediate)
838 HANDLE_OPERAND(immediate)
840 case X86Local::MRM_F8:
841 if (Opcode == 0xc6) {
842 assert(numPhysicalOperands == 1 &&
843 "Unexpected number of operands for X86Local::MRM_F8");
844 HANDLE_OPERAND(immediate)
845 } else if (Opcode == 0xc7) {
846 assert(numPhysicalOperands == 1 &&
847 "Unexpected number of operands for X86Local::MRM_F8");
848 HANDLE_OPERAND(relocation)
851 case X86Local::MRMInitReg:
856 #undef HANDLE_OPERAND
857 #undef HANDLE_OPTIONAL
860 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
861 // Special cases where the LLVM tables are not complete
863 #define MAP(from, to) \
864 case X86Local::MRM_##from: \
865 filter = new ExactFilter(0x##from); \
868 OpcodeType opcodeType = (OpcodeType)-1;
870 ModRMFilter* filter = NULL;
871 uint8_t opcodeToSet = 0;
874 default: llvm_unreachable("Invalid prefix!");
875 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
879 opcodeType = TWOBYTE;
883 if (needsModRMForDecode(Form))
884 filter = new ModFilter(isRegFormat(Form));
886 filter = new DumbFilter();
888 #define EXTENSION_TABLE(n) case 0x##n:
889 TWO_BYTE_EXTENSION_TABLES
890 #undef EXTENSION_TABLE
893 llvm_unreachable("Unhandled two-byte extended opcode");
894 case X86Local::MRM0r:
895 case X86Local::MRM1r:
896 case X86Local::MRM2r:
897 case X86Local::MRM3r:
898 case X86Local::MRM4r:
899 case X86Local::MRM5r:
900 case X86Local::MRM6r:
901 case X86Local::MRM7r:
902 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
904 case X86Local::MRM0m:
905 case X86Local::MRM1m:
906 case X86Local::MRM2m:
907 case X86Local::MRM3m:
908 case X86Local::MRM4m:
909 case X86Local::MRM5m:
910 case X86Local::MRM6m:
911 case X86Local::MRM7m:
912 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
918 opcodeToSet = Opcode;
923 opcodeType = THREEBYTE_38;
926 if (needsModRMForDecode(Form))
927 filter = new ModFilter(isRegFormat(Form));
929 filter = new DumbFilter();
931 #define EXTENSION_TABLE(n) case 0x##n:
932 THREE_BYTE_38_EXTENSION_TABLES
933 #undef EXTENSION_TABLE
936 llvm_unreachable("Unhandled two-byte extended opcode");
937 case X86Local::MRM0r:
938 case X86Local::MRM1r:
939 case X86Local::MRM2r:
940 case X86Local::MRM3r:
941 case X86Local::MRM4r:
942 case X86Local::MRM5r:
943 case X86Local::MRM6r:
944 case X86Local::MRM7r:
945 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
947 case X86Local::MRM0m:
948 case X86Local::MRM1m:
949 case X86Local::MRM2m:
950 case X86Local::MRM3m:
951 case X86Local::MRM4m:
952 case X86Local::MRM5m:
953 case X86Local::MRM6m:
954 case X86Local::MRM7m:
955 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
961 opcodeToSet = Opcode;
965 opcodeType = THREEBYTE_3A;
966 if (needsModRMForDecode(Form))
967 filter = new ModFilter(isRegFormat(Form));
969 filter = new DumbFilter();
970 opcodeToSet = Opcode;
973 opcodeType = THREEBYTE_A6;
974 if (needsModRMForDecode(Form))
975 filter = new ModFilter(isRegFormat(Form));
977 filter = new DumbFilter();
978 opcodeToSet = Opcode;
981 opcodeType = THREEBYTE_A7;
982 if (needsModRMForDecode(Form))
983 filter = new ModFilter(isRegFormat(Form));
985 filter = new DumbFilter();
986 opcodeToSet = Opcode;
989 opcodeType = XOP8_MAP;
990 if (needsModRMForDecode(Form))
991 filter = new ModFilter(isRegFormat(Form));
993 filter = new DumbFilter();
994 opcodeToSet = Opcode;
997 opcodeType = XOP9_MAP;
1000 if (needsModRMForDecode(Form))
1001 filter = new ModFilter(isRegFormat(Form));
1003 filter = new DumbFilter();
1005 #define EXTENSION_TABLE(n) case 0x##n:
1006 XOP9_MAP_EXTENSION_TABLES
1007 #undef EXTENSION_TABLE
1010 llvm_unreachable("Unhandled XOP9 extended opcode");
1011 case X86Local::MRM0r:
1012 case X86Local::MRM1r:
1013 case X86Local::MRM2r:
1014 case X86Local::MRM3r:
1015 case X86Local::MRM4r:
1016 case X86Local::MRM5r:
1017 case X86Local::MRM6r:
1018 case X86Local::MRM7r:
1019 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1021 case X86Local::MRM0m:
1022 case X86Local::MRM1m:
1023 case X86Local::MRM2m:
1024 case X86Local::MRM3m:
1025 case X86Local::MRM4m:
1026 case X86Local::MRM5m:
1027 case X86Local::MRM6m:
1028 case X86Local::MRM7m:
1029 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1034 } // switch (Opcode)
1035 opcodeToSet = Opcode;
1037 case X86Local::XOPA:
1038 opcodeType = XOPA_MAP;
1039 if (needsModRMForDecode(Form))
1040 filter = new ModFilter(isRegFormat(Form));
1042 filter = new DumbFilter();
1043 opcodeToSet = Opcode;
1053 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1054 assert(Form == X86Local::RawFrm);
1055 opcodeType = ONEBYTE;
1056 filter = new ExactFilter(Opcode);
1057 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1061 opcodeType = ONEBYTE;
1063 #define EXTENSION_TABLE(n) case 0x##n:
1064 ONE_BYTE_EXTENSION_TABLES
1065 #undef EXTENSION_TABLE
1068 llvm_unreachable("Fell through the cracks of a single-byte "
1070 case X86Local::MRM0r:
1071 case X86Local::MRM1r:
1072 case X86Local::MRM2r:
1073 case X86Local::MRM3r:
1074 case X86Local::MRM4r:
1075 case X86Local::MRM5r:
1076 case X86Local::MRM6r:
1077 case X86Local::MRM7r:
1078 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1080 case X86Local::MRM0m:
1081 case X86Local::MRM1m:
1082 case X86Local::MRM2m:
1083 case X86Local::MRM3m:
1084 case X86Local::MRM4m:
1085 case X86Local::MRM5m:
1086 case X86Local::MRM6m:
1087 case X86Local::MRM7m:
1088 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1103 llvm_unreachable("Unhandled escape opcode form");
1104 case X86Local::MRM0r:
1105 case X86Local::MRM1r:
1106 case X86Local::MRM2r:
1107 case X86Local::MRM3r:
1108 case X86Local::MRM4r:
1109 case X86Local::MRM5r:
1110 case X86Local::MRM6r:
1111 case X86Local::MRM7r:
1112 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1114 case X86Local::MRM0m:
1115 case X86Local::MRM1m:
1116 case X86Local::MRM2m:
1117 case X86Local::MRM3m:
1118 case X86Local::MRM4m:
1119 case X86Local::MRM5m:
1120 case X86Local::MRM6m:
1121 case X86Local::MRM7m:
1122 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1127 if (needsModRMForDecode(Form))
1128 filter = new ModFilter(isRegFormat(Form));
1130 filter = new DumbFilter();
1132 } // switch (Opcode)
1133 opcodeToSet = Opcode;
1134 } // switch (Prefix)
1136 assert(opcodeType != (OpcodeType)-1 &&
1137 "Opcode type not set");
1138 assert(filter && "Filter not set");
1140 if (Form == X86Local::AddRegFrm) {
1141 assert(((opcodeToSet & 7) == 0) &&
1142 "ADDREG_FRM opcode not aligned");
1144 uint8_t currentOpcode;
1146 for (currentOpcode = opcodeToSet;
1147 currentOpcode < opcodeToSet + 8;
1149 tables.setTableFields(opcodeType,
1153 UID, Is32Bit, IgnoresVEX_L);
1155 tables.setTableFields(opcodeType,
1159 UID, Is32Bit, IgnoresVEX_L);
1167 #define TYPE(str, type) if (s == str) return type;
1168 OperandType RecognizableInstr::typeFromString(const std::string &s,
1170 bool hasREX_WPrefix,
1171 bool hasOpSizePrefix) {
1173 // For SSE instructions, we ignore the OpSize prefix and force operand
1175 TYPE("GR16", TYPE_R16)
1176 TYPE("GR32", TYPE_R32)
1177 TYPE("GR64", TYPE_R64)
1179 if(hasREX_WPrefix) {
1180 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1182 TYPE("GR32", TYPE_R32)
1184 if(!hasOpSizePrefix) {
1185 // For instructions without an OpSize prefix, a declared 16-bit register or
1186 // immediate encoding is special.
1187 TYPE("GR16", TYPE_R16)
1188 TYPE("i16imm", TYPE_IMM16)
1190 TYPE("i16mem", TYPE_Mv)
1191 TYPE("i16imm", TYPE_IMMv)
1192 TYPE("i16i8imm", TYPE_IMMv)
1193 TYPE("GR16", TYPE_Rv)
1194 TYPE("i32mem", TYPE_Mv)
1195 TYPE("i32imm", TYPE_IMMv)
1196 TYPE("i32i8imm", TYPE_IMM32)
1197 TYPE("u32u8imm", TYPE_IMM32)
1198 TYPE("GR32", TYPE_Rv)
1199 TYPE("GR32orGR64", TYPE_R32)
1200 TYPE("i64mem", TYPE_Mv)
1201 TYPE("i64i32imm", TYPE_IMM64)
1202 TYPE("i64i8imm", TYPE_IMM64)
1203 TYPE("GR64", TYPE_R64)
1204 TYPE("i8mem", TYPE_M8)
1205 TYPE("i8imm", TYPE_IMM8)
1206 TYPE("GR8", TYPE_R8)
1207 TYPE("VR128", TYPE_XMM128)
1208 TYPE("VR128X", TYPE_XMM128)
1209 TYPE("f128mem", TYPE_M128)
1210 TYPE("f256mem", TYPE_M256)
1211 TYPE("f512mem", TYPE_M512)
1212 TYPE("FR64", TYPE_XMM64)
1213 TYPE("FR64X", TYPE_XMM64)
1214 TYPE("f64mem", TYPE_M64FP)
1215 TYPE("sdmem", TYPE_M64FP)
1216 TYPE("FR32", TYPE_XMM32)
1217 TYPE("FR32X", TYPE_XMM32)
1218 TYPE("f32mem", TYPE_M32FP)
1219 TYPE("ssmem", TYPE_M32FP)
1220 TYPE("RST", TYPE_ST)
1221 TYPE("i128mem", TYPE_M128)
1222 TYPE("i256mem", TYPE_M256)
1223 TYPE("i512mem", TYPE_M512)
1224 TYPE("i64i32imm_pcrel", TYPE_REL64)
1225 TYPE("i16imm_pcrel", TYPE_REL16)
1226 TYPE("i32imm_pcrel", TYPE_REL32)
1227 TYPE("SSECC", TYPE_IMM3)
1228 TYPE("AVXCC", TYPE_IMM5)
1229 TYPE("AVX512RC", TYPE_IMM32)
1230 TYPE("brtarget", TYPE_RELv)
1231 TYPE("uncondbrtarget", TYPE_RELv)
1232 TYPE("brtarget8", TYPE_REL8)
1233 TYPE("f80mem", TYPE_M80FP)
1234 TYPE("lea32mem", TYPE_LEA)
1235 TYPE("lea64_32mem", TYPE_LEA)
1236 TYPE("lea64mem", TYPE_LEA)
1237 TYPE("VR64", TYPE_MM64)
1238 TYPE("i64imm", TYPE_IMMv)
1239 TYPE("opaque32mem", TYPE_M1616)
1240 TYPE("opaque48mem", TYPE_M1632)
1241 TYPE("opaque80mem", TYPE_M1664)
1242 TYPE("opaque512mem", TYPE_M512)
1243 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1244 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1245 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1246 TYPE("offset8", TYPE_MOFFS8)
1247 TYPE("offset16", TYPE_MOFFS16)
1248 TYPE("offset32", TYPE_MOFFS32)
1249 TYPE("offset64", TYPE_MOFFS64)
1250 TYPE("VR256", TYPE_XMM256)
1251 TYPE("VR256X", TYPE_XMM256)
1252 TYPE("VR512", TYPE_XMM512)
1253 TYPE("VK1", TYPE_VK1)
1254 TYPE("VK1WM", TYPE_VK1)
1255 TYPE("VK8", TYPE_VK8)
1256 TYPE("VK8WM", TYPE_VK8)
1257 TYPE("VK16", TYPE_VK16)
1258 TYPE("VK16WM", TYPE_VK16)
1259 TYPE("GR16_NOAX", TYPE_Rv)
1260 TYPE("GR32_NOAX", TYPE_Rv)
1261 TYPE("GR64_NOAX", TYPE_R64)
1262 TYPE("vx32mem", TYPE_M32)
1263 TYPE("vy32mem", TYPE_M32)
1264 TYPE("vz32mem", TYPE_M32)
1265 TYPE("vx64mem", TYPE_M64)
1266 TYPE("vy64mem", TYPE_M64)
1267 TYPE("vy64xmem", TYPE_M64)
1268 TYPE("vz64mem", TYPE_M64)
1269 errs() << "Unhandled type string " << s << "\n";
1270 llvm_unreachable("Unhandled type string");
1274 #define ENCODING(str, encoding) if (s == str) return encoding;
1275 OperandEncoding RecognizableInstr::immediateEncodingFromString
1276 (const std::string &s,
1277 bool hasOpSizePrefix) {
1278 if(!hasOpSizePrefix) {
1279 // For instructions without an OpSize prefix, a declared 16-bit register or
1280 // immediate encoding is special.
1281 ENCODING("i16imm", ENCODING_IW)
1283 ENCODING("i32i8imm", ENCODING_IB)
1284 ENCODING("u32u8imm", ENCODING_IB)
1285 ENCODING("SSECC", ENCODING_IB)
1286 ENCODING("AVXCC", ENCODING_IB)
1287 ENCODING("AVX512RC", ENCODING_IB)
1288 ENCODING("i16imm", ENCODING_Iv)
1289 ENCODING("i16i8imm", ENCODING_IB)
1290 ENCODING("i32imm", ENCODING_Iv)
1291 ENCODING("i64i32imm", ENCODING_ID)
1292 ENCODING("i64i8imm", ENCODING_IB)
1293 ENCODING("i8imm", ENCODING_IB)
1294 // This is not a typo. Instructions like BLENDVPD put
1295 // register IDs in 8-bit immediates nowadays.
1296 ENCODING("FR32", ENCODING_IB)
1297 ENCODING("FR64", ENCODING_IB)
1298 ENCODING("VR128", ENCODING_IB)
1299 ENCODING("VR256", ENCODING_IB)
1300 ENCODING("FR32X", ENCODING_IB)
1301 ENCODING("FR64X", ENCODING_IB)
1302 ENCODING("VR128X", ENCODING_IB)
1303 ENCODING("VR256X", ENCODING_IB)
1304 ENCODING("VR512", ENCODING_IB)
1305 errs() << "Unhandled immediate encoding " << s << "\n";
1306 llvm_unreachable("Unhandled immediate encoding");
1309 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1310 (const std::string &s,
1311 bool hasOpSizePrefix) {
1312 ENCODING("RST", ENCODING_FP)
1313 ENCODING("GR16", ENCODING_RM)
1314 ENCODING("GR32", ENCODING_RM)
1315 ENCODING("GR32orGR64", ENCODING_RM)
1316 ENCODING("GR64", ENCODING_RM)
1317 ENCODING("GR8", ENCODING_RM)
1318 ENCODING("VR128", ENCODING_RM)
1319 ENCODING("VR128X", ENCODING_RM)
1320 ENCODING("FR64", ENCODING_RM)
1321 ENCODING("FR32", ENCODING_RM)
1322 ENCODING("FR64X", ENCODING_RM)
1323 ENCODING("FR32X", ENCODING_RM)
1324 ENCODING("VR64", ENCODING_RM)
1325 ENCODING("VR256", ENCODING_RM)
1326 ENCODING("VR256X", ENCODING_RM)
1327 ENCODING("VR512", ENCODING_RM)
1328 ENCODING("VK1", ENCODING_RM)
1329 ENCODING("VK8", ENCODING_RM)
1330 ENCODING("VK16", ENCODING_RM)
1331 errs() << "Unhandled R/M register encoding " << s << "\n";
1332 llvm_unreachable("Unhandled R/M register encoding");
1335 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1336 (const std::string &s,
1337 bool hasOpSizePrefix) {
1338 ENCODING("GR16", ENCODING_REG)
1339 ENCODING("GR32", ENCODING_REG)
1340 ENCODING("GR32orGR64", ENCODING_REG)
1341 ENCODING("GR64", ENCODING_REG)
1342 ENCODING("GR8", ENCODING_REG)
1343 ENCODING("VR128", ENCODING_REG)
1344 ENCODING("FR64", ENCODING_REG)
1345 ENCODING("FR32", ENCODING_REG)
1346 ENCODING("VR64", ENCODING_REG)
1347 ENCODING("SEGMENT_REG", ENCODING_REG)
1348 ENCODING("DEBUG_REG", ENCODING_REG)
1349 ENCODING("CONTROL_REG", ENCODING_REG)
1350 ENCODING("VR256", ENCODING_REG)
1351 ENCODING("VR256X", ENCODING_REG)
1352 ENCODING("VR128X", ENCODING_REG)
1353 ENCODING("FR64X", ENCODING_REG)
1354 ENCODING("FR32X", ENCODING_REG)
1355 ENCODING("VR512", ENCODING_REG)
1356 ENCODING("VK1", ENCODING_REG)
1357 ENCODING("VK8", ENCODING_REG)
1358 ENCODING("VK16", ENCODING_REG)
1359 ENCODING("VK1WM", ENCODING_REG)
1360 ENCODING("VK8WM", ENCODING_REG)
1361 ENCODING("VK16WM", ENCODING_REG)
1362 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1363 llvm_unreachable("Unhandled reg/opcode register encoding");
1366 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1367 (const std::string &s,
1368 bool hasOpSizePrefix) {
1369 ENCODING("GR32", ENCODING_VVVV)
1370 ENCODING("GR64", ENCODING_VVVV)
1371 ENCODING("FR32", ENCODING_VVVV)
1372 ENCODING("FR64", ENCODING_VVVV)
1373 ENCODING("VR128", ENCODING_VVVV)
1374 ENCODING("VR256", ENCODING_VVVV)
1375 ENCODING("FR32X", ENCODING_VVVV)
1376 ENCODING("FR64X", ENCODING_VVVV)
1377 ENCODING("VR128X", ENCODING_VVVV)
1378 ENCODING("VR256X", ENCODING_VVVV)
1379 ENCODING("VR512", ENCODING_VVVV)
1380 ENCODING("VK1", ENCODING_VVVV)
1381 ENCODING("VK8", ENCODING_VVVV)
1382 ENCODING("VK16", ENCODING_VVVV)
1383 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1384 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1387 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1388 (const std::string &s,
1389 bool hasOpSizePrefix) {
1390 ENCODING("VK1WM", ENCODING_WRITEMASK)
1391 ENCODING("VK8WM", ENCODING_WRITEMASK)
1392 ENCODING("VK16WM", ENCODING_WRITEMASK)
1393 errs() << "Unhandled mask register encoding " << s << "\n";
1394 llvm_unreachable("Unhandled mask register encoding");
1397 OperandEncoding RecognizableInstr::memoryEncodingFromString
1398 (const std::string &s,
1399 bool hasOpSizePrefix) {
1400 ENCODING("i16mem", ENCODING_RM)
1401 ENCODING("i32mem", ENCODING_RM)
1402 ENCODING("i64mem", ENCODING_RM)
1403 ENCODING("i8mem", ENCODING_RM)
1404 ENCODING("ssmem", ENCODING_RM)
1405 ENCODING("sdmem", ENCODING_RM)
1406 ENCODING("f128mem", ENCODING_RM)
1407 ENCODING("f256mem", ENCODING_RM)
1408 ENCODING("f512mem", ENCODING_RM)
1409 ENCODING("f64mem", ENCODING_RM)
1410 ENCODING("f32mem", ENCODING_RM)
1411 ENCODING("i128mem", ENCODING_RM)
1412 ENCODING("i256mem", ENCODING_RM)
1413 ENCODING("i512mem", ENCODING_RM)
1414 ENCODING("f80mem", ENCODING_RM)
1415 ENCODING("lea32mem", ENCODING_RM)
1416 ENCODING("lea64_32mem", ENCODING_RM)
1417 ENCODING("lea64mem", ENCODING_RM)
1418 ENCODING("opaque32mem", ENCODING_RM)
1419 ENCODING("opaque48mem", ENCODING_RM)
1420 ENCODING("opaque80mem", ENCODING_RM)
1421 ENCODING("opaque512mem", ENCODING_RM)
1422 ENCODING("vx32mem", ENCODING_RM)
1423 ENCODING("vy32mem", ENCODING_RM)
1424 ENCODING("vz32mem", ENCODING_RM)
1425 ENCODING("vx64mem", ENCODING_RM)
1426 ENCODING("vy64mem", ENCODING_RM)
1427 ENCODING("vy64xmem", ENCODING_RM)
1428 ENCODING("vz64mem", ENCODING_RM)
1429 errs() << "Unhandled memory encoding " << s << "\n";
1430 llvm_unreachable("Unhandled memory encoding");
1433 OperandEncoding RecognizableInstr::relocationEncodingFromString
1434 (const std::string &s,
1435 bool hasOpSizePrefix) {
1436 if(!hasOpSizePrefix) {
1437 // For instructions without an OpSize prefix, a declared 16-bit register or
1438 // immediate encoding is special.
1439 ENCODING("i16imm", ENCODING_IW)
1441 ENCODING("i16imm", ENCODING_Iv)
1442 ENCODING("i16i8imm", ENCODING_IB)
1443 ENCODING("i32imm", ENCODING_Iv)
1444 ENCODING("i32i8imm", ENCODING_IB)
1445 ENCODING("i64i32imm", ENCODING_ID)
1446 ENCODING("i64i8imm", ENCODING_IB)
1447 ENCODING("i8imm", ENCODING_IB)
1448 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1449 ENCODING("i16imm_pcrel", ENCODING_IW)
1450 ENCODING("i32imm_pcrel", ENCODING_ID)
1451 ENCODING("brtarget", ENCODING_Iv)
1452 ENCODING("brtarget8", ENCODING_IB)
1453 ENCODING("i64imm", ENCODING_IO)
1454 ENCODING("offset8", ENCODING_Ia)
1455 ENCODING("offset16", ENCODING_Ia)
1456 ENCODING("offset32", ENCODING_Ia)
1457 ENCODING("offset64", ENCODING_Ia)
1458 errs() << "Unhandled relocation encoding " << s << "\n";
1459 llvm_unreachable("Unhandled relocation encoding");
1462 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1463 (const std::string &s,
1464 bool hasOpSizePrefix) {
1465 ENCODING("GR32", ENCODING_Rv)
1466 ENCODING("GR64", ENCODING_RO)
1467 ENCODING("GR16", ENCODING_Rv)
1468 ENCODING("GR8", ENCODING_RB)
1469 ENCODING("GR16_NOAX", ENCODING_Rv)
1470 ENCODING("GR32_NOAX", ENCODING_Rv)
1471 ENCODING("GR64_NOAX", ENCODING_RO)
1472 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1473 llvm_unreachable("Unhandled opcode modifier encoding");