1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
65 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
66 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
67 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
68 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
71 #define MAP(from, to) MRM_##from = to,
80 D8 = 3, D9 = 4, DA = 5, DB = 6,
81 DC = 7, DD = 8, DE = 9, DF = 10,
84 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
85 XOP8 = 20, XOP9 = 21, XOPA = 22, PD = 23, T8PD = 24, TAPD = 25
89 // If rows are added to the opcode extension tables, then corresponding entries
90 // must be added here.
92 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
93 // that byte to ONE_BYTE_EXTENSION_TABLES.
95 // If the row corresponds to two bytes where the first is 0f, add an entry for
96 // the second byte to TWO_BYTE_EXTENSION_TABLES.
98 // If the row corresponds to some other set of bytes, you will need to modify
99 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
100 // to the X86 TD files, except in two cases: if the first two bytes of such a
101 // new combination are 0f 38 or 0f 3a, you just have to add maps called
102 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
103 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
104 // in RecognizableInstr::emitDecodePath().
106 #define ONE_BYTE_EXTENSION_TABLES \
107 EXTENSION_TABLE(80) \
108 EXTENSION_TABLE(81) \
109 EXTENSION_TABLE(82) \
110 EXTENSION_TABLE(83) \
111 EXTENSION_TABLE(8f) \
112 EXTENSION_TABLE(c0) \
113 EXTENSION_TABLE(c1) \
114 EXTENSION_TABLE(c6) \
115 EXTENSION_TABLE(c7) \
116 EXTENSION_TABLE(d0) \
117 EXTENSION_TABLE(d1) \
118 EXTENSION_TABLE(d2) \
119 EXTENSION_TABLE(d3) \
120 EXTENSION_TABLE(f6) \
121 EXTENSION_TABLE(f7) \
122 EXTENSION_TABLE(fe) \
125 #define TWO_BYTE_EXTENSION_TABLES \
126 EXTENSION_TABLE(00) \
127 EXTENSION_TABLE(01) \
128 EXTENSION_TABLE(0d) \
129 EXTENSION_TABLE(18) \
130 EXTENSION_TABLE(71) \
131 EXTENSION_TABLE(72) \
132 EXTENSION_TABLE(73) \
133 EXTENSION_TABLE(ae) \
134 EXTENSION_TABLE(ba) \
137 #define THREE_BYTE_38_EXTENSION_TABLES \
140 #define XOP9_MAP_EXTENSION_TABLES \
141 EXTENSION_TABLE(01) \
144 using namespace X86Disassembler;
146 /// needsModRMForDecode - Indicates whether a particular instruction requires a
147 /// ModR/M byte for the instruction to be properly decoded. For example, a
148 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
151 /// @param form - The form of the instruction.
152 /// @return - true if the form implies that a ModR/M byte is required, false
154 static bool needsModRMForDecode(uint8_t form) {
155 if (form == X86Local::MRMDestReg ||
156 form == X86Local::MRMDestMem ||
157 form == X86Local::MRMSrcReg ||
158 form == X86Local::MRMSrcMem ||
159 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
160 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
166 /// isRegFormat - Indicates whether a particular form requires the Mod field of
167 /// the ModR/M byte to be 0b11.
169 /// @param form - The form of the instruction.
170 /// @return - true if the form implies that Mod must be 0b11, false
172 static bool isRegFormat(uint8_t form) {
173 if (form == X86Local::MRMDestReg ||
174 form == X86Local::MRMSrcReg ||
175 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
181 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
182 /// Useful for switch statements and the like.
184 /// @param init - A reference to the BitsInit to be decoded.
185 /// @return - The field, with the first bit in the BitsInit as the lowest
187 static uint8_t byteFromBitsInit(BitsInit &init) {
188 int width = init.getNumBits();
190 assert(width <= 8 && "Field is too large for uint8_t!");
197 for (index = 0; index < width; index++) {
198 if (static_cast<BitInit*>(init.getBit(index))->getValue())
207 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
208 /// name of the field.
210 /// @param rec - The record from which to extract the value.
211 /// @param name - The name of the field in the record.
212 /// @return - The field, as translated by byteFromBitsInit().
213 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
214 BitsInit* bits = rec->getValueAsBitsInit(name);
215 return byteFromBitsInit(*bits);
218 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
219 const CodeGenInstruction &insn,
224 Name = Rec->getName();
225 Spec = &tables.specForUID(UID);
227 if (!Rec->isSubClassOf("X86Inst")) {
228 ShouldBeEmitted = false;
232 Prefix = byteFromRec(Rec, "Prefix");
233 Opcode = byteFromRec(Rec, "Opcode");
234 Form = byteFromRec(Rec, "FormBits");
236 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
237 HasOpSize16Prefix = Rec->getValueAsBit("hasOpSize16Prefix");
238 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
239 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
240 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
241 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
242 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
243 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
244 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
245 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
246 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
247 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
248 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
249 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
250 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
251 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
252 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
253 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
255 Name = Rec->getName();
256 AsmString = Rec->getValueAsString("AsmString");
258 Operands = &insn.Operands.OperandList;
260 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
262 // Check for 64-bit inst which does not require REX
265 // FIXME: Is there some better way to check for In64BitMode?
266 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
267 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
268 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
269 Predicates[i]->getName().find("In32Bit") != Name.npos) {
273 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
279 ShouldBeEmitted = true;
282 void RecognizableInstr::processInstr(DisassemblerTables &tables,
283 const CodeGenInstruction &insn,
286 // Ignore "asm parser only" instructions.
287 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
290 RecognizableInstr recogInstr(tables, insn, uid);
292 recogInstr.emitInstructionSpecifier();
294 if (recogInstr.shouldBeEmitted())
295 recogInstr.emitDecodePath(tables);
298 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
299 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
300 (HasEVEX_KZ ? n##_KZ : \
301 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
303 InstructionContext RecognizableInstr::insnContext() const {
304 InstructionContext insnContext;
307 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
308 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
309 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
312 if (HasVEX_LPrefix && HasVEX_WPrefix) {
313 if (HasOpSizePrefix || Prefix == X86Local::PD)
314 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
315 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
316 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
317 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
318 Prefix == X86Local::TAXD)
319 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
321 insnContext = EVEX_KB(IC_EVEX_L_W);
322 } else if (HasVEX_LPrefix) {
324 if (HasOpSizePrefix || Prefix == X86Local::PD ||
325 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
326 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
327 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
328 insnContext = EVEX_KB(IC_EVEX_L_XS);
329 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
330 Prefix == X86Local::TAXD)
331 insnContext = EVEX_KB(IC_EVEX_L_XD);
333 insnContext = EVEX_KB(IC_EVEX_L);
335 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
337 if (HasOpSizePrefix || Prefix == X86Local::PD ||
338 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
339 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
340 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
341 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
342 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
343 Prefix == X86Local::TAXD)
344 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
346 insnContext = EVEX_KB(IC_EVEX_L2_W);
347 } else if (HasEVEX_L2Prefix) {
349 if (HasOpSizePrefix || Prefix == X86Local::PD ||
350 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
351 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
352 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
353 Prefix == X86Local::TAXD)
354 insnContext = EVEX_KB(IC_EVEX_L2_XD);
355 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
356 insnContext = EVEX_KB(IC_EVEX_L2_XS);
358 insnContext = EVEX_KB(IC_EVEX_L2);
360 else if (HasVEX_WPrefix) {
362 if (HasOpSizePrefix || Prefix == X86Local::PD ||
363 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
364 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
365 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
366 insnContext = EVEX_KB(IC_EVEX_W_XS);
367 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
368 Prefix == X86Local::TAXD)
369 insnContext = EVEX_KB(IC_EVEX_W_XD);
371 insnContext = EVEX_KB(IC_EVEX_W);
374 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
375 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
376 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
377 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
378 Prefix == X86Local::TAXD)
379 insnContext = EVEX_KB(IC_EVEX_XD);
380 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
381 insnContext = EVEX_KB(IC_EVEX_XS);
383 insnContext = EVEX_KB(IC_EVEX);
385 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
386 if (HasVEX_LPrefix && HasVEX_WPrefix) {
387 if (HasOpSizePrefix || Prefix == X86Local::PD ||
388 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
389 insnContext = IC_VEX_L_W_OPSIZE;
390 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
391 insnContext = IC_VEX_L_W_XS;
392 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
393 Prefix == X86Local::TAXD)
394 insnContext = IC_VEX_L_W_XD;
396 insnContext = IC_VEX_L_W;
397 } else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
398 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
400 insnContext = IC_VEX_L_OPSIZE;
401 else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
402 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
404 insnContext = IC_VEX_W_OPSIZE;
405 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
406 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
407 insnContext = IC_VEX_OPSIZE;
408 else if (HasVEX_LPrefix &&
409 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
410 insnContext = IC_VEX_L_XS;
411 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
412 Prefix == X86Local::T8XD ||
413 Prefix == X86Local::TAXD))
414 insnContext = IC_VEX_L_XD;
415 else if (HasVEX_WPrefix &&
416 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
417 insnContext = IC_VEX_W_XS;
418 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
419 Prefix == X86Local::T8XD ||
420 Prefix == X86Local::TAXD))
421 insnContext = IC_VEX_W_XD;
422 else if (HasVEX_WPrefix)
423 insnContext = IC_VEX_W;
424 else if (HasVEX_LPrefix)
425 insnContext = IC_VEX_L;
426 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
427 Prefix == X86Local::TAXD)
428 insnContext = IC_VEX_XD;
429 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
430 insnContext = IC_VEX_XS;
432 insnContext = IC_VEX;
433 } else if (Is64Bit || HasREX_WPrefix) {
434 if (HasREX_WPrefix && (HasOpSizePrefix || Prefix == X86Local::PD ||
435 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD))
436 insnContext = IC_64BIT_REXW_OPSIZE;
437 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
438 Prefix == X86Local::T8XD ||
439 Prefix == X86Local::TAXD))
440 insnContext = IC_64BIT_XD_OPSIZE;
441 else if (HasOpSizePrefix &&
442 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
443 insnContext = IC_64BIT_XS_OPSIZE;
444 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
445 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
446 insnContext = IC_64BIT_OPSIZE;
447 else if (HasAdSizePrefix)
448 insnContext = IC_64BIT_ADSIZE;
449 else if (HasREX_WPrefix &&
450 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
451 insnContext = IC_64BIT_REXW_XS;
452 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
453 Prefix == X86Local::T8XD ||
454 Prefix == X86Local::TAXD))
455 insnContext = IC_64BIT_REXW_XD;
456 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
457 Prefix == X86Local::TAXD)
458 insnContext = IC_64BIT_XD;
459 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
460 insnContext = IC_64BIT_XS;
461 else if (HasREX_WPrefix)
462 insnContext = IC_64BIT_REXW;
464 insnContext = IC_64BIT;
466 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
467 Prefix == X86Local::T8XD ||
468 Prefix == X86Local::TAXD))
469 insnContext = IC_XD_OPSIZE;
470 else if (HasOpSizePrefix &&
471 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
472 insnContext = IC_XS_OPSIZE;
473 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
474 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
475 insnContext = IC_OPSIZE;
476 else if (HasAdSizePrefix)
477 insnContext = IC_ADSIZE;
478 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
479 Prefix == X86Local::TAXD)
481 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
482 Prefix == X86Local::REP)
491 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
496 // Filter out intrinsics
498 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
500 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
501 return FILTER_STRONG;
504 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
505 // printed as a separate "instruction".
513 // Filter out instructions with a LOCK prefix;
514 // prefer forms that do not have the prefix
520 if (Name == "VMASKMOVDQU64")
523 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
524 // For now, just prefer the REP versions.
525 if (Name == "XACQUIRE_PREFIX" ||
526 Name == "XRELEASE_PREFIX")
529 return FILTER_NORMAL;
532 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
533 unsigned &physicalOperandIndex,
534 unsigned &numPhysicalOperands,
535 const unsigned *operandMapping,
536 OperandEncoding (*encodingFromString)
538 bool hasOpSizePrefix)) {
540 if (physicalOperandIndex >= numPhysicalOperands)
543 assert(physicalOperandIndex < numPhysicalOperands);
546 while (operandMapping[operandIndex] != operandIndex) {
547 Spec->operands[operandIndex].encoding = ENCODING_DUP;
548 Spec->operands[operandIndex].type =
549 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
553 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
555 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
557 Spec->operands[operandIndex].type = typeFromString(typeName,
563 ++physicalOperandIndex;
566 void RecognizableInstr::emitInstructionSpecifier() {
569 if (!ShouldBeEmitted)
574 Spec->filtered = true;
577 ShouldBeEmitted = false;
583 Spec->insnContext = insnContext();
585 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
587 unsigned numOperands = OperandList.size();
588 unsigned numPhysicalOperands = 0;
590 // operandMapping maps from operands in OperandList to their originals.
591 // If operandMapping[i] != i, then the entry is a duplicate.
592 unsigned operandMapping[X86_MAX_OPERANDS];
593 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
595 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
596 if (OperandList[operandIndex].Constraints.size()) {
597 const CGIOperandList::ConstraintInfo &Constraint =
598 OperandList[operandIndex].Constraints[0];
599 if (Constraint.isTied()) {
600 operandMapping[operandIndex] = operandIndex;
601 operandMapping[Constraint.getTiedOperand()] = operandIndex;
603 ++numPhysicalOperands;
604 operandMapping[operandIndex] = operandIndex;
607 ++numPhysicalOperands;
608 operandMapping[operandIndex] = operandIndex;
612 #define HANDLE_OPERAND(class) \
613 handleOperand(false, \
615 physicalOperandIndex, \
616 numPhysicalOperands, \
618 class##EncodingFromString);
620 #define HANDLE_OPTIONAL(class) \
621 handleOperand(true, \
623 physicalOperandIndex, \
624 numPhysicalOperands, \
626 class##EncodingFromString);
628 // operandIndex should always be < numOperands
629 unsigned operandIndex = 0;
630 // physicalOperandIndex should always be < numPhysicalOperands
631 unsigned physicalOperandIndex = 0;
634 default: llvm_unreachable("Unhandled form");
635 case X86Local::RawFrmSrc:
636 HANDLE_OPERAND(relocation);
638 case X86Local::RawFrmDst:
639 HANDLE_OPERAND(relocation);
641 case X86Local::RawFrm:
642 // Operand 1 (optional) is an address or immediate.
643 // Operand 2 (optional) is an immediate.
644 assert(numPhysicalOperands <= 2 &&
645 "Unexpected number of operands for RawFrm");
646 HANDLE_OPTIONAL(relocation)
647 HANDLE_OPTIONAL(immediate)
649 case X86Local::RawFrmMemOffs:
650 // Operand 1 is an address.
651 HANDLE_OPERAND(relocation);
653 case X86Local::AddRegFrm:
654 // Operand 1 is added to the opcode.
655 // Operand 2 (optional) is an address.
656 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
657 "Unexpected number of operands for AddRegFrm");
658 HANDLE_OPERAND(opcodeModifier)
659 HANDLE_OPTIONAL(relocation)
661 case X86Local::MRMDestReg:
662 // Operand 1 is a register operand in the R/M field.
663 // Operand 2 is a register operand in the Reg/Opcode field.
664 // - In AVX, there is a register operand in the VEX.vvvv field here -
665 // Operand 3 (optional) is an immediate.
667 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
668 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
670 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
671 "Unexpected number of operands for MRMDestRegFrm");
673 HANDLE_OPERAND(rmRegister)
676 // FIXME: In AVX, the register below becomes the one encoded
677 // in ModRMVEX and the one above the one in the VEX.VVVV field
678 HANDLE_OPERAND(vvvvRegister)
680 HANDLE_OPERAND(roRegister)
681 HANDLE_OPTIONAL(immediate)
683 case X86Local::MRMDestMem:
684 // Operand 1 is a memory operand (possibly SIB-extended)
685 // Operand 2 is a register operand in the Reg/Opcode field.
686 // - In AVX, there is a register operand in the VEX.vvvv field here -
687 // Operand 3 (optional) is an immediate.
689 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
690 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
692 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
693 "Unexpected number of operands for MRMDestMemFrm");
694 HANDLE_OPERAND(memory)
697 HANDLE_OPERAND(writemaskRegister)
700 // FIXME: In AVX, the register below becomes the one encoded
701 // in ModRMVEX and the one above the one in the VEX.VVVV field
702 HANDLE_OPERAND(vvvvRegister)
704 HANDLE_OPERAND(roRegister)
705 HANDLE_OPTIONAL(immediate)
707 case X86Local::MRMSrcReg:
708 // Operand 1 is a register operand in the Reg/Opcode field.
709 // Operand 2 is a register operand in the R/M field.
710 // - In AVX, there is a register operand in the VEX.vvvv field here -
711 // Operand 3 (optional) is an immediate.
712 // Operand 4 (optional) is an immediate.
714 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
715 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
716 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
718 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
719 "Unexpected number of operands for MRMSrcRegFrm");
721 HANDLE_OPERAND(roRegister)
724 HANDLE_OPERAND(writemaskRegister)
727 // FIXME: In AVX, the register below becomes the one encoded
728 // in ModRMVEX and the one above the one in the VEX.VVVV field
729 HANDLE_OPERAND(vvvvRegister)
732 HANDLE_OPERAND(immediate)
734 HANDLE_OPERAND(rmRegister)
736 if (HasVEX_4VOp3Prefix)
737 HANDLE_OPERAND(vvvvRegister)
739 if (!HasMemOp4Prefix)
740 HANDLE_OPTIONAL(immediate)
741 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
742 HANDLE_OPTIONAL(immediate)
744 case X86Local::MRMSrcMem:
745 // Operand 1 is a register operand in the Reg/Opcode field.
746 // Operand 2 is a memory operand (possibly SIB-extended)
747 // - In AVX, there is a register operand in the VEX.vvvv field here -
748 // Operand 3 (optional) is an immediate.
750 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
751 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
752 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
754 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
755 "Unexpected number of operands for MRMSrcMemFrm");
757 HANDLE_OPERAND(roRegister)
760 HANDLE_OPERAND(writemaskRegister)
763 // FIXME: In AVX, the register below becomes the one encoded
764 // in ModRMVEX and the one above the one in the VEX.VVVV field
765 HANDLE_OPERAND(vvvvRegister)
768 HANDLE_OPERAND(immediate)
770 HANDLE_OPERAND(memory)
772 if (HasVEX_4VOp3Prefix)
773 HANDLE_OPERAND(vvvvRegister)
775 if (!HasMemOp4Prefix)
776 HANDLE_OPTIONAL(immediate)
777 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
779 case X86Local::MRM0r:
780 case X86Local::MRM1r:
781 case X86Local::MRM2r:
782 case X86Local::MRM3r:
783 case X86Local::MRM4r:
784 case X86Local::MRM5r:
785 case X86Local::MRM6r:
786 case X86Local::MRM7r:
788 // Operand 1 is a register operand in the R/M field.
789 // Operand 2 (optional) is an immediate or relocation.
790 // Operand 3 (optional) is an immediate.
791 unsigned kOp = (HasEVEX_K) ? 1:0;
792 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
793 if (numPhysicalOperands > 3 + kOp + Op4v)
794 llvm_unreachable("Unexpected number of operands for MRMnr");
797 HANDLE_OPERAND(vvvvRegister)
800 HANDLE_OPERAND(writemaskRegister)
801 HANDLE_OPTIONAL(rmRegister)
802 HANDLE_OPTIONAL(relocation)
803 HANDLE_OPTIONAL(immediate)
805 case X86Local::MRM0m:
806 case X86Local::MRM1m:
807 case X86Local::MRM2m:
808 case X86Local::MRM3m:
809 case X86Local::MRM4m:
810 case X86Local::MRM5m:
811 case X86Local::MRM6m:
812 case X86Local::MRM7m:
814 // Operand 1 is a memory operand (possibly SIB-extended)
815 // Operand 2 (optional) is an immediate or relocation.
816 unsigned kOp = (HasEVEX_K) ? 1:0;
817 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
818 if (numPhysicalOperands < 1 + kOp + Op4v ||
819 numPhysicalOperands > 2 + kOp + Op4v)
820 llvm_unreachable("Unexpected number of operands for MRMnm");
823 HANDLE_OPERAND(vvvvRegister)
825 HANDLE_OPERAND(writemaskRegister)
826 HANDLE_OPERAND(memory)
827 HANDLE_OPTIONAL(relocation)
829 case X86Local::RawFrmImm8:
830 // operand 1 is a 16-bit immediate
831 // operand 2 is an 8-bit immediate
832 assert(numPhysicalOperands == 2 &&
833 "Unexpected number of operands for X86Local::RawFrmImm8");
834 HANDLE_OPERAND(immediate)
835 HANDLE_OPERAND(immediate)
837 case X86Local::RawFrmImm16:
838 // operand 1 is a 16-bit immediate
839 // operand 2 is a 16-bit immediate
840 HANDLE_OPERAND(immediate)
841 HANDLE_OPERAND(immediate)
843 case X86Local::MRM_F8:
844 if (Opcode == 0xc6) {
845 assert(numPhysicalOperands == 1 &&
846 "Unexpected number of operands for X86Local::MRM_F8");
847 HANDLE_OPERAND(immediate)
848 } else if (Opcode == 0xc7) {
849 assert(numPhysicalOperands == 1 &&
850 "Unexpected number of operands for X86Local::MRM_F8");
851 HANDLE_OPERAND(relocation)
854 case X86Local::MRM_C1:
855 case X86Local::MRM_C2:
856 case X86Local::MRM_C3:
857 case X86Local::MRM_C4:
858 case X86Local::MRM_C8:
859 case X86Local::MRM_C9:
860 case X86Local::MRM_CA:
861 case X86Local::MRM_CB:
862 case X86Local::MRM_E8:
863 case X86Local::MRM_F0:
864 case X86Local::MRM_F9:
865 case X86Local::MRM_D0:
866 case X86Local::MRM_D1:
867 case X86Local::MRM_D4:
868 case X86Local::MRM_D5:
869 case X86Local::MRM_D6:
870 case X86Local::MRM_D8:
871 case X86Local::MRM_D9:
872 case X86Local::MRM_DA:
873 case X86Local::MRM_DB:
874 case X86Local::MRM_DC:
875 case X86Local::MRM_DD:
876 case X86Local::MRM_DE:
877 case X86Local::MRM_DF:
882 #undef HANDLE_OPERAND
883 #undef HANDLE_OPTIONAL
886 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
887 // Special cases where the LLVM tables are not complete
889 #define MAP(from, to) \
890 case X86Local::MRM_##from: \
891 filter = new ExactFilter(0x##from); \
894 OpcodeType opcodeType = (OpcodeType)-1;
896 ModRMFilter* filter = NULL;
897 uint8_t opcodeToSet = 0;
900 default: llvm_unreachable("Invalid prefix!");
901 // Extended two-byte opcodes can start with 66 0f, f2 0f, f3 0f, or 0f
906 opcodeType = TWOBYTE;
910 if (needsModRMForDecode(Form))
911 filter = new ModFilter(isRegFormat(Form));
913 filter = new DumbFilter();
915 #define EXTENSION_TABLE(n) case 0x##n:
916 TWO_BYTE_EXTENSION_TABLES
917 #undef EXTENSION_TABLE
920 llvm_unreachable("Unhandled two-byte extended opcode");
921 case X86Local::MRM0r:
922 case X86Local::MRM1r:
923 case X86Local::MRM2r:
924 case X86Local::MRM3r:
925 case X86Local::MRM4r:
926 case X86Local::MRM5r:
927 case X86Local::MRM6r:
928 case X86Local::MRM7r:
929 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
931 case X86Local::MRM0m:
932 case X86Local::MRM1m:
933 case X86Local::MRM2m:
934 case X86Local::MRM3m:
935 case X86Local::MRM4m:
936 case X86Local::MRM5m:
937 case X86Local::MRM6m:
938 case X86Local::MRM7m:
939 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
945 opcodeToSet = Opcode;
951 opcodeType = THREEBYTE_38;
954 if (needsModRMForDecode(Form))
955 filter = new ModFilter(isRegFormat(Form));
957 filter = new DumbFilter();
959 #define EXTENSION_TABLE(n) case 0x##n:
960 THREE_BYTE_38_EXTENSION_TABLES
961 #undef EXTENSION_TABLE
964 llvm_unreachable("Unhandled two-byte extended opcode");
965 case X86Local::MRM0r:
966 case X86Local::MRM1r:
967 case X86Local::MRM2r:
968 case X86Local::MRM3r:
969 case X86Local::MRM4r:
970 case X86Local::MRM5r:
971 case X86Local::MRM6r:
972 case X86Local::MRM7r:
973 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
975 case X86Local::MRM0m:
976 case X86Local::MRM1m:
977 case X86Local::MRM2m:
978 case X86Local::MRM3m:
979 case X86Local::MRM4m:
980 case X86Local::MRM5m:
981 case X86Local::MRM6m:
982 case X86Local::MRM7m:
983 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
989 opcodeToSet = Opcode;
994 opcodeType = THREEBYTE_3A;
995 if (needsModRMForDecode(Form))
996 filter = new ModFilter(isRegFormat(Form));
998 filter = new DumbFilter();
999 opcodeToSet = Opcode;
1002 opcodeType = THREEBYTE_A6;
1003 if (needsModRMForDecode(Form))
1004 filter = new ModFilter(isRegFormat(Form));
1006 filter = new DumbFilter();
1007 opcodeToSet = Opcode;
1010 opcodeType = THREEBYTE_A7;
1011 if (needsModRMForDecode(Form))
1012 filter = new ModFilter(isRegFormat(Form));
1014 filter = new DumbFilter();
1015 opcodeToSet = Opcode;
1017 case X86Local::XOP8:
1018 opcodeType = XOP8_MAP;
1019 if (needsModRMForDecode(Form))
1020 filter = new ModFilter(isRegFormat(Form));
1022 filter = new DumbFilter();
1023 opcodeToSet = Opcode;
1025 case X86Local::XOP9:
1026 opcodeType = XOP9_MAP;
1029 if (needsModRMForDecode(Form))
1030 filter = new ModFilter(isRegFormat(Form));
1032 filter = new DumbFilter();
1034 #define EXTENSION_TABLE(n) case 0x##n:
1035 XOP9_MAP_EXTENSION_TABLES
1036 #undef EXTENSION_TABLE
1039 llvm_unreachable("Unhandled XOP9 extended opcode");
1040 case X86Local::MRM0r:
1041 case X86Local::MRM1r:
1042 case X86Local::MRM2r:
1043 case X86Local::MRM3r:
1044 case X86Local::MRM4r:
1045 case X86Local::MRM5r:
1046 case X86Local::MRM6r:
1047 case X86Local::MRM7r:
1048 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1050 case X86Local::MRM0m:
1051 case X86Local::MRM1m:
1052 case X86Local::MRM2m:
1053 case X86Local::MRM3m:
1054 case X86Local::MRM4m:
1055 case X86Local::MRM5m:
1056 case X86Local::MRM6m:
1057 case X86Local::MRM7m:
1058 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1063 } // switch (Opcode)
1064 opcodeToSet = Opcode;
1066 case X86Local::XOPA:
1067 opcodeType = XOPA_MAP;
1068 if (needsModRMForDecode(Form))
1069 filter = new ModFilter(isRegFormat(Form));
1071 filter = new DumbFilter();
1072 opcodeToSet = Opcode;
1082 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1083 assert(Form == X86Local::RawFrm);
1084 opcodeType = ONEBYTE;
1085 filter = new ExactFilter(Opcode);
1086 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1090 opcodeType = ONEBYTE;
1092 #define EXTENSION_TABLE(n) case 0x##n:
1093 ONE_BYTE_EXTENSION_TABLES
1094 #undef EXTENSION_TABLE
1097 llvm_unreachable("Fell through the cracks of a single-byte "
1099 case X86Local::MRM0r:
1100 case X86Local::MRM1r:
1101 case X86Local::MRM2r:
1102 case X86Local::MRM3r:
1103 case X86Local::MRM4r:
1104 case X86Local::MRM5r:
1105 case X86Local::MRM6r:
1106 case X86Local::MRM7r:
1107 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1109 case X86Local::MRM0m:
1110 case X86Local::MRM1m:
1111 case X86Local::MRM2m:
1112 case X86Local::MRM3m:
1113 case X86Local::MRM4m:
1114 case X86Local::MRM5m:
1115 case X86Local::MRM6m:
1116 case X86Local::MRM7m:
1117 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1132 llvm_unreachable("Unhandled escape opcode form");
1133 case X86Local::MRM0r:
1134 case X86Local::MRM1r:
1135 case X86Local::MRM2r:
1136 case X86Local::MRM3r:
1137 case X86Local::MRM4r:
1138 case X86Local::MRM5r:
1139 case X86Local::MRM6r:
1140 case X86Local::MRM7r:
1141 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1143 case X86Local::MRM0m:
1144 case X86Local::MRM1m:
1145 case X86Local::MRM2m:
1146 case X86Local::MRM3m:
1147 case X86Local::MRM4m:
1148 case X86Local::MRM5m:
1149 case X86Local::MRM6m:
1150 case X86Local::MRM7m:
1151 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1156 if (needsModRMForDecode(Form))
1157 filter = new ModFilter(isRegFormat(Form));
1159 filter = new DumbFilter();
1161 } // switch (Opcode)
1162 opcodeToSet = Opcode;
1163 } // switch (Prefix)
1165 assert(opcodeType != (OpcodeType)-1 &&
1166 "Opcode type not set");
1167 assert(filter && "Filter not set");
1169 if (Form == X86Local::AddRegFrm) {
1170 assert(((opcodeToSet & 7) == 0) &&
1171 "ADDREG_FRM opcode not aligned");
1173 uint8_t currentOpcode;
1175 for (currentOpcode = opcodeToSet;
1176 currentOpcode < opcodeToSet + 8;
1178 tables.setTableFields(opcodeType,
1182 UID, Is32Bit, IgnoresVEX_L);
1184 tables.setTableFields(opcodeType,
1188 UID, Is32Bit, IgnoresVEX_L);
1196 #define TYPE(str, type) if (s == str) return type;
1197 OperandType RecognizableInstr::typeFromString(const std::string &s,
1198 bool hasREX_WPrefix,
1199 bool hasOpSizePrefix,
1200 bool hasOpSize16Prefix) {
1201 if(hasREX_WPrefix) {
1202 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1204 TYPE("GR32", TYPE_R32)
1206 if(hasOpSizePrefix) {
1207 // For instructions with an OpSize prefix, a declared 16-bit register or
1208 // immediate encoding is special.
1209 TYPE("GR16", TYPE_Rv)
1210 TYPE("i16imm", TYPE_IMMv)
1212 if(hasOpSize16Prefix) {
1213 // For instructions with an OpSize16 prefix, a declared 32-bit register or
1214 // immediate encoding is special.
1215 TYPE("GR32", TYPE_Rv)
1217 TYPE("i16mem", TYPE_Mv)
1218 TYPE("i16imm", TYPE_IMM16)
1219 TYPE("i16i8imm", TYPE_IMMv)
1220 TYPE("GR16", TYPE_R16)
1221 TYPE("i32mem", TYPE_Mv)
1222 TYPE("i32imm", TYPE_IMMv)
1223 TYPE("i32i8imm", TYPE_IMM32)
1224 TYPE("u32u8imm", TYPE_IMM32)
1225 TYPE("GR32", TYPE_R32)
1226 TYPE("GR32orGR64", TYPE_R32)
1227 TYPE("i64mem", TYPE_Mv)
1228 TYPE("i64i32imm", TYPE_IMM64)
1229 TYPE("i64i8imm", TYPE_IMM64)
1230 TYPE("GR64", TYPE_R64)
1231 TYPE("i8mem", TYPE_M8)
1232 TYPE("i8imm", TYPE_IMM8)
1233 TYPE("GR8", TYPE_R8)
1234 TYPE("VR128", TYPE_XMM128)
1235 TYPE("VR128X", TYPE_XMM128)
1236 TYPE("f128mem", TYPE_M128)
1237 TYPE("f256mem", TYPE_M256)
1238 TYPE("f512mem", TYPE_M512)
1239 TYPE("FR64", TYPE_XMM64)
1240 TYPE("FR64X", TYPE_XMM64)
1241 TYPE("f64mem", TYPE_M64FP)
1242 TYPE("sdmem", TYPE_M64FP)
1243 TYPE("FR32", TYPE_XMM32)
1244 TYPE("FR32X", TYPE_XMM32)
1245 TYPE("f32mem", TYPE_M32FP)
1246 TYPE("ssmem", TYPE_M32FP)
1247 TYPE("RST", TYPE_ST)
1248 TYPE("i128mem", TYPE_M128)
1249 TYPE("i256mem", TYPE_M256)
1250 TYPE("i512mem", TYPE_M512)
1251 TYPE("i64i32imm_pcrel", TYPE_REL64)
1252 TYPE("i16imm_pcrel", TYPE_REL16)
1253 TYPE("i32imm_pcrel", TYPE_REL32)
1254 TYPE("SSECC", TYPE_IMM3)
1255 TYPE("AVXCC", TYPE_IMM5)
1256 TYPE("AVX512RC", TYPE_IMM32)
1257 TYPE("brtarget", TYPE_RELv)
1258 TYPE("uncondbrtarget", TYPE_RELv)
1259 TYPE("brtarget8", TYPE_REL8)
1260 TYPE("f80mem", TYPE_M80FP)
1261 TYPE("lea32mem", TYPE_LEA)
1262 TYPE("lea64_32mem", TYPE_LEA)
1263 TYPE("lea64mem", TYPE_LEA)
1264 TYPE("VR64", TYPE_MM64)
1265 TYPE("i64imm", TYPE_IMMv)
1266 TYPE("opaque32mem", TYPE_M1616)
1267 TYPE("opaque48mem", TYPE_M1632)
1268 TYPE("opaque80mem", TYPE_M1664)
1269 TYPE("opaque512mem", TYPE_M512)
1270 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1271 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1272 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1273 TYPE("srcidx8", TYPE_SRCIDX8)
1274 TYPE("srcidx16", TYPE_SRCIDX16)
1275 TYPE("srcidx32", TYPE_SRCIDX32)
1276 TYPE("srcidx64", TYPE_SRCIDX64)
1277 TYPE("dstidx8", TYPE_DSTIDX8)
1278 TYPE("dstidx16", TYPE_DSTIDX16)
1279 TYPE("dstidx32", TYPE_DSTIDX32)
1280 TYPE("dstidx64", TYPE_DSTIDX64)
1281 TYPE("offset8", TYPE_MOFFS8)
1282 TYPE("offset16", TYPE_MOFFS16)
1283 TYPE("offset32", TYPE_MOFFS32)
1284 TYPE("offset64", TYPE_MOFFS64)
1285 TYPE("VR256", TYPE_XMM256)
1286 TYPE("VR256X", TYPE_XMM256)
1287 TYPE("VR512", TYPE_XMM512)
1288 TYPE("VK1", TYPE_VK1)
1289 TYPE("VK1WM", TYPE_VK1)
1290 TYPE("VK8", TYPE_VK8)
1291 TYPE("VK8WM", TYPE_VK8)
1292 TYPE("VK16", TYPE_VK16)
1293 TYPE("VK16WM", TYPE_VK16)
1294 TYPE("GR16_NOAX", TYPE_Rv)
1295 TYPE("GR32_NOAX", TYPE_Rv)
1296 TYPE("GR64_NOAX", TYPE_R64)
1297 TYPE("vx32mem", TYPE_M32)
1298 TYPE("vy32mem", TYPE_M32)
1299 TYPE("vz32mem", TYPE_M32)
1300 TYPE("vx64mem", TYPE_M64)
1301 TYPE("vy64mem", TYPE_M64)
1302 TYPE("vy64xmem", TYPE_M64)
1303 TYPE("vz64mem", TYPE_M64)
1304 errs() << "Unhandled type string " << s << "\n";
1305 llvm_unreachable("Unhandled type string");
1309 #define ENCODING(str, encoding) if (s == str) return encoding;
1310 OperandEncoding RecognizableInstr::immediateEncodingFromString
1311 (const std::string &s,
1312 bool hasOpSizePrefix) {
1313 if(!hasOpSizePrefix) {
1314 // For instructions without an OpSize prefix, a declared 16-bit register or
1315 // immediate encoding is special.
1316 ENCODING("i16imm", ENCODING_IW)
1318 ENCODING("i32i8imm", ENCODING_IB)
1319 ENCODING("u32u8imm", ENCODING_IB)
1320 ENCODING("SSECC", ENCODING_IB)
1321 ENCODING("AVXCC", ENCODING_IB)
1322 ENCODING("AVX512RC", ENCODING_IB)
1323 ENCODING("i16imm", ENCODING_Iv)
1324 ENCODING("i16i8imm", ENCODING_IB)
1325 ENCODING("i32imm", ENCODING_Iv)
1326 ENCODING("i64i32imm", ENCODING_ID)
1327 ENCODING("i64i8imm", ENCODING_IB)
1328 ENCODING("i8imm", ENCODING_IB)
1329 // This is not a typo. Instructions like BLENDVPD put
1330 // register IDs in 8-bit immediates nowadays.
1331 ENCODING("FR32", ENCODING_IB)
1332 ENCODING("FR64", ENCODING_IB)
1333 ENCODING("VR128", ENCODING_IB)
1334 ENCODING("VR256", ENCODING_IB)
1335 ENCODING("FR32X", ENCODING_IB)
1336 ENCODING("FR64X", ENCODING_IB)
1337 ENCODING("VR128X", ENCODING_IB)
1338 ENCODING("VR256X", ENCODING_IB)
1339 ENCODING("VR512", ENCODING_IB)
1340 errs() << "Unhandled immediate encoding " << s << "\n";
1341 llvm_unreachable("Unhandled immediate encoding");
1344 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1345 (const std::string &s,
1346 bool hasOpSizePrefix) {
1347 ENCODING("RST", ENCODING_FP)
1348 ENCODING("GR16", ENCODING_RM)
1349 ENCODING("GR32", ENCODING_RM)
1350 ENCODING("GR32orGR64", ENCODING_RM)
1351 ENCODING("GR64", ENCODING_RM)
1352 ENCODING("GR8", ENCODING_RM)
1353 ENCODING("VR128", ENCODING_RM)
1354 ENCODING("VR128X", ENCODING_RM)
1355 ENCODING("FR64", ENCODING_RM)
1356 ENCODING("FR32", ENCODING_RM)
1357 ENCODING("FR64X", ENCODING_RM)
1358 ENCODING("FR32X", ENCODING_RM)
1359 ENCODING("VR64", ENCODING_RM)
1360 ENCODING("VR256", ENCODING_RM)
1361 ENCODING("VR256X", ENCODING_RM)
1362 ENCODING("VR512", ENCODING_RM)
1363 ENCODING("VK1", ENCODING_RM)
1364 ENCODING("VK8", ENCODING_RM)
1365 ENCODING("VK16", ENCODING_RM)
1366 errs() << "Unhandled R/M register encoding " << s << "\n";
1367 llvm_unreachable("Unhandled R/M register encoding");
1370 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1371 (const std::string &s,
1372 bool hasOpSizePrefix) {
1373 ENCODING("GR16", ENCODING_REG)
1374 ENCODING("GR32", ENCODING_REG)
1375 ENCODING("GR32orGR64", ENCODING_REG)
1376 ENCODING("GR64", ENCODING_REG)
1377 ENCODING("GR8", ENCODING_REG)
1378 ENCODING("VR128", ENCODING_REG)
1379 ENCODING("FR64", ENCODING_REG)
1380 ENCODING("FR32", ENCODING_REG)
1381 ENCODING("VR64", ENCODING_REG)
1382 ENCODING("SEGMENT_REG", ENCODING_REG)
1383 ENCODING("DEBUG_REG", ENCODING_REG)
1384 ENCODING("CONTROL_REG", ENCODING_REG)
1385 ENCODING("VR256", ENCODING_REG)
1386 ENCODING("VR256X", ENCODING_REG)
1387 ENCODING("VR128X", ENCODING_REG)
1388 ENCODING("FR64X", ENCODING_REG)
1389 ENCODING("FR32X", ENCODING_REG)
1390 ENCODING("VR512", ENCODING_REG)
1391 ENCODING("VK1", ENCODING_REG)
1392 ENCODING("VK8", ENCODING_REG)
1393 ENCODING("VK16", ENCODING_REG)
1394 ENCODING("VK1WM", ENCODING_REG)
1395 ENCODING("VK8WM", ENCODING_REG)
1396 ENCODING("VK16WM", ENCODING_REG)
1397 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1398 llvm_unreachable("Unhandled reg/opcode register encoding");
1401 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1402 (const std::string &s,
1403 bool hasOpSizePrefix) {
1404 ENCODING("GR32", ENCODING_VVVV)
1405 ENCODING("GR64", ENCODING_VVVV)
1406 ENCODING("FR32", ENCODING_VVVV)
1407 ENCODING("FR64", ENCODING_VVVV)
1408 ENCODING("VR128", ENCODING_VVVV)
1409 ENCODING("VR256", ENCODING_VVVV)
1410 ENCODING("FR32X", ENCODING_VVVV)
1411 ENCODING("FR64X", ENCODING_VVVV)
1412 ENCODING("VR128X", ENCODING_VVVV)
1413 ENCODING("VR256X", ENCODING_VVVV)
1414 ENCODING("VR512", ENCODING_VVVV)
1415 ENCODING("VK1", ENCODING_VVVV)
1416 ENCODING("VK8", ENCODING_VVVV)
1417 ENCODING("VK16", ENCODING_VVVV)
1418 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1419 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1422 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1423 (const std::string &s,
1424 bool hasOpSizePrefix) {
1425 ENCODING("VK1WM", ENCODING_WRITEMASK)
1426 ENCODING("VK8WM", ENCODING_WRITEMASK)
1427 ENCODING("VK16WM", ENCODING_WRITEMASK)
1428 errs() << "Unhandled mask register encoding " << s << "\n";
1429 llvm_unreachable("Unhandled mask register encoding");
1432 OperandEncoding RecognizableInstr::memoryEncodingFromString
1433 (const std::string &s,
1434 bool hasOpSizePrefix) {
1435 ENCODING("i16mem", ENCODING_RM)
1436 ENCODING("i32mem", ENCODING_RM)
1437 ENCODING("i64mem", ENCODING_RM)
1438 ENCODING("i8mem", ENCODING_RM)
1439 ENCODING("ssmem", ENCODING_RM)
1440 ENCODING("sdmem", ENCODING_RM)
1441 ENCODING("f128mem", ENCODING_RM)
1442 ENCODING("f256mem", ENCODING_RM)
1443 ENCODING("f512mem", ENCODING_RM)
1444 ENCODING("f64mem", ENCODING_RM)
1445 ENCODING("f32mem", ENCODING_RM)
1446 ENCODING("i128mem", ENCODING_RM)
1447 ENCODING("i256mem", ENCODING_RM)
1448 ENCODING("i512mem", ENCODING_RM)
1449 ENCODING("f80mem", ENCODING_RM)
1450 ENCODING("lea32mem", ENCODING_RM)
1451 ENCODING("lea64_32mem", ENCODING_RM)
1452 ENCODING("lea64mem", ENCODING_RM)
1453 ENCODING("opaque32mem", ENCODING_RM)
1454 ENCODING("opaque48mem", ENCODING_RM)
1455 ENCODING("opaque80mem", ENCODING_RM)
1456 ENCODING("opaque512mem", ENCODING_RM)
1457 ENCODING("vx32mem", ENCODING_RM)
1458 ENCODING("vy32mem", ENCODING_RM)
1459 ENCODING("vz32mem", ENCODING_RM)
1460 ENCODING("vx64mem", ENCODING_RM)
1461 ENCODING("vy64mem", ENCODING_RM)
1462 ENCODING("vy64xmem", ENCODING_RM)
1463 ENCODING("vz64mem", ENCODING_RM)
1464 errs() << "Unhandled memory encoding " << s << "\n";
1465 llvm_unreachable("Unhandled memory encoding");
1468 OperandEncoding RecognizableInstr::relocationEncodingFromString
1469 (const std::string &s,
1470 bool hasOpSizePrefix) {
1471 if(!hasOpSizePrefix) {
1472 // For instructions without an OpSize prefix, a declared 16-bit register or
1473 // immediate encoding is special.
1474 ENCODING("i16imm", ENCODING_IW)
1476 ENCODING("i16imm", ENCODING_Iv)
1477 ENCODING("i16i8imm", ENCODING_IB)
1478 ENCODING("i32imm", ENCODING_Iv)
1479 ENCODING("i32i8imm", ENCODING_IB)
1480 ENCODING("i64i32imm", ENCODING_ID)
1481 ENCODING("i64i8imm", ENCODING_IB)
1482 ENCODING("i8imm", ENCODING_IB)
1483 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1484 ENCODING("i16imm_pcrel", ENCODING_IW)
1485 ENCODING("i32imm_pcrel", ENCODING_ID)
1486 ENCODING("brtarget", ENCODING_Iv)
1487 ENCODING("brtarget8", ENCODING_IB)
1488 ENCODING("i64imm", ENCODING_IO)
1489 ENCODING("offset8", ENCODING_Ia)
1490 ENCODING("offset16", ENCODING_Ia)
1491 ENCODING("offset32", ENCODING_Ia)
1492 ENCODING("offset64", ENCODING_Ia)
1493 ENCODING("srcidx8", ENCODING_SI)
1494 ENCODING("srcidx16", ENCODING_SI)
1495 ENCODING("srcidx32", ENCODING_SI)
1496 ENCODING("srcidx64", ENCODING_SI)
1497 ENCODING("dstidx8", ENCODING_DI)
1498 ENCODING("dstidx16", ENCODING_DI)
1499 ENCODING("dstidx32", ENCODING_DI)
1500 ENCODING("dstidx64", ENCODING_DI)
1501 errs() << "Unhandled relocation encoding " << s << "\n";
1502 llvm_unreachable("Unhandled relocation encoding");
1505 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1506 (const std::string &s,
1507 bool hasOpSizePrefix) {
1508 ENCODING("GR32", ENCODING_Rv)
1509 ENCODING("GR64", ENCODING_RO)
1510 ENCODING("GR16", ENCODING_Rv)
1511 ENCODING("GR8", ENCODING_RB)
1512 ENCODING("GR16_NOAX", ENCODING_Rv)
1513 ENCODING("GR32_NOAX", ENCODING_Rv)
1514 ENCODING("GR64_NOAX", ENCODING_RO)
1515 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1516 llvm_unreachable("Unhandled opcode modifier encoding");