1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
64 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
65 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
66 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
67 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
70 #define MAP(from, to) MRM_##from = to,
79 D8 = 3, D9 = 4, DA = 5, DB = 6,
80 DC = 7, DD = 8, DE = 9, DF = 10,
83 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
84 XOP8 = 20, XOP9 = 21, XOPA = 22, PD = 23, T8PD = 24, TAPD = 25
88 // If rows are added to the opcode extension tables, then corresponding entries
89 // must be added here.
91 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
92 // that byte to ONE_BYTE_EXTENSION_TABLES.
94 // If the row corresponds to two bytes where the first is 0f, add an entry for
95 // the second byte to TWO_BYTE_EXTENSION_TABLES.
97 // If the row corresponds to some other set of bytes, you will need to modify
98 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
99 // to the X86 TD files, except in two cases: if the first two bytes of such a
100 // new combination are 0f 38 or 0f 3a, you just have to add maps called
101 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
102 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
103 // in RecognizableInstr::emitDecodePath().
105 #define ONE_BYTE_EXTENSION_TABLES \
106 EXTENSION_TABLE(80) \
107 EXTENSION_TABLE(81) \
108 EXTENSION_TABLE(82) \
109 EXTENSION_TABLE(83) \
110 EXTENSION_TABLE(8f) \
111 EXTENSION_TABLE(c0) \
112 EXTENSION_TABLE(c1) \
113 EXTENSION_TABLE(c6) \
114 EXTENSION_TABLE(c7) \
115 EXTENSION_TABLE(d0) \
116 EXTENSION_TABLE(d1) \
117 EXTENSION_TABLE(d2) \
118 EXTENSION_TABLE(d3) \
119 EXTENSION_TABLE(f6) \
120 EXTENSION_TABLE(f7) \
121 EXTENSION_TABLE(fe) \
124 #define TWO_BYTE_EXTENSION_TABLES \
125 EXTENSION_TABLE(00) \
126 EXTENSION_TABLE(01) \
127 EXTENSION_TABLE(0d) \
128 EXTENSION_TABLE(18) \
129 EXTENSION_TABLE(71) \
130 EXTENSION_TABLE(72) \
131 EXTENSION_TABLE(73) \
132 EXTENSION_TABLE(ae) \
133 EXTENSION_TABLE(ba) \
136 #define THREE_BYTE_38_EXTENSION_TABLES \
139 #define XOP9_MAP_EXTENSION_TABLES \
140 EXTENSION_TABLE(01) \
143 using namespace X86Disassembler;
145 /// needsModRMForDecode - Indicates whether a particular instruction requires a
146 /// ModR/M byte for the instruction to be properly decoded. For example, a
147 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
150 /// @param form - The form of the instruction.
151 /// @return - true if the form implies that a ModR/M byte is required, false
153 static bool needsModRMForDecode(uint8_t form) {
154 if (form == X86Local::MRMDestReg ||
155 form == X86Local::MRMDestMem ||
156 form == X86Local::MRMSrcReg ||
157 form == X86Local::MRMSrcMem ||
158 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
159 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
165 /// isRegFormat - Indicates whether a particular form requires the Mod field of
166 /// the ModR/M byte to be 0b11.
168 /// @param form - The form of the instruction.
169 /// @return - true if the form implies that Mod must be 0b11, false
171 static bool isRegFormat(uint8_t form) {
172 if (form == X86Local::MRMDestReg ||
173 form == X86Local::MRMSrcReg ||
174 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
180 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
181 /// Useful for switch statements and the like.
183 /// @param init - A reference to the BitsInit to be decoded.
184 /// @return - The field, with the first bit in the BitsInit as the lowest
186 static uint8_t byteFromBitsInit(BitsInit &init) {
187 int width = init.getNumBits();
189 assert(width <= 8 && "Field is too large for uint8_t!");
196 for (index = 0; index < width; index++) {
197 if (static_cast<BitInit*>(init.getBit(index))->getValue())
206 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
207 /// name of the field.
209 /// @param rec - The record from which to extract the value.
210 /// @param name - The name of the field in the record.
211 /// @return - The field, as translated by byteFromBitsInit().
212 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
213 BitsInit* bits = rec->getValueAsBitsInit(name);
214 return byteFromBitsInit(*bits);
217 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
218 const CodeGenInstruction &insn,
223 Name = Rec->getName();
224 Spec = &tables.specForUID(UID);
226 if (!Rec->isSubClassOf("X86Inst")) {
227 ShouldBeEmitted = false;
231 Prefix = byteFromRec(Rec, "Prefix");
232 Opcode = byteFromRec(Rec, "Opcode");
233 Form = byteFromRec(Rec, "FormBits");
235 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
236 HasOpSize16Prefix = Rec->getValueAsBit("hasOpSize16Prefix");
237 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
238 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
239 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
240 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
241 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
242 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
243 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
244 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
245 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
246 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
247 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
248 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
249 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
250 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
251 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
252 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
254 Name = Rec->getName();
255 AsmString = Rec->getValueAsString("AsmString");
257 Operands = &insn.Operands.OperandList;
259 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
261 // Check for 64-bit inst which does not require REX
264 // FIXME: Is there some better way to check for In64BitMode?
265 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
266 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
267 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
268 Predicates[i]->getName().find("In32Bit") != Name.npos) {
272 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
278 ShouldBeEmitted = true;
281 void RecognizableInstr::processInstr(DisassemblerTables &tables,
282 const CodeGenInstruction &insn,
285 // Ignore "asm parser only" instructions.
286 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
289 RecognizableInstr recogInstr(tables, insn, uid);
291 recogInstr.emitInstructionSpecifier();
293 if (recogInstr.shouldBeEmitted())
294 recogInstr.emitDecodePath(tables);
297 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
298 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
299 (HasEVEX_KZ ? n##_KZ : \
300 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
302 InstructionContext RecognizableInstr::insnContext() const {
303 InstructionContext insnContext;
306 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
307 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
308 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
311 if (HasVEX_LPrefix && HasVEX_WPrefix) {
312 if (HasOpSizePrefix || Prefix == X86Local::PD)
313 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
314 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
315 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
316 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
317 Prefix == X86Local::TAXD)
318 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
320 insnContext = EVEX_KB(IC_EVEX_L_W);
321 } else if (HasVEX_LPrefix) {
323 if (HasOpSizePrefix || Prefix == X86Local::PD ||
324 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
325 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
326 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
327 insnContext = EVEX_KB(IC_EVEX_L_XS);
328 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
329 Prefix == X86Local::TAXD)
330 insnContext = EVEX_KB(IC_EVEX_L_XD);
332 insnContext = EVEX_KB(IC_EVEX_L);
334 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
336 if (HasOpSizePrefix || Prefix == X86Local::PD ||
337 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
338 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
339 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
340 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
341 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
342 Prefix == X86Local::TAXD)
343 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
345 insnContext = EVEX_KB(IC_EVEX_L2_W);
346 } else if (HasEVEX_L2Prefix) {
348 if (HasOpSizePrefix || Prefix == X86Local::PD ||
349 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
350 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
351 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
352 Prefix == X86Local::TAXD)
353 insnContext = EVEX_KB(IC_EVEX_L2_XD);
354 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
355 insnContext = EVEX_KB(IC_EVEX_L2_XS);
357 insnContext = EVEX_KB(IC_EVEX_L2);
359 else if (HasVEX_WPrefix) {
361 if (HasOpSizePrefix || Prefix == X86Local::PD ||
362 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
363 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
364 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
365 insnContext = EVEX_KB(IC_EVEX_W_XS);
366 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
367 Prefix == X86Local::TAXD)
368 insnContext = EVEX_KB(IC_EVEX_W_XD);
370 insnContext = EVEX_KB(IC_EVEX_W);
373 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
374 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
375 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
376 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
377 Prefix == X86Local::TAXD)
378 insnContext = EVEX_KB(IC_EVEX_XD);
379 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
380 insnContext = EVEX_KB(IC_EVEX_XS);
382 insnContext = EVEX_KB(IC_EVEX);
384 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
385 if (HasVEX_LPrefix && HasVEX_WPrefix) {
386 if (HasOpSizePrefix || Prefix == X86Local::PD ||
387 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
388 insnContext = IC_VEX_L_W_OPSIZE;
389 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
390 insnContext = IC_VEX_L_W_XS;
391 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
392 Prefix == X86Local::TAXD)
393 insnContext = IC_VEX_L_W_XD;
395 insnContext = IC_VEX_L_W;
396 } else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
397 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
399 insnContext = IC_VEX_L_OPSIZE;
400 else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
401 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
403 insnContext = IC_VEX_W_OPSIZE;
404 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
405 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
406 insnContext = IC_VEX_OPSIZE;
407 else if (HasVEX_LPrefix &&
408 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
409 insnContext = IC_VEX_L_XS;
410 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
411 Prefix == X86Local::T8XD ||
412 Prefix == X86Local::TAXD))
413 insnContext = IC_VEX_L_XD;
414 else if (HasVEX_WPrefix &&
415 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
416 insnContext = IC_VEX_W_XS;
417 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
418 Prefix == X86Local::T8XD ||
419 Prefix == X86Local::TAXD))
420 insnContext = IC_VEX_W_XD;
421 else if (HasVEX_WPrefix)
422 insnContext = IC_VEX_W;
423 else if (HasVEX_LPrefix)
424 insnContext = IC_VEX_L;
425 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
426 Prefix == X86Local::TAXD)
427 insnContext = IC_VEX_XD;
428 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
429 insnContext = IC_VEX_XS;
431 insnContext = IC_VEX;
432 } else if (Is64Bit || HasREX_WPrefix) {
433 if (HasREX_WPrefix && (HasOpSizePrefix || Prefix == X86Local::PD ||
434 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD))
435 insnContext = IC_64BIT_REXW_OPSIZE;
436 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
437 Prefix == X86Local::T8XD ||
438 Prefix == X86Local::TAXD))
439 insnContext = IC_64BIT_XD_OPSIZE;
440 else if (HasOpSizePrefix &&
441 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
442 insnContext = IC_64BIT_XS_OPSIZE;
443 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
444 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
445 insnContext = IC_64BIT_OPSIZE;
446 else if (HasAdSizePrefix)
447 insnContext = IC_64BIT_ADSIZE;
448 else if (HasREX_WPrefix &&
449 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
450 insnContext = IC_64BIT_REXW_XS;
451 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
452 Prefix == X86Local::T8XD ||
453 Prefix == X86Local::TAXD))
454 insnContext = IC_64BIT_REXW_XD;
455 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
456 Prefix == X86Local::TAXD)
457 insnContext = IC_64BIT_XD;
458 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
459 insnContext = IC_64BIT_XS;
460 else if (HasREX_WPrefix)
461 insnContext = IC_64BIT_REXW;
463 insnContext = IC_64BIT;
465 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
466 Prefix == X86Local::T8XD ||
467 Prefix == X86Local::TAXD))
468 insnContext = IC_XD_OPSIZE;
469 else if (HasOpSizePrefix &&
470 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
471 insnContext = IC_XS_OPSIZE;
472 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
473 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
474 insnContext = IC_OPSIZE;
475 else if (HasAdSizePrefix)
476 insnContext = IC_ADSIZE;
477 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
478 Prefix == X86Local::TAXD)
480 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
481 Prefix == X86Local::REP)
490 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
495 // Filter out intrinsics
497 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
499 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
500 return FILTER_STRONG;
503 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
504 // printed as a separate "instruction".
512 // Filter out instructions with a LOCK prefix;
513 // prefer forms that do not have the prefix
519 if (Name == "VMASKMOVDQU64")
522 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
523 // For now, just prefer the REP versions.
524 if (Name == "XACQUIRE_PREFIX" ||
525 Name == "XRELEASE_PREFIX")
528 return FILTER_NORMAL;
531 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
532 unsigned &physicalOperandIndex,
533 unsigned &numPhysicalOperands,
534 const unsigned *operandMapping,
535 OperandEncoding (*encodingFromString)
537 bool hasOpSizePrefix)) {
539 if (physicalOperandIndex >= numPhysicalOperands)
542 assert(physicalOperandIndex < numPhysicalOperands);
545 while (operandMapping[operandIndex] != operandIndex) {
546 Spec->operands[operandIndex].encoding = ENCODING_DUP;
547 Spec->operands[operandIndex].type =
548 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
552 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
554 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
556 Spec->operands[operandIndex].type = typeFromString(typeName,
562 ++physicalOperandIndex;
565 void RecognizableInstr::emitInstructionSpecifier() {
568 if (!ShouldBeEmitted)
573 Spec->filtered = true;
576 ShouldBeEmitted = false;
582 Spec->insnContext = insnContext();
584 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
586 unsigned numOperands = OperandList.size();
587 unsigned numPhysicalOperands = 0;
589 // operandMapping maps from operands in OperandList to their originals.
590 // If operandMapping[i] != i, then the entry is a duplicate.
591 unsigned operandMapping[X86_MAX_OPERANDS];
592 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
594 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
595 if (OperandList[operandIndex].Constraints.size()) {
596 const CGIOperandList::ConstraintInfo &Constraint =
597 OperandList[operandIndex].Constraints[0];
598 if (Constraint.isTied()) {
599 operandMapping[operandIndex] = operandIndex;
600 operandMapping[Constraint.getTiedOperand()] = operandIndex;
602 ++numPhysicalOperands;
603 operandMapping[operandIndex] = operandIndex;
606 ++numPhysicalOperands;
607 operandMapping[operandIndex] = operandIndex;
611 #define HANDLE_OPERAND(class) \
612 handleOperand(false, \
614 physicalOperandIndex, \
615 numPhysicalOperands, \
617 class##EncodingFromString);
619 #define HANDLE_OPTIONAL(class) \
620 handleOperand(true, \
622 physicalOperandIndex, \
623 numPhysicalOperands, \
625 class##EncodingFromString);
627 // operandIndex should always be < numOperands
628 unsigned operandIndex = 0;
629 // physicalOperandIndex should always be < numPhysicalOperands
630 unsigned physicalOperandIndex = 0;
633 default: llvm_unreachable("Unhandled form");
634 case X86Local::RawFrmSrc:
635 HANDLE_OPERAND(relocation);
637 case X86Local::RawFrm:
638 // Operand 1 (optional) is an address or immediate.
639 // Operand 2 (optional) is an immediate.
640 assert(numPhysicalOperands <= 2 &&
641 "Unexpected number of operands for RawFrm");
642 HANDLE_OPTIONAL(relocation)
643 HANDLE_OPTIONAL(immediate)
645 case X86Local::RawFrmMemOffs:
646 // Operand 1 is an address.
647 HANDLE_OPERAND(relocation);
649 case X86Local::AddRegFrm:
650 // Operand 1 is added to the opcode.
651 // Operand 2 (optional) is an address.
652 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
653 "Unexpected number of operands for AddRegFrm");
654 HANDLE_OPERAND(opcodeModifier)
655 HANDLE_OPTIONAL(relocation)
657 case X86Local::MRMDestReg:
658 // Operand 1 is a register operand in the R/M field.
659 // Operand 2 is a register operand in the Reg/Opcode field.
660 // - In AVX, there is a register operand in the VEX.vvvv field here -
661 // Operand 3 (optional) is an immediate.
663 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
664 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
666 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
667 "Unexpected number of operands for MRMDestRegFrm");
669 HANDLE_OPERAND(rmRegister)
672 // FIXME: In AVX, the register below becomes the one encoded
673 // in ModRMVEX and the one above the one in the VEX.VVVV field
674 HANDLE_OPERAND(vvvvRegister)
676 HANDLE_OPERAND(roRegister)
677 HANDLE_OPTIONAL(immediate)
679 case X86Local::MRMDestMem:
680 // Operand 1 is a memory operand (possibly SIB-extended)
681 // Operand 2 is a register operand in the Reg/Opcode field.
682 // - In AVX, there is a register operand in the VEX.vvvv field here -
683 // Operand 3 (optional) is an immediate.
685 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
686 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
688 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
689 "Unexpected number of operands for MRMDestMemFrm");
690 HANDLE_OPERAND(memory)
693 HANDLE_OPERAND(writemaskRegister)
696 // FIXME: In AVX, the register below becomes the one encoded
697 // in ModRMVEX and the one above the one in the VEX.VVVV field
698 HANDLE_OPERAND(vvvvRegister)
700 HANDLE_OPERAND(roRegister)
701 HANDLE_OPTIONAL(immediate)
703 case X86Local::MRMSrcReg:
704 // Operand 1 is a register operand in the Reg/Opcode field.
705 // Operand 2 is a register operand in the R/M field.
706 // - In AVX, there is a register operand in the VEX.vvvv field here -
707 // Operand 3 (optional) is an immediate.
708 // Operand 4 (optional) is an immediate.
710 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
711 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
712 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
714 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
715 "Unexpected number of operands for MRMSrcRegFrm");
717 HANDLE_OPERAND(roRegister)
720 HANDLE_OPERAND(writemaskRegister)
723 // FIXME: In AVX, the register below becomes the one encoded
724 // in ModRMVEX and the one above the one in the VEX.VVVV field
725 HANDLE_OPERAND(vvvvRegister)
728 HANDLE_OPERAND(immediate)
730 HANDLE_OPERAND(rmRegister)
732 if (HasVEX_4VOp3Prefix)
733 HANDLE_OPERAND(vvvvRegister)
735 if (!HasMemOp4Prefix)
736 HANDLE_OPTIONAL(immediate)
737 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
738 HANDLE_OPTIONAL(immediate)
740 case X86Local::MRMSrcMem:
741 // Operand 1 is a register operand in the Reg/Opcode field.
742 // Operand 2 is a memory operand (possibly SIB-extended)
743 // - In AVX, there is a register operand in the VEX.vvvv field here -
744 // Operand 3 (optional) is an immediate.
746 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
747 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
748 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
750 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
751 "Unexpected number of operands for MRMSrcMemFrm");
753 HANDLE_OPERAND(roRegister)
756 HANDLE_OPERAND(writemaskRegister)
759 // FIXME: In AVX, the register below becomes the one encoded
760 // in ModRMVEX and the one above the one in the VEX.VVVV field
761 HANDLE_OPERAND(vvvvRegister)
764 HANDLE_OPERAND(immediate)
766 HANDLE_OPERAND(memory)
768 if (HasVEX_4VOp3Prefix)
769 HANDLE_OPERAND(vvvvRegister)
771 if (!HasMemOp4Prefix)
772 HANDLE_OPTIONAL(immediate)
773 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
775 case X86Local::MRM0r:
776 case X86Local::MRM1r:
777 case X86Local::MRM2r:
778 case X86Local::MRM3r:
779 case X86Local::MRM4r:
780 case X86Local::MRM5r:
781 case X86Local::MRM6r:
782 case X86Local::MRM7r:
784 // Operand 1 is a register operand in the R/M field.
785 // Operand 2 (optional) is an immediate or relocation.
786 // Operand 3 (optional) is an immediate.
787 unsigned kOp = (HasEVEX_K) ? 1:0;
788 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
789 if (numPhysicalOperands > 3 + kOp + Op4v)
790 llvm_unreachable("Unexpected number of operands for MRMnr");
793 HANDLE_OPERAND(vvvvRegister)
796 HANDLE_OPERAND(writemaskRegister)
797 HANDLE_OPTIONAL(rmRegister)
798 HANDLE_OPTIONAL(relocation)
799 HANDLE_OPTIONAL(immediate)
801 case X86Local::MRM0m:
802 case X86Local::MRM1m:
803 case X86Local::MRM2m:
804 case X86Local::MRM3m:
805 case X86Local::MRM4m:
806 case X86Local::MRM5m:
807 case X86Local::MRM6m:
808 case X86Local::MRM7m:
810 // Operand 1 is a memory operand (possibly SIB-extended)
811 // Operand 2 (optional) is an immediate or relocation.
812 unsigned kOp = (HasEVEX_K) ? 1:0;
813 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
814 if (numPhysicalOperands < 1 + kOp + Op4v ||
815 numPhysicalOperands > 2 + kOp + Op4v)
816 llvm_unreachable("Unexpected number of operands for MRMnm");
819 HANDLE_OPERAND(vvvvRegister)
821 HANDLE_OPERAND(writemaskRegister)
822 HANDLE_OPERAND(memory)
823 HANDLE_OPTIONAL(relocation)
825 case X86Local::RawFrmImm8:
826 // operand 1 is a 16-bit immediate
827 // operand 2 is an 8-bit immediate
828 assert(numPhysicalOperands == 2 &&
829 "Unexpected number of operands for X86Local::RawFrmImm8");
830 HANDLE_OPERAND(immediate)
831 HANDLE_OPERAND(immediate)
833 case X86Local::RawFrmImm16:
834 // operand 1 is a 16-bit immediate
835 // operand 2 is a 16-bit immediate
836 HANDLE_OPERAND(immediate)
837 HANDLE_OPERAND(immediate)
839 case X86Local::MRM_F8:
840 if (Opcode == 0xc6) {
841 assert(numPhysicalOperands == 1 &&
842 "Unexpected number of operands for X86Local::MRM_F8");
843 HANDLE_OPERAND(immediate)
844 } else if (Opcode == 0xc7) {
845 assert(numPhysicalOperands == 1 &&
846 "Unexpected number of operands for X86Local::MRM_F8");
847 HANDLE_OPERAND(relocation)
850 case X86Local::MRM_C1:
851 case X86Local::MRM_C2:
852 case X86Local::MRM_C3:
853 case X86Local::MRM_C4:
854 case X86Local::MRM_C8:
855 case X86Local::MRM_C9:
856 case X86Local::MRM_CA:
857 case X86Local::MRM_CB:
858 case X86Local::MRM_E8:
859 case X86Local::MRM_F0:
860 case X86Local::MRM_F9:
861 case X86Local::MRM_D0:
862 case X86Local::MRM_D1:
863 case X86Local::MRM_D4:
864 case X86Local::MRM_D5:
865 case X86Local::MRM_D6:
866 case X86Local::MRM_D8:
867 case X86Local::MRM_D9:
868 case X86Local::MRM_DA:
869 case X86Local::MRM_DB:
870 case X86Local::MRM_DC:
871 case X86Local::MRM_DD:
872 case X86Local::MRM_DE:
873 case X86Local::MRM_DF:
878 #undef HANDLE_OPERAND
879 #undef HANDLE_OPTIONAL
882 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
883 // Special cases where the LLVM tables are not complete
885 #define MAP(from, to) \
886 case X86Local::MRM_##from: \
887 filter = new ExactFilter(0x##from); \
890 OpcodeType opcodeType = (OpcodeType)-1;
892 ModRMFilter* filter = NULL;
893 uint8_t opcodeToSet = 0;
896 default: llvm_unreachable("Invalid prefix!");
897 // Extended two-byte opcodes can start with 66 0f, f2 0f, f3 0f, or 0f
902 opcodeType = TWOBYTE;
906 if (needsModRMForDecode(Form))
907 filter = new ModFilter(isRegFormat(Form));
909 filter = new DumbFilter();
911 #define EXTENSION_TABLE(n) case 0x##n:
912 TWO_BYTE_EXTENSION_TABLES
913 #undef EXTENSION_TABLE
916 llvm_unreachable("Unhandled two-byte extended opcode");
917 case X86Local::MRM0r:
918 case X86Local::MRM1r:
919 case X86Local::MRM2r:
920 case X86Local::MRM3r:
921 case X86Local::MRM4r:
922 case X86Local::MRM5r:
923 case X86Local::MRM6r:
924 case X86Local::MRM7r:
925 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
927 case X86Local::MRM0m:
928 case X86Local::MRM1m:
929 case X86Local::MRM2m:
930 case X86Local::MRM3m:
931 case X86Local::MRM4m:
932 case X86Local::MRM5m:
933 case X86Local::MRM6m:
934 case X86Local::MRM7m:
935 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
941 opcodeToSet = Opcode;
947 opcodeType = THREEBYTE_38;
950 if (needsModRMForDecode(Form))
951 filter = new ModFilter(isRegFormat(Form));
953 filter = new DumbFilter();
955 #define EXTENSION_TABLE(n) case 0x##n:
956 THREE_BYTE_38_EXTENSION_TABLES
957 #undef EXTENSION_TABLE
960 llvm_unreachable("Unhandled two-byte extended opcode");
961 case X86Local::MRM0r:
962 case X86Local::MRM1r:
963 case X86Local::MRM2r:
964 case X86Local::MRM3r:
965 case X86Local::MRM4r:
966 case X86Local::MRM5r:
967 case X86Local::MRM6r:
968 case X86Local::MRM7r:
969 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
971 case X86Local::MRM0m:
972 case X86Local::MRM1m:
973 case X86Local::MRM2m:
974 case X86Local::MRM3m:
975 case X86Local::MRM4m:
976 case X86Local::MRM5m:
977 case X86Local::MRM6m:
978 case X86Local::MRM7m:
979 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
985 opcodeToSet = Opcode;
990 opcodeType = THREEBYTE_3A;
991 if (needsModRMForDecode(Form))
992 filter = new ModFilter(isRegFormat(Form));
994 filter = new DumbFilter();
995 opcodeToSet = Opcode;
998 opcodeType = THREEBYTE_A6;
999 if (needsModRMForDecode(Form))
1000 filter = new ModFilter(isRegFormat(Form));
1002 filter = new DumbFilter();
1003 opcodeToSet = Opcode;
1006 opcodeType = THREEBYTE_A7;
1007 if (needsModRMForDecode(Form))
1008 filter = new ModFilter(isRegFormat(Form));
1010 filter = new DumbFilter();
1011 opcodeToSet = Opcode;
1013 case X86Local::XOP8:
1014 opcodeType = XOP8_MAP;
1015 if (needsModRMForDecode(Form))
1016 filter = new ModFilter(isRegFormat(Form));
1018 filter = new DumbFilter();
1019 opcodeToSet = Opcode;
1021 case X86Local::XOP9:
1022 opcodeType = XOP9_MAP;
1025 if (needsModRMForDecode(Form))
1026 filter = new ModFilter(isRegFormat(Form));
1028 filter = new DumbFilter();
1030 #define EXTENSION_TABLE(n) case 0x##n:
1031 XOP9_MAP_EXTENSION_TABLES
1032 #undef EXTENSION_TABLE
1035 llvm_unreachable("Unhandled XOP9 extended opcode");
1036 case X86Local::MRM0r:
1037 case X86Local::MRM1r:
1038 case X86Local::MRM2r:
1039 case X86Local::MRM3r:
1040 case X86Local::MRM4r:
1041 case X86Local::MRM5r:
1042 case X86Local::MRM6r:
1043 case X86Local::MRM7r:
1044 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1046 case X86Local::MRM0m:
1047 case X86Local::MRM1m:
1048 case X86Local::MRM2m:
1049 case X86Local::MRM3m:
1050 case X86Local::MRM4m:
1051 case X86Local::MRM5m:
1052 case X86Local::MRM6m:
1053 case X86Local::MRM7m:
1054 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1059 } // switch (Opcode)
1060 opcodeToSet = Opcode;
1062 case X86Local::XOPA:
1063 opcodeType = XOPA_MAP;
1064 if (needsModRMForDecode(Form))
1065 filter = new ModFilter(isRegFormat(Form));
1067 filter = new DumbFilter();
1068 opcodeToSet = Opcode;
1078 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1079 assert(Form == X86Local::RawFrm);
1080 opcodeType = ONEBYTE;
1081 filter = new ExactFilter(Opcode);
1082 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1086 opcodeType = ONEBYTE;
1088 #define EXTENSION_TABLE(n) case 0x##n:
1089 ONE_BYTE_EXTENSION_TABLES
1090 #undef EXTENSION_TABLE
1093 llvm_unreachable("Fell through the cracks of a single-byte "
1095 case X86Local::MRM0r:
1096 case X86Local::MRM1r:
1097 case X86Local::MRM2r:
1098 case X86Local::MRM3r:
1099 case X86Local::MRM4r:
1100 case X86Local::MRM5r:
1101 case X86Local::MRM6r:
1102 case X86Local::MRM7r:
1103 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1105 case X86Local::MRM0m:
1106 case X86Local::MRM1m:
1107 case X86Local::MRM2m:
1108 case X86Local::MRM3m:
1109 case X86Local::MRM4m:
1110 case X86Local::MRM5m:
1111 case X86Local::MRM6m:
1112 case X86Local::MRM7m:
1113 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1128 llvm_unreachable("Unhandled escape opcode form");
1129 case X86Local::MRM0r:
1130 case X86Local::MRM1r:
1131 case X86Local::MRM2r:
1132 case X86Local::MRM3r:
1133 case X86Local::MRM4r:
1134 case X86Local::MRM5r:
1135 case X86Local::MRM6r:
1136 case X86Local::MRM7r:
1137 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1139 case X86Local::MRM0m:
1140 case X86Local::MRM1m:
1141 case X86Local::MRM2m:
1142 case X86Local::MRM3m:
1143 case X86Local::MRM4m:
1144 case X86Local::MRM5m:
1145 case X86Local::MRM6m:
1146 case X86Local::MRM7m:
1147 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1152 if (needsModRMForDecode(Form))
1153 filter = new ModFilter(isRegFormat(Form));
1155 filter = new DumbFilter();
1157 } // switch (Opcode)
1158 opcodeToSet = Opcode;
1159 } // switch (Prefix)
1161 assert(opcodeType != (OpcodeType)-1 &&
1162 "Opcode type not set");
1163 assert(filter && "Filter not set");
1165 if (Form == X86Local::AddRegFrm) {
1166 assert(((opcodeToSet & 7) == 0) &&
1167 "ADDREG_FRM opcode not aligned");
1169 uint8_t currentOpcode;
1171 for (currentOpcode = opcodeToSet;
1172 currentOpcode < opcodeToSet + 8;
1174 tables.setTableFields(opcodeType,
1178 UID, Is32Bit, IgnoresVEX_L);
1180 tables.setTableFields(opcodeType,
1184 UID, Is32Bit, IgnoresVEX_L);
1192 #define TYPE(str, type) if (s == str) return type;
1193 OperandType RecognizableInstr::typeFromString(const std::string &s,
1194 bool hasREX_WPrefix,
1195 bool hasOpSizePrefix,
1196 bool hasOpSize16Prefix) {
1197 if(hasREX_WPrefix) {
1198 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1200 TYPE("GR32", TYPE_R32)
1202 if(hasOpSizePrefix) {
1203 // For instructions with an OpSize prefix, a declared 16-bit register or
1204 // immediate encoding is special.
1205 TYPE("GR16", TYPE_Rv)
1206 TYPE("i16imm", TYPE_IMMv)
1208 if(hasOpSize16Prefix) {
1209 // For instructions with an OpSize16 prefix, a declared 32-bit register or
1210 // immediate encoding is special.
1211 TYPE("GR32", TYPE_Rv)
1213 TYPE("i16mem", TYPE_Mv)
1214 TYPE("i16imm", TYPE_IMM16)
1215 TYPE("i16i8imm", TYPE_IMMv)
1216 TYPE("GR16", TYPE_R16)
1217 TYPE("i32mem", TYPE_Mv)
1218 TYPE("i32imm", TYPE_IMMv)
1219 TYPE("i32i8imm", TYPE_IMM32)
1220 TYPE("u32u8imm", TYPE_IMM32)
1221 TYPE("GR32", TYPE_R32)
1222 TYPE("GR32orGR64", TYPE_R32)
1223 TYPE("i64mem", TYPE_Mv)
1224 TYPE("i64i32imm", TYPE_IMM64)
1225 TYPE("i64i8imm", TYPE_IMM64)
1226 TYPE("GR64", TYPE_R64)
1227 TYPE("i8mem", TYPE_M8)
1228 TYPE("i8imm", TYPE_IMM8)
1229 TYPE("GR8", TYPE_R8)
1230 TYPE("VR128", TYPE_XMM128)
1231 TYPE("VR128X", TYPE_XMM128)
1232 TYPE("f128mem", TYPE_M128)
1233 TYPE("f256mem", TYPE_M256)
1234 TYPE("f512mem", TYPE_M512)
1235 TYPE("FR64", TYPE_XMM64)
1236 TYPE("FR64X", TYPE_XMM64)
1237 TYPE("f64mem", TYPE_M64FP)
1238 TYPE("sdmem", TYPE_M64FP)
1239 TYPE("FR32", TYPE_XMM32)
1240 TYPE("FR32X", TYPE_XMM32)
1241 TYPE("f32mem", TYPE_M32FP)
1242 TYPE("ssmem", TYPE_M32FP)
1243 TYPE("RST", TYPE_ST)
1244 TYPE("i128mem", TYPE_M128)
1245 TYPE("i256mem", TYPE_M256)
1246 TYPE("i512mem", TYPE_M512)
1247 TYPE("i64i32imm_pcrel", TYPE_REL64)
1248 TYPE("i16imm_pcrel", TYPE_REL16)
1249 TYPE("i32imm_pcrel", TYPE_REL32)
1250 TYPE("SSECC", TYPE_IMM3)
1251 TYPE("AVXCC", TYPE_IMM5)
1252 TYPE("AVX512RC", TYPE_IMM32)
1253 TYPE("brtarget", TYPE_RELv)
1254 TYPE("uncondbrtarget", TYPE_RELv)
1255 TYPE("brtarget8", TYPE_REL8)
1256 TYPE("f80mem", TYPE_M80FP)
1257 TYPE("lea32mem", TYPE_LEA)
1258 TYPE("lea64_32mem", TYPE_LEA)
1259 TYPE("lea64mem", TYPE_LEA)
1260 TYPE("VR64", TYPE_MM64)
1261 TYPE("i64imm", TYPE_IMMv)
1262 TYPE("opaque32mem", TYPE_M1616)
1263 TYPE("opaque48mem", TYPE_M1632)
1264 TYPE("opaque80mem", TYPE_M1664)
1265 TYPE("opaque512mem", TYPE_M512)
1266 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1267 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1268 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1269 TYPE("srcidx8", TYPE_SRCIDX8)
1270 TYPE("srcidx16", TYPE_SRCIDX16)
1271 TYPE("srcidx32", TYPE_SRCIDX32)
1272 TYPE("srcidx64", TYPE_SRCIDX64)
1273 TYPE("offset8", TYPE_MOFFS8)
1274 TYPE("offset16", TYPE_MOFFS16)
1275 TYPE("offset32", TYPE_MOFFS32)
1276 TYPE("offset64", TYPE_MOFFS64)
1277 TYPE("VR256", TYPE_XMM256)
1278 TYPE("VR256X", TYPE_XMM256)
1279 TYPE("VR512", TYPE_XMM512)
1280 TYPE("VK1", TYPE_VK1)
1281 TYPE("VK1WM", TYPE_VK1)
1282 TYPE("VK8", TYPE_VK8)
1283 TYPE("VK8WM", TYPE_VK8)
1284 TYPE("VK16", TYPE_VK16)
1285 TYPE("VK16WM", TYPE_VK16)
1286 TYPE("GR16_NOAX", TYPE_Rv)
1287 TYPE("GR32_NOAX", TYPE_Rv)
1288 TYPE("GR64_NOAX", TYPE_R64)
1289 TYPE("vx32mem", TYPE_M32)
1290 TYPE("vy32mem", TYPE_M32)
1291 TYPE("vz32mem", TYPE_M32)
1292 TYPE("vx64mem", TYPE_M64)
1293 TYPE("vy64mem", TYPE_M64)
1294 TYPE("vy64xmem", TYPE_M64)
1295 TYPE("vz64mem", TYPE_M64)
1296 errs() << "Unhandled type string " << s << "\n";
1297 llvm_unreachable("Unhandled type string");
1301 #define ENCODING(str, encoding) if (s == str) return encoding;
1302 OperandEncoding RecognizableInstr::immediateEncodingFromString
1303 (const std::string &s,
1304 bool hasOpSizePrefix) {
1305 if(!hasOpSizePrefix) {
1306 // For instructions without an OpSize prefix, a declared 16-bit register or
1307 // immediate encoding is special.
1308 ENCODING("i16imm", ENCODING_IW)
1310 ENCODING("i32i8imm", ENCODING_IB)
1311 ENCODING("u32u8imm", ENCODING_IB)
1312 ENCODING("SSECC", ENCODING_IB)
1313 ENCODING("AVXCC", ENCODING_IB)
1314 ENCODING("AVX512RC", ENCODING_IB)
1315 ENCODING("i16imm", ENCODING_Iv)
1316 ENCODING("i16i8imm", ENCODING_IB)
1317 ENCODING("i32imm", ENCODING_Iv)
1318 ENCODING("i64i32imm", ENCODING_ID)
1319 ENCODING("i64i8imm", ENCODING_IB)
1320 ENCODING("i8imm", ENCODING_IB)
1321 // This is not a typo. Instructions like BLENDVPD put
1322 // register IDs in 8-bit immediates nowadays.
1323 ENCODING("FR32", ENCODING_IB)
1324 ENCODING("FR64", ENCODING_IB)
1325 ENCODING("VR128", ENCODING_IB)
1326 ENCODING("VR256", ENCODING_IB)
1327 ENCODING("FR32X", ENCODING_IB)
1328 ENCODING("FR64X", ENCODING_IB)
1329 ENCODING("VR128X", ENCODING_IB)
1330 ENCODING("VR256X", ENCODING_IB)
1331 ENCODING("VR512", ENCODING_IB)
1332 errs() << "Unhandled immediate encoding " << s << "\n";
1333 llvm_unreachable("Unhandled immediate encoding");
1336 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1337 (const std::string &s,
1338 bool hasOpSizePrefix) {
1339 ENCODING("RST", ENCODING_FP)
1340 ENCODING("GR16", ENCODING_RM)
1341 ENCODING("GR32", ENCODING_RM)
1342 ENCODING("GR32orGR64", ENCODING_RM)
1343 ENCODING("GR64", ENCODING_RM)
1344 ENCODING("GR8", ENCODING_RM)
1345 ENCODING("VR128", ENCODING_RM)
1346 ENCODING("VR128X", ENCODING_RM)
1347 ENCODING("FR64", ENCODING_RM)
1348 ENCODING("FR32", ENCODING_RM)
1349 ENCODING("FR64X", ENCODING_RM)
1350 ENCODING("FR32X", ENCODING_RM)
1351 ENCODING("VR64", ENCODING_RM)
1352 ENCODING("VR256", ENCODING_RM)
1353 ENCODING("VR256X", ENCODING_RM)
1354 ENCODING("VR512", ENCODING_RM)
1355 ENCODING("VK1", ENCODING_RM)
1356 ENCODING("VK8", ENCODING_RM)
1357 ENCODING("VK16", ENCODING_RM)
1358 errs() << "Unhandled R/M register encoding " << s << "\n";
1359 llvm_unreachable("Unhandled R/M register encoding");
1362 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1363 (const std::string &s,
1364 bool hasOpSizePrefix) {
1365 ENCODING("GR16", ENCODING_REG)
1366 ENCODING("GR32", ENCODING_REG)
1367 ENCODING("GR32orGR64", ENCODING_REG)
1368 ENCODING("GR64", ENCODING_REG)
1369 ENCODING("GR8", ENCODING_REG)
1370 ENCODING("VR128", ENCODING_REG)
1371 ENCODING("FR64", ENCODING_REG)
1372 ENCODING("FR32", ENCODING_REG)
1373 ENCODING("VR64", ENCODING_REG)
1374 ENCODING("SEGMENT_REG", ENCODING_REG)
1375 ENCODING("DEBUG_REG", ENCODING_REG)
1376 ENCODING("CONTROL_REG", ENCODING_REG)
1377 ENCODING("VR256", ENCODING_REG)
1378 ENCODING("VR256X", ENCODING_REG)
1379 ENCODING("VR128X", ENCODING_REG)
1380 ENCODING("FR64X", ENCODING_REG)
1381 ENCODING("FR32X", ENCODING_REG)
1382 ENCODING("VR512", ENCODING_REG)
1383 ENCODING("VK1", ENCODING_REG)
1384 ENCODING("VK8", ENCODING_REG)
1385 ENCODING("VK16", ENCODING_REG)
1386 ENCODING("VK1WM", ENCODING_REG)
1387 ENCODING("VK8WM", ENCODING_REG)
1388 ENCODING("VK16WM", ENCODING_REG)
1389 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1390 llvm_unreachable("Unhandled reg/opcode register encoding");
1393 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1394 (const std::string &s,
1395 bool hasOpSizePrefix) {
1396 ENCODING("GR32", ENCODING_VVVV)
1397 ENCODING("GR64", ENCODING_VVVV)
1398 ENCODING("FR32", ENCODING_VVVV)
1399 ENCODING("FR64", ENCODING_VVVV)
1400 ENCODING("VR128", ENCODING_VVVV)
1401 ENCODING("VR256", ENCODING_VVVV)
1402 ENCODING("FR32X", ENCODING_VVVV)
1403 ENCODING("FR64X", ENCODING_VVVV)
1404 ENCODING("VR128X", ENCODING_VVVV)
1405 ENCODING("VR256X", ENCODING_VVVV)
1406 ENCODING("VR512", ENCODING_VVVV)
1407 ENCODING("VK1", ENCODING_VVVV)
1408 ENCODING("VK8", ENCODING_VVVV)
1409 ENCODING("VK16", ENCODING_VVVV)
1410 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1411 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1414 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1415 (const std::string &s,
1416 bool hasOpSizePrefix) {
1417 ENCODING("VK1WM", ENCODING_WRITEMASK)
1418 ENCODING("VK8WM", ENCODING_WRITEMASK)
1419 ENCODING("VK16WM", ENCODING_WRITEMASK)
1420 errs() << "Unhandled mask register encoding " << s << "\n";
1421 llvm_unreachable("Unhandled mask register encoding");
1424 OperandEncoding RecognizableInstr::memoryEncodingFromString
1425 (const std::string &s,
1426 bool hasOpSizePrefix) {
1427 ENCODING("i16mem", ENCODING_RM)
1428 ENCODING("i32mem", ENCODING_RM)
1429 ENCODING("i64mem", ENCODING_RM)
1430 ENCODING("i8mem", ENCODING_RM)
1431 ENCODING("ssmem", ENCODING_RM)
1432 ENCODING("sdmem", ENCODING_RM)
1433 ENCODING("f128mem", ENCODING_RM)
1434 ENCODING("f256mem", ENCODING_RM)
1435 ENCODING("f512mem", ENCODING_RM)
1436 ENCODING("f64mem", ENCODING_RM)
1437 ENCODING("f32mem", ENCODING_RM)
1438 ENCODING("i128mem", ENCODING_RM)
1439 ENCODING("i256mem", ENCODING_RM)
1440 ENCODING("i512mem", ENCODING_RM)
1441 ENCODING("f80mem", ENCODING_RM)
1442 ENCODING("lea32mem", ENCODING_RM)
1443 ENCODING("lea64_32mem", ENCODING_RM)
1444 ENCODING("lea64mem", ENCODING_RM)
1445 ENCODING("opaque32mem", ENCODING_RM)
1446 ENCODING("opaque48mem", ENCODING_RM)
1447 ENCODING("opaque80mem", ENCODING_RM)
1448 ENCODING("opaque512mem", ENCODING_RM)
1449 ENCODING("vx32mem", ENCODING_RM)
1450 ENCODING("vy32mem", ENCODING_RM)
1451 ENCODING("vz32mem", ENCODING_RM)
1452 ENCODING("vx64mem", ENCODING_RM)
1453 ENCODING("vy64mem", ENCODING_RM)
1454 ENCODING("vy64xmem", ENCODING_RM)
1455 ENCODING("vz64mem", ENCODING_RM)
1456 errs() << "Unhandled memory encoding " << s << "\n";
1457 llvm_unreachable("Unhandled memory encoding");
1460 OperandEncoding RecognizableInstr::relocationEncodingFromString
1461 (const std::string &s,
1462 bool hasOpSizePrefix) {
1463 if(!hasOpSizePrefix) {
1464 // For instructions without an OpSize prefix, a declared 16-bit register or
1465 // immediate encoding is special.
1466 ENCODING("i16imm", ENCODING_IW)
1468 ENCODING("i16imm", ENCODING_Iv)
1469 ENCODING("i16i8imm", ENCODING_IB)
1470 ENCODING("i32imm", ENCODING_Iv)
1471 ENCODING("i32i8imm", ENCODING_IB)
1472 ENCODING("i64i32imm", ENCODING_ID)
1473 ENCODING("i64i8imm", ENCODING_IB)
1474 ENCODING("i8imm", ENCODING_IB)
1475 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1476 ENCODING("i16imm_pcrel", ENCODING_IW)
1477 ENCODING("i32imm_pcrel", ENCODING_ID)
1478 ENCODING("brtarget", ENCODING_Iv)
1479 ENCODING("brtarget8", ENCODING_IB)
1480 ENCODING("i64imm", ENCODING_IO)
1481 ENCODING("offset8", ENCODING_Ia)
1482 ENCODING("offset16", ENCODING_Ia)
1483 ENCODING("offset32", ENCODING_Ia)
1484 ENCODING("offset64", ENCODING_Ia)
1485 ENCODING("srcidx8", ENCODING_SI)
1486 ENCODING("srcidx16", ENCODING_SI)
1487 ENCODING("srcidx32", ENCODING_SI)
1488 ENCODING("srcidx64", ENCODING_SI)
1489 errs() << "Unhandled relocation encoding " << s << "\n";
1490 llvm_unreachable("Unhandled relocation encoding");
1493 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1494 (const std::string &s,
1495 bool hasOpSizePrefix) {
1496 ENCODING("GR32", ENCODING_Rv)
1497 ENCODING("GR64", ENCODING_RO)
1498 ENCODING("GR16", ENCODING_Rv)
1499 ENCODING("GR8", ENCODING_RB)
1500 ENCODING("GR16_NOAX", ENCODING_Rv)
1501 ENCODING("GR32_NOAX", ENCODING_Rv)
1502 ENCODING("GR64_NOAX", ENCODING_RO)
1503 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1504 llvm_unreachable("Unhandled opcode modifier encoding");