1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
135 #define THREE_BYTE_38_EXTENSION_TABLES \
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
234 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
235 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
236 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
237 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
238 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
239 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
240 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
241 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
242 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
243 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
244 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
245 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
246 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
247 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
248 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
249 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
250 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
252 Name = Rec->getName();
253 AsmString = Rec->getValueAsString("AsmString");
255 Operands = &insn.Operands.OperandList;
257 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
258 (Name.find("CRC32") != Name.npos);
259 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
261 // Check for 64-bit inst which does not require REX
264 // FIXME: Is there some better way to check for In64BitMode?
265 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
266 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
267 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
268 Predicates[i]->getName().find("In32Bit") != Name.npos) {
272 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
278 ShouldBeEmitted = true;
281 void RecognizableInstr::processInstr(DisassemblerTables &tables,
282 const CodeGenInstruction &insn,
285 // Ignore "asm parser only" instructions.
286 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
289 RecognizableInstr recogInstr(tables, insn, uid);
291 recogInstr.emitInstructionSpecifier();
293 if (recogInstr.shouldBeEmitted())
294 recogInstr.emitDecodePath(tables);
297 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
298 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
299 (HasEVEX_KZ ? n##_KZ : \
300 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
302 InstructionContext RecognizableInstr::insnContext() const {
303 InstructionContext insnContext;
306 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
307 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
308 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
311 if (HasVEX_LPrefix && HasVEX_WPrefix) {
313 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
314 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
315 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
316 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
317 Prefix == X86Local::TAXD)
318 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
320 insnContext = EVEX_KB(IC_EVEX_L_W);
321 } else if (HasVEX_LPrefix) {
324 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
325 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
326 insnContext = EVEX_KB(IC_EVEX_L_XS);
327 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
328 Prefix == X86Local::TAXD)
329 insnContext = EVEX_KB(IC_EVEX_L_XD);
331 insnContext = EVEX_KB(IC_EVEX_L);
333 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
336 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
337 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
338 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
339 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
340 Prefix == X86Local::TAXD)
341 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
343 insnContext = EVEX_KB(IC_EVEX_L2_W);
344 } else if (HasEVEX_L2Prefix) {
347 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
348 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
349 Prefix == X86Local::TAXD)
350 insnContext = EVEX_KB(IC_EVEX_L2_XD);
351 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
352 insnContext = EVEX_KB(IC_EVEX_L2_XS);
354 insnContext = EVEX_KB(IC_EVEX_L2);
356 else if (HasVEX_WPrefix) {
359 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
360 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
361 insnContext = EVEX_KB(IC_EVEX_W_XS);
362 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
363 Prefix == X86Local::TAXD)
364 insnContext = EVEX_KB(IC_EVEX_W_XD);
366 insnContext = EVEX_KB(IC_EVEX_W);
369 else if (HasOpSizePrefix)
370 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
371 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
372 Prefix == X86Local::TAXD)
373 insnContext = EVEX_KB(IC_EVEX_XD);
374 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
375 insnContext = EVEX_KB(IC_EVEX_XS);
377 insnContext = EVEX_KB(IC_EVEX);
379 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
380 if (HasVEX_LPrefix && HasVEX_WPrefix) {
382 insnContext = IC_VEX_L_W_OPSIZE;
383 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
384 insnContext = IC_VEX_L_W_XS;
385 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
386 Prefix == X86Local::TAXD)
387 insnContext = IC_VEX_L_W_XD;
389 insnContext = IC_VEX_L_W;
390 } else if (HasOpSizePrefix && HasVEX_LPrefix)
391 insnContext = IC_VEX_L_OPSIZE;
392 else if (HasOpSizePrefix && HasVEX_WPrefix)
393 insnContext = IC_VEX_W_OPSIZE;
394 else if (HasOpSizePrefix)
395 insnContext = IC_VEX_OPSIZE;
396 else if (HasVEX_LPrefix &&
397 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
398 insnContext = IC_VEX_L_XS;
399 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
400 Prefix == X86Local::T8XD ||
401 Prefix == X86Local::TAXD))
402 insnContext = IC_VEX_L_XD;
403 else if (HasVEX_WPrefix &&
404 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
405 insnContext = IC_VEX_W_XS;
406 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
407 Prefix == X86Local::T8XD ||
408 Prefix == X86Local::TAXD))
409 insnContext = IC_VEX_W_XD;
410 else if (HasVEX_WPrefix)
411 insnContext = IC_VEX_W;
412 else if (HasVEX_LPrefix)
413 insnContext = IC_VEX_L;
414 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
415 Prefix == X86Local::TAXD)
416 insnContext = IC_VEX_XD;
417 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
418 insnContext = IC_VEX_XS;
420 insnContext = IC_VEX;
421 } else if (Is64Bit || HasREX_WPrefix) {
422 if (HasREX_WPrefix && HasOpSizePrefix)
423 insnContext = IC_64BIT_REXW_OPSIZE;
424 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
425 Prefix == X86Local::T8XD ||
426 Prefix == X86Local::TAXD))
427 insnContext = IC_64BIT_XD_OPSIZE;
428 else if (HasOpSizePrefix &&
429 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
430 insnContext = IC_64BIT_XS_OPSIZE;
431 else if (HasOpSizePrefix)
432 insnContext = IC_64BIT_OPSIZE;
433 else if (HasAdSizePrefix)
434 insnContext = IC_64BIT_ADSIZE;
435 else if (HasREX_WPrefix &&
436 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
437 insnContext = IC_64BIT_REXW_XS;
438 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
439 Prefix == X86Local::T8XD ||
440 Prefix == X86Local::TAXD))
441 insnContext = IC_64BIT_REXW_XD;
442 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
443 Prefix == X86Local::TAXD)
444 insnContext = IC_64BIT_XD;
445 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
446 insnContext = IC_64BIT_XS;
447 else if (HasREX_WPrefix)
448 insnContext = IC_64BIT_REXW;
450 insnContext = IC_64BIT;
452 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
453 Prefix == X86Local::T8XD ||
454 Prefix == X86Local::TAXD))
455 insnContext = IC_XD_OPSIZE;
456 else if (HasOpSizePrefix &&
457 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
458 insnContext = IC_XS_OPSIZE;
459 else if (HasOpSizePrefix)
460 insnContext = IC_OPSIZE;
461 else if (HasAdSizePrefix)
462 insnContext = IC_ADSIZE;
463 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
464 Prefix == X86Local::TAXD)
466 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
467 Prefix == X86Local::REP)
476 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
481 // Filter out intrinsics
483 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
485 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
486 return FILTER_STRONG;
489 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
490 // printed as a separate "instruction".
498 // Filter out instructions with a LOCK prefix;
499 // prefer forms that do not have the prefix
505 if (Name == "VMASKMOVDQU64")
508 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
509 // For now, just prefer the REP versions.
510 if (Name == "XACQUIRE_PREFIX" ||
511 Name == "XRELEASE_PREFIX")
514 return FILTER_NORMAL;
517 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
518 unsigned &physicalOperandIndex,
519 unsigned &numPhysicalOperands,
520 const unsigned *operandMapping,
521 OperandEncoding (*encodingFromString)
523 bool hasOpSizePrefix)) {
525 if (physicalOperandIndex >= numPhysicalOperands)
528 assert(physicalOperandIndex < numPhysicalOperands);
531 while (operandMapping[operandIndex] != operandIndex) {
532 Spec->operands[operandIndex].encoding = ENCODING_DUP;
533 Spec->operands[operandIndex].type =
534 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
538 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
540 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
542 Spec->operands[operandIndex].type = typeFromString(typeName,
548 ++physicalOperandIndex;
551 void RecognizableInstr::emitInstructionSpecifier() {
554 if (!ShouldBeEmitted)
559 Spec->filtered = true;
562 ShouldBeEmitted = false;
568 Spec->insnContext = insnContext();
570 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
572 unsigned numOperands = OperandList.size();
573 unsigned numPhysicalOperands = 0;
575 // operandMapping maps from operands in OperandList to their originals.
576 // If operandMapping[i] != i, then the entry is a duplicate.
577 unsigned operandMapping[X86_MAX_OPERANDS];
578 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
580 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
581 if (OperandList[operandIndex].Constraints.size()) {
582 const CGIOperandList::ConstraintInfo &Constraint =
583 OperandList[operandIndex].Constraints[0];
584 if (Constraint.isTied()) {
585 operandMapping[operandIndex] = operandIndex;
586 operandMapping[Constraint.getTiedOperand()] = operandIndex;
588 ++numPhysicalOperands;
589 operandMapping[operandIndex] = operandIndex;
592 ++numPhysicalOperands;
593 operandMapping[operandIndex] = operandIndex;
597 #define HANDLE_OPERAND(class) \
598 handleOperand(false, \
600 physicalOperandIndex, \
601 numPhysicalOperands, \
603 class##EncodingFromString);
605 #define HANDLE_OPTIONAL(class) \
606 handleOperand(true, \
608 physicalOperandIndex, \
609 numPhysicalOperands, \
611 class##EncodingFromString);
613 // operandIndex should always be < numOperands
614 unsigned operandIndex = 0;
615 // physicalOperandIndex should always be < numPhysicalOperands
616 unsigned physicalOperandIndex = 0;
619 case X86Local::RawFrm:
620 // Operand 1 (optional) is an address or immediate.
621 // Operand 2 (optional) is an immediate.
622 assert(numPhysicalOperands <= 2 &&
623 "Unexpected number of operands for RawFrm");
624 HANDLE_OPTIONAL(relocation)
625 HANDLE_OPTIONAL(immediate)
627 case X86Local::AddRegFrm:
628 // Operand 1 is added to the opcode.
629 // Operand 2 (optional) is an address.
630 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
631 "Unexpected number of operands for AddRegFrm");
632 HANDLE_OPERAND(opcodeModifier)
633 HANDLE_OPTIONAL(relocation)
635 case X86Local::MRMDestReg:
636 // Operand 1 is a register operand in the R/M field.
637 // Operand 2 is a register operand in the Reg/Opcode field.
638 // - In AVX, there is a register operand in the VEX.vvvv field here -
639 // Operand 3 (optional) is an immediate.
641 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
642 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
644 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
645 "Unexpected number of operands for MRMDestRegFrm");
647 HANDLE_OPERAND(rmRegister)
650 // FIXME: In AVX, the register below becomes the one encoded
651 // in ModRMVEX and the one above the one in the VEX.VVVV field
652 HANDLE_OPERAND(vvvvRegister)
654 HANDLE_OPERAND(roRegister)
655 HANDLE_OPTIONAL(immediate)
657 case X86Local::MRMDestMem:
658 // Operand 1 is a memory operand (possibly SIB-extended)
659 // Operand 2 is a register operand in the Reg/Opcode field.
660 // - In AVX, there is a register operand in the VEX.vvvv field here -
661 // Operand 3 (optional) is an immediate.
663 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
664 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
666 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
667 "Unexpected number of operands for MRMDestMemFrm");
668 HANDLE_OPERAND(memory)
671 HANDLE_OPERAND(writemaskRegister)
674 // FIXME: In AVX, the register below becomes the one encoded
675 // in ModRMVEX and the one above the one in the VEX.VVVV field
676 HANDLE_OPERAND(vvvvRegister)
678 HANDLE_OPERAND(roRegister)
679 HANDLE_OPTIONAL(immediate)
681 case X86Local::MRMSrcReg:
682 // Operand 1 is a register operand in the Reg/Opcode field.
683 // Operand 2 is a register operand in the R/M field.
684 // - In AVX, there is a register operand in the VEX.vvvv field here -
685 // Operand 3 (optional) is an immediate.
686 // Operand 4 (optional) is an immediate.
688 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
689 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
690 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
692 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
693 "Unexpected number of operands for MRMSrcRegFrm");
695 HANDLE_OPERAND(roRegister)
698 HANDLE_OPERAND(writemaskRegister)
701 // FIXME: In AVX, the register below becomes the one encoded
702 // in ModRMVEX and the one above the one in the VEX.VVVV field
703 HANDLE_OPERAND(vvvvRegister)
706 HANDLE_OPERAND(immediate)
708 HANDLE_OPERAND(rmRegister)
710 if (HasVEX_4VOp3Prefix)
711 HANDLE_OPERAND(vvvvRegister)
713 if (!HasMemOp4Prefix)
714 HANDLE_OPTIONAL(immediate)
715 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
716 HANDLE_OPTIONAL(immediate)
718 case X86Local::MRMSrcMem:
719 // Operand 1 is a register operand in the Reg/Opcode field.
720 // Operand 2 is a memory operand (possibly SIB-extended)
721 // - In AVX, there is a register operand in the VEX.vvvv field here -
722 // Operand 3 (optional) is an immediate.
724 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
725 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
726 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
728 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
729 "Unexpected number of operands for MRMSrcMemFrm");
731 HANDLE_OPERAND(roRegister)
734 HANDLE_OPERAND(writemaskRegister)
737 // FIXME: In AVX, the register below becomes the one encoded
738 // in ModRMVEX and the one above the one in the VEX.VVVV field
739 HANDLE_OPERAND(vvvvRegister)
742 HANDLE_OPERAND(immediate)
744 HANDLE_OPERAND(memory)
746 if (HasVEX_4VOp3Prefix)
747 HANDLE_OPERAND(vvvvRegister)
749 if (!HasMemOp4Prefix)
750 HANDLE_OPTIONAL(immediate)
751 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
753 case X86Local::MRM0r:
754 case X86Local::MRM1r:
755 case X86Local::MRM2r:
756 case X86Local::MRM3r:
757 case X86Local::MRM4r:
758 case X86Local::MRM5r:
759 case X86Local::MRM6r:
760 case X86Local::MRM7r:
762 // Operand 1 is a register operand in the R/M field.
763 // Operand 2 (optional) is an immediate or relocation.
764 // Operand 3 (optional) is an immediate.
765 unsigned kOp = (HasEVEX_K) ? 1:0;
766 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
767 if (numPhysicalOperands > 3 + kOp + Op4v)
768 llvm_unreachable("Unexpected number of operands for MRMnr");
771 HANDLE_OPERAND(vvvvRegister)
774 HANDLE_OPERAND(writemaskRegister)
775 HANDLE_OPTIONAL(rmRegister)
776 HANDLE_OPTIONAL(relocation)
777 HANDLE_OPTIONAL(immediate)
779 case X86Local::MRM0m:
780 case X86Local::MRM1m:
781 case X86Local::MRM2m:
782 case X86Local::MRM3m:
783 case X86Local::MRM4m:
784 case X86Local::MRM5m:
785 case X86Local::MRM6m:
786 case X86Local::MRM7m:
788 // Operand 1 is a memory operand (possibly SIB-extended)
789 // Operand 2 (optional) is an immediate or relocation.
790 unsigned kOp = (HasEVEX_K) ? 1:0;
791 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
792 if (numPhysicalOperands < 1 + kOp + Op4v ||
793 numPhysicalOperands > 2 + kOp + Op4v)
794 llvm_unreachable("Unexpected number of operands for MRMnm");
797 HANDLE_OPERAND(vvvvRegister)
799 HANDLE_OPERAND(writemaskRegister)
800 HANDLE_OPERAND(memory)
801 HANDLE_OPTIONAL(relocation)
803 case X86Local::RawFrmImm8:
804 // operand 1 is a 16-bit immediate
805 // operand 2 is an 8-bit immediate
806 assert(numPhysicalOperands == 2 &&
807 "Unexpected number of operands for X86Local::RawFrmImm8");
808 HANDLE_OPERAND(immediate)
809 HANDLE_OPERAND(immediate)
811 case X86Local::RawFrmImm16:
812 // operand 1 is a 16-bit immediate
813 // operand 2 is a 16-bit immediate
814 HANDLE_OPERAND(immediate)
815 HANDLE_OPERAND(immediate)
817 case X86Local::MRM_F8:
818 if (Opcode == 0xc6) {
819 assert(numPhysicalOperands == 1 &&
820 "Unexpected number of operands for X86Local::MRM_F8");
821 HANDLE_OPERAND(immediate)
822 } else if (Opcode == 0xc7) {
823 assert(numPhysicalOperands == 1 &&
824 "Unexpected number of operands for X86Local::MRM_F8");
825 HANDLE_OPERAND(relocation)
828 case X86Local::MRMInitReg:
833 #undef HANDLE_OPERAND
834 #undef HANDLE_OPTIONAL
837 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
838 // Special cases where the LLVM tables are not complete
840 #define MAP(from, to) \
841 case X86Local::MRM_##from: \
842 filter = new ExactFilter(0x##from); \
845 OpcodeType opcodeType = (OpcodeType)-1;
847 ModRMFilter* filter = NULL;
848 uint8_t opcodeToSet = 0;
851 default: llvm_unreachable("Invalid prefix!");
852 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
856 opcodeType = TWOBYTE;
860 if (needsModRMForDecode(Form))
861 filter = new ModFilter(isRegFormat(Form));
863 filter = new DumbFilter();
865 #define EXTENSION_TABLE(n) case 0x##n:
866 TWO_BYTE_EXTENSION_TABLES
867 #undef EXTENSION_TABLE
870 llvm_unreachable("Unhandled two-byte extended opcode");
871 case X86Local::MRM0r:
872 case X86Local::MRM1r:
873 case X86Local::MRM2r:
874 case X86Local::MRM3r:
875 case X86Local::MRM4r:
876 case X86Local::MRM5r:
877 case X86Local::MRM6r:
878 case X86Local::MRM7r:
879 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
881 case X86Local::MRM0m:
882 case X86Local::MRM1m:
883 case X86Local::MRM2m:
884 case X86Local::MRM3m:
885 case X86Local::MRM4m:
886 case X86Local::MRM5m:
887 case X86Local::MRM6m:
888 case X86Local::MRM7m:
889 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
895 opcodeToSet = Opcode;
900 opcodeType = THREEBYTE_38;
903 if (needsModRMForDecode(Form))
904 filter = new ModFilter(isRegFormat(Form));
906 filter = new DumbFilter();
908 #define EXTENSION_TABLE(n) case 0x##n:
909 THREE_BYTE_38_EXTENSION_TABLES
910 #undef EXTENSION_TABLE
913 llvm_unreachable("Unhandled two-byte extended opcode");
914 case X86Local::MRM0r:
915 case X86Local::MRM1r:
916 case X86Local::MRM2r:
917 case X86Local::MRM3r:
918 case X86Local::MRM4r:
919 case X86Local::MRM5r:
920 case X86Local::MRM6r:
921 case X86Local::MRM7r:
922 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
924 case X86Local::MRM0m:
925 case X86Local::MRM1m:
926 case X86Local::MRM2m:
927 case X86Local::MRM3m:
928 case X86Local::MRM4m:
929 case X86Local::MRM5m:
930 case X86Local::MRM6m:
931 case X86Local::MRM7m:
932 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
938 opcodeToSet = Opcode;
942 opcodeType = THREEBYTE_3A;
943 if (needsModRMForDecode(Form))
944 filter = new ModFilter(isRegFormat(Form));
946 filter = new DumbFilter();
947 opcodeToSet = Opcode;
950 opcodeType = THREEBYTE_A6;
951 if (needsModRMForDecode(Form))
952 filter = new ModFilter(isRegFormat(Form));
954 filter = new DumbFilter();
955 opcodeToSet = Opcode;
958 opcodeType = THREEBYTE_A7;
959 if (needsModRMForDecode(Form))
960 filter = new ModFilter(isRegFormat(Form));
962 filter = new DumbFilter();
963 opcodeToSet = Opcode;
966 opcodeType = XOP8_MAP;
967 if (needsModRMForDecode(Form))
968 filter = new ModFilter(isRegFormat(Form));
970 filter = new DumbFilter();
971 opcodeToSet = Opcode;
974 opcodeType = XOP9_MAP;
977 if (needsModRMForDecode(Form))
978 filter = new ModFilter(isRegFormat(Form));
980 filter = new DumbFilter();
982 #define EXTENSION_TABLE(n) case 0x##n:
983 XOP9_MAP_EXTENSION_TABLES
984 #undef EXTENSION_TABLE
987 llvm_unreachable("Unhandled XOP9 extended opcode");
988 case X86Local::MRM0r:
989 case X86Local::MRM1r:
990 case X86Local::MRM2r:
991 case X86Local::MRM3r:
992 case X86Local::MRM4r:
993 case X86Local::MRM5r:
994 case X86Local::MRM6r:
995 case X86Local::MRM7r:
996 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
998 case X86Local::MRM0m:
999 case X86Local::MRM1m:
1000 case X86Local::MRM2m:
1001 case X86Local::MRM3m:
1002 case X86Local::MRM4m:
1003 case X86Local::MRM5m:
1004 case X86Local::MRM6m:
1005 case X86Local::MRM7m:
1006 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1011 } // switch (Opcode)
1012 opcodeToSet = Opcode;
1014 case X86Local::XOPA:
1015 opcodeType = XOPA_MAP;
1016 if (needsModRMForDecode(Form))
1017 filter = new ModFilter(isRegFormat(Form));
1019 filter = new DumbFilter();
1020 opcodeToSet = Opcode;
1030 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1031 assert(Form == X86Local::RawFrm);
1032 opcodeType = ONEBYTE;
1033 filter = new ExactFilter(Opcode);
1034 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1038 opcodeType = ONEBYTE;
1040 #define EXTENSION_TABLE(n) case 0x##n:
1041 ONE_BYTE_EXTENSION_TABLES
1042 #undef EXTENSION_TABLE
1045 llvm_unreachable("Fell through the cracks of a single-byte "
1047 case X86Local::MRM0r:
1048 case X86Local::MRM1r:
1049 case X86Local::MRM2r:
1050 case X86Local::MRM3r:
1051 case X86Local::MRM4r:
1052 case X86Local::MRM5r:
1053 case X86Local::MRM6r:
1054 case X86Local::MRM7r:
1055 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1057 case X86Local::MRM0m:
1058 case X86Local::MRM1m:
1059 case X86Local::MRM2m:
1060 case X86Local::MRM3m:
1061 case X86Local::MRM4m:
1062 case X86Local::MRM5m:
1063 case X86Local::MRM6m:
1064 case X86Local::MRM7m:
1065 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1080 llvm_unreachable("Unhandled escape opcode form");
1081 case X86Local::MRM0r:
1082 case X86Local::MRM1r:
1083 case X86Local::MRM2r:
1084 case X86Local::MRM3r:
1085 case X86Local::MRM4r:
1086 case X86Local::MRM5r:
1087 case X86Local::MRM6r:
1088 case X86Local::MRM7r:
1089 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1091 case X86Local::MRM0m:
1092 case X86Local::MRM1m:
1093 case X86Local::MRM2m:
1094 case X86Local::MRM3m:
1095 case X86Local::MRM4m:
1096 case X86Local::MRM5m:
1097 case X86Local::MRM6m:
1098 case X86Local::MRM7m:
1099 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1104 if (needsModRMForDecode(Form))
1105 filter = new ModFilter(isRegFormat(Form));
1107 filter = new DumbFilter();
1109 } // switch (Opcode)
1110 opcodeToSet = Opcode;
1111 } // switch (Prefix)
1113 assert(opcodeType != (OpcodeType)-1 &&
1114 "Opcode type not set");
1115 assert(filter && "Filter not set");
1117 if (Form == X86Local::AddRegFrm) {
1118 assert(((opcodeToSet & 7) == 0) &&
1119 "ADDREG_FRM opcode not aligned");
1121 uint8_t currentOpcode;
1123 for (currentOpcode = opcodeToSet;
1124 currentOpcode < opcodeToSet + 8;
1126 tables.setTableFields(opcodeType,
1130 UID, Is32Bit, IgnoresVEX_L);
1132 tables.setTableFields(opcodeType,
1136 UID, Is32Bit, IgnoresVEX_L);
1144 #define TYPE(str, type) if (s == str) return type;
1145 OperandType RecognizableInstr::typeFromString(const std::string &s,
1147 bool hasREX_WPrefix,
1148 bool hasOpSizePrefix) {
1150 // For SSE instructions, we ignore the OpSize prefix and force operand
1152 TYPE("GR16", TYPE_R16)
1153 TYPE("GR32", TYPE_R32)
1154 TYPE("GR64", TYPE_R64)
1156 if(hasREX_WPrefix) {
1157 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1159 TYPE("GR32", TYPE_R32)
1161 if(!hasOpSizePrefix) {
1162 // For instructions without an OpSize prefix, a declared 16-bit register or
1163 // immediate encoding is special.
1164 TYPE("GR16", TYPE_R16)
1165 TYPE("i16imm", TYPE_IMM16)
1167 TYPE("i16mem", TYPE_Mv)
1168 TYPE("i16imm", TYPE_IMMv)
1169 TYPE("i16i8imm", TYPE_IMMv)
1170 TYPE("GR16", TYPE_Rv)
1171 TYPE("i32mem", TYPE_Mv)
1172 TYPE("i32imm", TYPE_IMMv)
1173 TYPE("i32i8imm", TYPE_IMM32)
1174 TYPE("u32u8imm", TYPE_IMM32)
1175 TYPE("GR32", TYPE_Rv)
1176 TYPE("GR32orGR64", TYPE_R32)
1177 TYPE("i64mem", TYPE_Mv)
1178 TYPE("i64i32imm", TYPE_IMM64)
1179 TYPE("i64i8imm", TYPE_IMM64)
1180 TYPE("GR64", TYPE_R64)
1181 TYPE("i8mem", TYPE_M8)
1182 TYPE("i8imm", TYPE_IMM8)
1183 TYPE("GR8", TYPE_R8)
1184 TYPE("VR128", TYPE_XMM128)
1185 TYPE("VR128X", TYPE_XMM128)
1186 TYPE("f128mem", TYPE_M128)
1187 TYPE("f256mem", TYPE_M256)
1188 TYPE("f512mem", TYPE_M512)
1189 TYPE("FR64", TYPE_XMM64)
1190 TYPE("FR64X", TYPE_XMM64)
1191 TYPE("f64mem", TYPE_M64FP)
1192 TYPE("sdmem", TYPE_M64FP)
1193 TYPE("FR32", TYPE_XMM32)
1194 TYPE("FR32X", TYPE_XMM32)
1195 TYPE("f32mem", TYPE_M32FP)
1196 TYPE("ssmem", TYPE_M32FP)
1197 TYPE("RST", TYPE_ST)
1198 TYPE("i128mem", TYPE_M128)
1199 TYPE("i256mem", TYPE_M256)
1200 TYPE("i512mem", TYPE_M512)
1201 TYPE("i64i32imm_pcrel", TYPE_REL64)
1202 TYPE("i16imm_pcrel", TYPE_REL16)
1203 TYPE("i32imm_pcrel", TYPE_REL32)
1204 TYPE("SSECC", TYPE_IMM3)
1205 TYPE("AVXCC", TYPE_IMM5)
1206 TYPE("AVX512RC", TYPE_IMM32)
1207 TYPE("brtarget", TYPE_RELv)
1208 TYPE("uncondbrtarget", TYPE_RELv)
1209 TYPE("brtarget8", TYPE_REL8)
1210 TYPE("f80mem", TYPE_M80FP)
1211 TYPE("lea32mem", TYPE_LEA)
1212 TYPE("lea64_32mem", TYPE_LEA)
1213 TYPE("lea64mem", TYPE_LEA)
1214 TYPE("VR64", TYPE_MM64)
1215 TYPE("i64imm", TYPE_IMMv)
1216 TYPE("opaque32mem", TYPE_M1616)
1217 TYPE("opaque48mem", TYPE_M1632)
1218 TYPE("opaque80mem", TYPE_M1664)
1219 TYPE("opaque512mem", TYPE_M512)
1220 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1221 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1222 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1223 TYPE("offset8", TYPE_MOFFS8)
1224 TYPE("offset16", TYPE_MOFFS16)
1225 TYPE("offset32", TYPE_MOFFS32)
1226 TYPE("offset64", TYPE_MOFFS64)
1227 TYPE("VR256", TYPE_XMM256)
1228 TYPE("VR256X", TYPE_XMM256)
1229 TYPE("VR512", TYPE_XMM512)
1230 TYPE("VK1", TYPE_VK1)
1231 TYPE("VK1WM", TYPE_VK1)
1232 TYPE("VK8", TYPE_VK8)
1233 TYPE("VK8WM", TYPE_VK8)
1234 TYPE("VK16", TYPE_VK16)
1235 TYPE("VK16WM", TYPE_VK16)
1236 TYPE("GR16_NOAX", TYPE_Rv)
1237 TYPE("GR32_NOAX", TYPE_Rv)
1238 TYPE("GR64_NOAX", TYPE_R64)
1239 TYPE("vx32mem", TYPE_M32)
1240 TYPE("vy32mem", TYPE_M32)
1241 TYPE("vz32mem", TYPE_M32)
1242 TYPE("vx64mem", TYPE_M64)
1243 TYPE("vy64mem", TYPE_M64)
1244 TYPE("vy64xmem", TYPE_M64)
1245 TYPE("vz64mem", TYPE_M64)
1246 errs() << "Unhandled type string " << s << "\n";
1247 llvm_unreachable("Unhandled type string");
1251 #define ENCODING(str, encoding) if (s == str) return encoding;
1252 OperandEncoding RecognizableInstr::immediateEncodingFromString
1253 (const std::string &s,
1254 bool hasOpSizePrefix) {
1255 if(!hasOpSizePrefix) {
1256 // For instructions without an OpSize prefix, a declared 16-bit register or
1257 // immediate encoding is special.
1258 ENCODING("i16imm", ENCODING_IW)
1260 ENCODING("i32i8imm", ENCODING_IB)
1261 ENCODING("u32u8imm", ENCODING_IB)
1262 ENCODING("SSECC", ENCODING_IB)
1263 ENCODING("AVXCC", ENCODING_IB)
1264 ENCODING("AVX512RC", ENCODING_IB)
1265 ENCODING("i16imm", ENCODING_Iv)
1266 ENCODING("i16i8imm", ENCODING_IB)
1267 ENCODING("i32imm", ENCODING_Iv)
1268 ENCODING("i64i32imm", ENCODING_ID)
1269 ENCODING("i64i8imm", ENCODING_IB)
1270 ENCODING("i8imm", ENCODING_IB)
1271 // This is not a typo. Instructions like BLENDVPD put
1272 // register IDs in 8-bit immediates nowadays.
1273 ENCODING("FR32", ENCODING_IB)
1274 ENCODING("FR64", ENCODING_IB)
1275 ENCODING("VR128", ENCODING_IB)
1276 ENCODING("VR256", ENCODING_IB)
1277 ENCODING("FR32X", ENCODING_IB)
1278 ENCODING("FR64X", ENCODING_IB)
1279 ENCODING("VR128X", ENCODING_IB)
1280 ENCODING("VR256X", ENCODING_IB)
1281 ENCODING("VR512", ENCODING_IB)
1282 errs() << "Unhandled immediate encoding " << s << "\n";
1283 llvm_unreachable("Unhandled immediate encoding");
1286 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1287 (const std::string &s,
1288 bool hasOpSizePrefix) {
1289 ENCODING("RST", ENCODING_FP)
1290 ENCODING("GR16", ENCODING_RM)
1291 ENCODING("GR32", ENCODING_RM)
1292 ENCODING("GR32orGR64", ENCODING_RM)
1293 ENCODING("GR64", ENCODING_RM)
1294 ENCODING("GR8", ENCODING_RM)
1295 ENCODING("VR128", ENCODING_RM)
1296 ENCODING("VR128X", ENCODING_RM)
1297 ENCODING("FR64", ENCODING_RM)
1298 ENCODING("FR32", ENCODING_RM)
1299 ENCODING("FR64X", ENCODING_RM)
1300 ENCODING("FR32X", ENCODING_RM)
1301 ENCODING("VR64", ENCODING_RM)
1302 ENCODING("VR256", ENCODING_RM)
1303 ENCODING("VR256X", ENCODING_RM)
1304 ENCODING("VR512", ENCODING_RM)
1305 ENCODING("VK1", ENCODING_RM)
1306 ENCODING("VK8", ENCODING_RM)
1307 ENCODING("VK16", ENCODING_RM)
1308 errs() << "Unhandled R/M register encoding " << s << "\n";
1309 llvm_unreachable("Unhandled R/M register encoding");
1312 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1313 (const std::string &s,
1314 bool hasOpSizePrefix) {
1315 ENCODING("GR16", ENCODING_REG)
1316 ENCODING("GR32", ENCODING_REG)
1317 ENCODING("GR32orGR64", ENCODING_REG)
1318 ENCODING("GR64", ENCODING_REG)
1319 ENCODING("GR8", ENCODING_REG)
1320 ENCODING("VR128", ENCODING_REG)
1321 ENCODING("FR64", ENCODING_REG)
1322 ENCODING("FR32", ENCODING_REG)
1323 ENCODING("VR64", ENCODING_REG)
1324 ENCODING("SEGMENT_REG", ENCODING_REG)
1325 ENCODING("DEBUG_REG", ENCODING_REG)
1326 ENCODING("CONTROL_REG", ENCODING_REG)
1327 ENCODING("VR256", ENCODING_REG)
1328 ENCODING("VR256X", ENCODING_REG)
1329 ENCODING("VR128X", ENCODING_REG)
1330 ENCODING("FR64X", ENCODING_REG)
1331 ENCODING("FR32X", ENCODING_REG)
1332 ENCODING("VR512", ENCODING_REG)
1333 ENCODING("VK1", ENCODING_REG)
1334 ENCODING("VK8", ENCODING_REG)
1335 ENCODING("VK16", ENCODING_REG)
1336 ENCODING("VK1WM", ENCODING_REG)
1337 ENCODING("VK8WM", ENCODING_REG)
1338 ENCODING("VK16WM", ENCODING_REG)
1339 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1340 llvm_unreachable("Unhandled reg/opcode register encoding");
1343 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1344 (const std::string &s,
1345 bool hasOpSizePrefix) {
1346 ENCODING("GR32", ENCODING_VVVV)
1347 ENCODING("GR64", ENCODING_VVVV)
1348 ENCODING("FR32", ENCODING_VVVV)
1349 ENCODING("FR64", ENCODING_VVVV)
1350 ENCODING("VR128", ENCODING_VVVV)
1351 ENCODING("VR256", ENCODING_VVVV)
1352 ENCODING("FR32X", ENCODING_VVVV)
1353 ENCODING("FR64X", ENCODING_VVVV)
1354 ENCODING("VR128X", ENCODING_VVVV)
1355 ENCODING("VR256X", ENCODING_VVVV)
1356 ENCODING("VR512", ENCODING_VVVV)
1357 ENCODING("VK1", ENCODING_VVVV)
1358 ENCODING("VK8", ENCODING_VVVV)
1359 ENCODING("VK16", ENCODING_VVVV)
1360 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1361 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1364 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1365 (const std::string &s,
1366 bool hasOpSizePrefix) {
1367 ENCODING("VK1WM", ENCODING_WRITEMASK)
1368 ENCODING("VK8WM", ENCODING_WRITEMASK)
1369 ENCODING("VK16WM", ENCODING_WRITEMASK)
1370 errs() << "Unhandled mask register encoding " << s << "\n";
1371 llvm_unreachable("Unhandled mask register encoding");
1374 OperandEncoding RecognizableInstr::memoryEncodingFromString
1375 (const std::string &s,
1376 bool hasOpSizePrefix) {
1377 ENCODING("i16mem", ENCODING_RM)
1378 ENCODING("i32mem", ENCODING_RM)
1379 ENCODING("i64mem", ENCODING_RM)
1380 ENCODING("i8mem", ENCODING_RM)
1381 ENCODING("ssmem", ENCODING_RM)
1382 ENCODING("sdmem", ENCODING_RM)
1383 ENCODING("f128mem", ENCODING_RM)
1384 ENCODING("f256mem", ENCODING_RM)
1385 ENCODING("f512mem", ENCODING_RM)
1386 ENCODING("f64mem", ENCODING_RM)
1387 ENCODING("f32mem", ENCODING_RM)
1388 ENCODING("i128mem", ENCODING_RM)
1389 ENCODING("i256mem", ENCODING_RM)
1390 ENCODING("i512mem", ENCODING_RM)
1391 ENCODING("f80mem", ENCODING_RM)
1392 ENCODING("lea32mem", ENCODING_RM)
1393 ENCODING("lea64_32mem", ENCODING_RM)
1394 ENCODING("lea64mem", ENCODING_RM)
1395 ENCODING("opaque32mem", ENCODING_RM)
1396 ENCODING("opaque48mem", ENCODING_RM)
1397 ENCODING("opaque80mem", ENCODING_RM)
1398 ENCODING("opaque512mem", ENCODING_RM)
1399 ENCODING("vx32mem", ENCODING_RM)
1400 ENCODING("vy32mem", ENCODING_RM)
1401 ENCODING("vz32mem", ENCODING_RM)
1402 ENCODING("vx64mem", ENCODING_RM)
1403 ENCODING("vy64mem", ENCODING_RM)
1404 ENCODING("vy64xmem", ENCODING_RM)
1405 ENCODING("vz64mem", ENCODING_RM)
1406 errs() << "Unhandled memory encoding " << s << "\n";
1407 llvm_unreachable("Unhandled memory encoding");
1410 OperandEncoding RecognizableInstr::relocationEncodingFromString
1411 (const std::string &s,
1412 bool hasOpSizePrefix) {
1413 if(!hasOpSizePrefix) {
1414 // For instructions without an OpSize prefix, a declared 16-bit register or
1415 // immediate encoding is special.
1416 ENCODING("i16imm", ENCODING_IW)
1418 ENCODING("i16imm", ENCODING_Iv)
1419 ENCODING("i16i8imm", ENCODING_IB)
1420 ENCODING("i32imm", ENCODING_Iv)
1421 ENCODING("i32i8imm", ENCODING_IB)
1422 ENCODING("i64i32imm", ENCODING_ID)
1423 ENCODING("i64i8imm", ENCODING_IB)
1424 ENCODING("i8imm", ENCODING_IB)
1425 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1426 ENCODING("i16imm_pcrel", ENCODING_IW)
1427 ENCODING("i32imm_pcrel", ENCODING_ID)
1428 ENCODING("brtarget", ENCODING_Iv)
1429 ENCODING("brtarget8", ENCODING_IB)
1430 ENCODING("i64imm", ENCODING_IO)
1431 ENCODING("offset8", ENCODING_Ia)
1432 ENCODING("offset16", ENCODING_Ia)
1433 ENCODING("offset32", ENCODING_Ia)
1434 ENCODING("offset64", ENCODING_Ia)
1435 errs() << "Unhandled relocation encoding " << s << "\n";
1436 llvm_unreachable("Unhandled relocation encoding");
1439 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1440 (const std::string &s,
1441 bool hasOpSizePrefix) {
1442 ENCODING("GR32", ENCODING_Rv)
1443 ENCODING("GR64", ENCODING_RO)
1444 ENCODING("GR16", ENCODING_Rv)
1445 ENCODING("GR8", ENCODING_RB)
1446 ENCODING("GR16_NOAX", ENCODING_Rv)
1447 ENCODING("GR32_NOAX", ENCODING_Rv)
1448 ENCODING("GR64_NOAX", ENCODING_RO)
1449 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1450 llvm_unreachable("Unhandled opcode modifier encoding");