1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
135 #define THREE_BYTE_38_EXTENSION_TABLES \
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
233 SegOvr = byteFromRec(Rec, "SegOvrBits");
235 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
236 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
237 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
238 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
239 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
240 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
242 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
243 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
244 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
245 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
247 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
248 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
249 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
250 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
252 Name = Rec->getName();
253 AsmString = Rec->getValueAsString("AsmString");
255 Operands = &insn.Operands.OperandList;
257 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
258 (Name.find("CRC32") != Name.npos);
259 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
261 // Check for 64-bit inst which does not require REX
264 // FIXME: Is there some better way to check for In64BitMode?
265 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
266 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
267 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
268 Predicates[i]->getName().find("In32Bit") != Name.npos) {
272 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
277 // FIXME: These instructions aren't marked as 64-bit in any way
278 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
279 Rec->getName() == "REX64_PREFIX" ||
280 Rec->getName().find("MOV64") != Name.npos ||
281 Rec->getName().find("PUSH64") != Name.npos ||
282 Rec->getName().find("POP64") != Name.npos;
284 ShouldBeEmitted = true;
287 void RecognizableInstr::processInstr(DisassemblerTables &tables,
288 const CodeGenInstruction &insn,
291 // Ignore "asm parser only" instructions.
292 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
295 RecognizableInstr recogInstr(tables, insn, uid);
297 recogInstr.emitInstructionSpecifier();
299 if (recogInstr.shouldBeEmitted())
300 recogInstr.emitDecodePath(tables);
303 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
304 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
305 (HasEVEX_KZ ? n##_KZ : \
306 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
308 InstructionContext RecognizableInstr::insnContext() const {
309 InstructionContext insnContext;
312 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
313 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
314 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
317 if (HasVEX_LPrefix && HasVEX_WPrefix) {
319 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
320 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
321 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
322 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
323 Prefix == X86Local::TAXD)
324 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
326 insnContext = EVEX_KB(IC_EVEX_L_W);
327 } else if (HasVEX_LPrefix) {
330 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
331 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
332 insnContext = EVEX_KB(IC_EVEX_L_XS);
333 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
334 Prefix == X86Local::TAXD)
335 insnContext = EVEX_KB(IC_EVEX_L_XD);
337 insnContext = EVEX_KB(IC_EVEX_L);
339 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
342 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
343 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
344 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
345 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
346 Prefix == X86Local::TAXD)
347 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
349 insnContext = EVEX_KB(IC_EVEX_L2_W);
350 } else if (HasEVEX_L2Prefix) {
353 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
354 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
355 Prefix == X86Local::TAXD)
356 insnContext = EVEX_KB(IC_EVEX_L2_XD);
357 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
358 insnContext = EVEX_KB(IC_EVEX_L2_XS);
360 insnContext = EVEX_KB(IC_EVEX_L2);
362 else if (HasVEX_WPrefix) {
365 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
366 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
367 insnContext = EVEX_KB(IC_EVEX_W_XS);
368 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
369 Prefix == X86Local::TAXD)
370 insnContext = EVEX_KB(IC_EVEX_W_XD);
372 insnContext = EVEX_KB(IC_EVEX_W);
375 else if (HasOpSizePrefix)
376 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
377 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
378 Prefix == X86Local::TAXD)
379 insnContext = EVEX_KB(IC_EVEX_XD);
380 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
381 insnContext = EVEX_KB(IC_EVEX_XS);
383 insnContext = EVEX_KB(IC_EVEX);
385 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
386 if (HasVEX_LPrefix && HasVEX_WPrefix) {
388 insnContext = IC_VEX_L_W_OPSIZE;
389 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
390 insnContext = IC_VEX_L_W_XS;
391 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
392 Prefix == X86Local::TAXD)
393 insnContext = IC_VEX_L_W_XD;
395 insnContext = IC_VEX_L_W;
396 } else if (HasOpSizePrefix && HasVEX_LPrefix)
397 insnContext = IC_VEX_L_OPSIZE;
398 else if (HasOpSizePrefix && HasVEX_WPrefix)
399 insnContext = IC_VEX_W_OPSIZE;
400 else if (HasOpSizePrefix)
401 insnContext = IC_VEX_OPSIZE;
402 else if (HasVEX_LPrefix &&
403 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
404 insnContext = IC_VEX_L_XS;
405 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
406 Prefix == X86Local::T8XD ||
407 Prefix == X86Local::TAXD))
408 insnContext = IC_VEX_L_XD;
409 else if (HasVEX_WPrefix &&
410 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
411 insnContext = IC_VEX_W_XS;
412 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
413 Prefix == X86Local::T8XD ||
414 Prefix == X86Local::TAXD))
415 insnContext = IC_VEX_W_XD;
416 else if (HasVEX_WPrefix)
417 insnContext = IC_VEX_W;
418 else if (HasVEX_LPrefix)
419 insnContext = IC_VEX_L;
420 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
421 Prefix == X86Local::TAXD)
422 insnContext = IC_VEX_XD;
423 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
424 insnContext = IC_VEX_XS;
426 insnContext = IC_VEX;
427 } else if (Is64Bit || HasREX_WPrefix) {
428 if (HasREX_WPrefix && HasOpSizePrefix)
429 insnContext = IC_64BIT_REXW_OPSIZE;
430 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
431 Prefix == X86Local::T8XD ||
432 Prefix == X86Local::TAXD))
433 insnContext = IC_64BIT_XD_OPSIZE;
434 else if (HasOpSizePrefix &&
435 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
436 insnContext = IC_64BIT_XS_OPSIZE;
437 else if (HasOpSizePrefix)
438 insnContext = IC_64BIT_OPSIZE;
439 else if (HasAdSizePrefix)
440 insnContext = IC_64BIT_ADSIZE;
441 else if (HasREX_WPrefix &&
442 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
443 insnContext = IC_64BIT_REXW_XS;
444 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
445 Prefix == X86Local::T8XD ||
446 Prefix == X86Local::TAXD))
447 insnContext = IC_64BIT_REXW_XD;
448 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
449 Prefix == X86Local::TAXD)
450 insnContext = IC_64BIT_XD;
451 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
452 insnContext = IC_64BIT_XS;
453 else if (HasREX_WPrefix)
454 insnContext = IC_64BIT_REXW;
456 insnContext = IC_64BIT;
458 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
459 Prefix == X86Local::T8XD ||
460 Prefix == X86Local::TAXD))
461 insnContext = IC_XD_OPSIZE;
462 else if (HasOpSizePrefix &&
463 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
464 insnContext = IC_XS_OPSIZE;
465 else if (HasOpSizePrefix)
466 insnContext = IC_OPSIZE;
467 else if (HasAdSizePrefix)
468 insnContext = IC_ADSIZE;
469 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
470 Prefix == X86Local::TAXD)
472 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
473 Prefix == X86Local::REP)
482 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
487 // Filter out intrinsics
489 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
491 if (Form == X86Local::Pseudo ||
492 (IsCodeGenOnly && Name.find("_REV") == Name.npos &&
493 Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos))
494 return FILTER_STRONG;
497 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
498 // printed as a separate "instruction".
500 // Filter out instructions with segment override prefixes.
501 // They're too messy to handle now and we'll special case them if needed.
504 return FILTER_STRONG;
512 // Filter out instructions with a LOCK prefix;
513 // prefer forms that do not have the prefix
517 // Filter out alternate forms of AVX instructions
518 if (Name.find("_alt") != Name.npos ||
519 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
520 Name.find("_64mr") != Name.npos ||
521 Name.find("rr64") != Name.npos)
526 if (Name == "PUSH64i16" ||
527 Name == "MOVPQI2QImr" ||
528 Name == "VMOVPQI2QImr" ||
529 Name == "VMASKMOVDQU64")
532 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
533 // For now, just prefer the REP versions.
534 if (Name == "XACQUIRE_PREFIX" ||
535 Name == "XRELEASE_PREFIX")
538 return FILTER_NORMAL;
541 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
542 unsigned &physicalOperandIndex,
543 unsigned &numPhysicalOperands,
544 const unsigned *operandMapping,
545 OperandEncoding (*encodingFromString)
547 bool hasOpSizePrefix)) {
549 if (physicalOperandIndex >= numPhysicalOperands)
552 assert(physicalOperandIndex < numPhysicalOperands);
555 while (operandMapping[operandIndex] != operandIndex) {
556 Spec->operands[operandIndex].encoding = ENCODING_DUP;
557 Spec->operands[operandIndex].type =
558 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
562 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
564 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
566 Spec->operands[operandIndex].type = typeFromString(typeName,
572 ++physicalOperandIndex;
575 void RecognizableInstr::emitInstructionSpecifier() {
578 if (!ShouldBeEmitted)
583 Spec->filtered = true;
586 ShouldBeEmitted = false;
592 Spec->insnContext = insnContext();
594 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
596 unsigned numOperands = OperandList.size();
597 unsigned numPhysicalOperands = 0;
599 // operandMapping maps from operands in OperandList to their originals.
600 // If operandMapping[i] != i, then the entry is a duplicate.
601 unsigned operandMapping[X86_MAX_OPERANDS];
602 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
604 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
605 if (OperandList[operandIndex].Constraints.size()) {
606 const CGIOperandList::ConstraintInfo &Constraint =
607 OperandList[operandIndex].Constraints[0];
608 if (Constraint.isTied()) {
609 operandMapping[operandIndex] = operandIndex;
610 operandMapping[Constraint.getTiedOperand()] = operandIndex;
612 ++numPhysicalOperands;
613 operandMapping[operandIndex] = operandIndex;
616 ++numPhysicalOperands;
617 operandMapping[operandIndex] = operandIndex;
621 #define HANDLE_OPERAND(class) \
622 handleOperand(false, \
624 physicalOperandIndex, \
625 numPhysicalOperands, \
627 class##EncodingFromString);
629 #define HANDLE_OPTIONAL(class) \
630 handleOperand(true, \
632 physicalOperandIndex, \
633 numPhysicalOperands, \
635 class##EncodingFromString);
637 // operandIndex should always be < numOperands
638 unsigned operandIndex = 0;
639 // physicalOperandIndex should always be < numPhysicalOperands
640 unsigned physicalOperandIndex = 0;
643 case X86Local::RawFrm:
644 // Operand 1 (optional) is an address or immediate.
645 // Operand 2 (optional) is an immediate.
646 assert(numPhysicalOperands <= 2 &&
647 "Unexpected number of operands for RawFrm");
648 HANDLE_OPTIONAL(relocation)
649 HANDLE_OPTIONAL(immediate)
651 case X86Local::AddRegFrm:
652 // Operand 1 is added to the opcode.
653 // Operand 2 (optional) is an address.
654 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
655 "Unexpected number of operands for AddRegFrm");
656 HANDLE_OPERAND(opcodeModifier)
657 HANDLE_OPTIONAL(relocation)
659 case X86Local::MRMDestReg:
660 // Operand 1 is a register operand in the R/M field.
661 // Operand 2 is a register operand in the Reg/Opcode field.
662 // - In AVX, there is a register operand in the VEX.vvvv field here -
663 // Operand 3 (optional) is an immediate.
665 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
666 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
668 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
669 "Unexpected number of operands for MRMDestRegFrm");
671 HANDLE_OPERAND(rmRegister)
674 // FIXME: In AVX, the register below becomes the one encoded
675 // in ModRMVEX and the one above the one in the VEX.VVVV field
676 HANDLE_OPERAND(vvvvRegister)
678 HANDLE_OPERAND(roRegister)
679 HANDLE_OPTIONAL(immediate)
681 case X86Local::MRMDestMem:
682 // Operand 1 is a memory operand (possibly SIB-extended)
683 // Operand 2 is a register operand in the Reg/Opcode field.
684 // - In AVX, there is a register operand in the VEX.vvvv field here -
685 // Operand 3 (optional) is an immediate.
687 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
688 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
690 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
691 "Unexpected number of operands for MRMDestMemFrm");
692 HANDLE_OPERAND(memory)
695 HANDLE_OPERAND(writemaskRegister)
698 // FIXME: In AVX, the register below becomes the one encoded
699 // in ModRMVEX and the one above the one in the VEX.VVVV field
700 HANDLE_OPERAND(vvvvRegister)
702 HANDLE_OPERAND(roRegister)
703 HANDLE_OPTIONAL(immediate)
705 case X86Local::MRMSrcReg:
706 // Operand 1 is a register operand in the Reg/Opcode field.
707 // Operand 2 is a register operand in the R/M field.
708 // - In AVX, there is a register operand in the VEX.vvvv field here -
709 // Operand 3 (optional) is an immediate.
710 // Operand 4 (optional) is an immediate.
712 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
713 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
714 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
716 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
717 "Unexpected number of operands for MRMSrcRegFrm");
719 HANDLE_OPERAND(roRegister)
722 HANDLE_OPERAND(writemaskRegister)
725 // FIXME: In AVX, the register below becomes the one encoded
726 // in ModRMVEX and the one above the one in the VEX.VVVV field
727 HANDLE_OPERAND(vvvvRegister)
730 HANDLE_OPERAND(immediate)
732 HANDLE_OPERAND(rmRegister)
734 if (HasVEX_4VOp3Prefix)
735 HANDLE_OPERAND(vvvvRegister)
737 if (!HasMemOp4Prefix)
738 HANDLE_OPTIONAL(immediate)
739 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
740 HANDLE_OPTIONAL(immediate)
742 case X86Local::MRMSrcMem:
743 // Operand 1 is a register operand in the Reg/Opcode field.
744 // Operand 2 is a memory operand (possibly SIB-extended)
745 // - In AVX, there is a register operand in the VEX.vvvv field here -
746 // Operand 3 (optional) is an immediate.
748 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
749 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
750 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
752 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
753 "Unexpected number of operands for MRMSrcMemFrm");
755 HANDLE_OPERAND(roRegister)
758 HANDLE_OPERAND(writemaskRegister)
761 // FIXME: In AVX, the register below becomes the one encoded
762 // in ModRMVEX and the one above the one in the VEX.VVVV field
763 HANDLE_OPERAND(vvvvRegister)
766 HANDLE_OPERAND(immediate)
768 HANDLE_OPERAND(memory)
770 if (HasVEX_4VOp3Prefix)
771 HANDLE_OPERAND(vvvvRegister)
773 if (!HasMemOp4Prefix)
774 HANDLE_OPTIONAL(immediate)
775 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
777 case X86Local::MRM0r:
778 case X86Local::MRM1r:
779 case X86Local::MRM2r:
780 case X86Local::MRM3r:
781 case X86Local::MRM4r:
782 case X86Local::MRM5r:
783 case X86Local::MRM6r:
784 case X86Local::MRM7r:
786 // Operand 1 is a register operand in the R/M field.
787 // Operand 2 (optional) is an immediate or relocation.
788 // Operand 3 (optional) is an immediate.
789 unsigned kOp = (HasEVEX_K) ? 1:0;
790 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
791 if (numPhysicalOperands > 3 + kOp + Op4v)
792 llvm_unreachable("Unexpected number of operands for MRMnr");
795 HANDLE_OPERAND(vvvvRegister)
798 HANDLE_OPERAND(writemaskRegister)
799 HANDLE_OPTIONAL(rmRegister)
800 HANDLE_OPTIONAL(relocation)
801 HANDLE_OPTIONAL(immediate)
803 case X86Local::MRM0m:
804 case X86Local::MRM1m:
805 case X86Local::MRM2m:
806 case X86Local::MRM3m:
807 case X86Local::MRM4m:
808 case X86Local::MRM5m:
809 case X86Local::MRM6m:
810 case X86Local::MRM7m:
812 // Operand 1 is a memory operand (possibly SIB-extended)
813 // Operand 2 (optional) is an immediate or relocation.
814 unsigned kOp = (HasEVEX_K) ? 1:0;
815 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
816 if (numPhysicalOperands < 1 + kOp + Op4v ||
817 numPhysicalOperands > 2 + kOp + Op4v)
818 llvm_unreachable("Unexpected number of operands for MRMnm");
821 HANDLE_OPERAND(vvvvRegister)
823 HANDLE_OPERAND(writemaskRegister)
824 HANDLE_OPERAND(memory)
825 HANDLE_OPTIONAL(relocation)
827 case X86Local::RawFrmImm8:
828 // operand 1 is a 16-bit immediate
829 // operand 2 is an 8-bit immediate
830 assert(numPhysicalOperands == 2 &&
831 "Unexpected number of operands for X86Local::RawFrmImm8");
832 HANDLE_OPERAND(immediate)
833 HANDLE_OPERAND(immediate)
835 case X86Local::RawFrmImm16:
836 // operand 1 is a 16-bit immediate
837 // operand 2 is a 16-bit immediate
838 HANDLE_OPERAND(immediate)
839 HANDLE_OPERAND(immediate)
841 case X86Local::MRM_F8:
842 if (Opcode == 0xc6) {
843 assert(numPhysicalOperands == 1 &&
844 "Unexpected number of operands for X86Local::MRM_F8");
845 HANDLE_OPERAND(immediate)
846 } else if (Opcode == 0xc7) {
847 assert(numPhysicalOperands == 1 &&
848 "Unexpected number of operands for X86Local::MRM_F8");
849 HANDLE_OPERAND(relocation)
852 case X86Local::MRMInitReg:
857 #undef HANDLE_OPERAND
858 #undef HANDLE_OPTIONAL
861 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
862 // Special cases where the LLVM tables are not complete
864 #define MAP(from, to) \
865 case X86Local::MRM_##from: \
866 filter = new ExactFilter(0x##from); \
869 OpcodeType opcodeType = (OpcodeType)-1;
871 ModRMFilter* filter = NULL;
872 uint8_t opcodeToSet = 0;
875 default: llvm_unreachable("Invalid prefix!");
876 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
880 opcodeType = TWOBYTE;
884 if (needsModRMForDecode(Form))
885 filter = new ModFilter(isRegFormat(Form));
887 filter = new DumbFilter();
889 #define EXTENSION_TABLE(n) case 0x##n:
890 TWO_BYTE_EXTENSION_TABLES
891 #undef EXTENSION_TABLE
894 llvm_unreachable("Unhandled two-byte extended opcode");
895 case X86Local::MRM0r:
896 case X86Local::MRM1r:
897 case X86Local::MRM2r:
898 case X86Local::MRM3r:
899 case X86Local::MRM4r:
900 case X86Local::MRM5r:
901 case X86Local::MRM6r:
902 case X86Local::MRM7r:
903 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
905 case X86Local::MRM0m:
906 case X86Local::MRM1m:
907 case X86Local::MRM2m:
908 case X86Local::MRM3m:
909 case X86Local::MRM4m:
910 case X86Local::MRM5m:
911 case X86Local::MRM6m:
912 case X86Local::MRM7m:
913 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
919 opcodeToSet = Opcode;
924 opcodeType = THREEBYTE_38;
927 if (needsModRMForDecode(Form))
928 filter = new ModFilter(isRegFormat(Form));
930 filter = new DumbFilter();
932 #define EXTENSION_TABLE(n) case 0x##n:
933 THREE_BYTE_38_EXTENSION_TABLES
934 #undef EXTENSION_TABLE
937 llvm_unreachable("Unhandled two-byte extended opcode");
938 case X86Local::MRM0r:
939 case X86Local::MRM1r:
940 case X86Local::MRM2r:
941 case X86Local::MRM3r:
942 case X86Local::MRM4r:
943 case X86Local::MRM5r:
944 case X86Local::MRM6r:
945 case X86Local::MRM7r:
946 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
948 case X86Local::MRM0m:
949 case X86Local::MRM1m:
950 case X86Local::MRM2m:
951 case X86Local::MRM3m:
952 case X86Local::MRM4m:
953 case X86Local::MRM5m:
954 case X86Local::MRM6m:
955 case X86Local::MRM7m:
956 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
962 opcodeToSet = Opcode;
966 opcodeType = THREEBYTE_3A;
967 if (needsModRMForDecode(Form))
968 filter = new ModFilter(isRegFormat(Form));
970 filter = new DumbFilter();
971 opcodeToSet = Opcode;
974 opcodeType = THREEBYTE_A6;
975 if (needsModRMForDecode(Form))
976 filter = new ModFilter(isRegFormat(Form));
978 filter = new DumbFilter();
979 opcodeToSet = Opcode;
982 opcodeType = THREEBYTE_A7;
983 if (needsModRMForDecode(Form))
984 filter = new ModFilter(isRegFormat(Form));
986 filter = new DumbFilter();
987 opcodeToSet = Opcode;
990 opcodeType = XOP8_MAP;
991 if (needsModRMForDecode(Form))
992 filter = new ModFilter(isRegFormat(Form));
994 filter = new DumbFilter();
995 opcodeToSet = Opcode;
998 opcodeType = XOP9_MAP;
1001 if (needsModRMForDecode(Form))
1002 filter = new ModFilter(isRegFormat(Form));
1004 filter = new DumbFilter();
1006 #define EXTENSION_TABLE(n) case 0x##n:
1007 XOP9_MAP_EXTENSION_TABLES
1008 #undef EXTENSION_TABLE
1011 llvm_unreachable("Unhandled XOP9 extended opcode");
1012 case X86Local::MRM0r:
1013 case X86Local::MRM1r:
1014 case X86Local::MRM2r:
1015 case X86Local::MRM3r:
1016 case X86Local::MRM4r:
1017 case X86Local::MRM5r:
1018 case X86Local::MRM6r:
1019 case X86Local::MRM7r:
1020 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1022 case X86Local::MRM0m:
1023 case X86Local::MRM1m:
1024 case X86Local::MRM2m:
1025 case X86Local::MRM3m:
1026 case X86Local::MRM4m:
1027 case X86Local::MRM5m:
1028 case X86Local::MRM6m:
1029 case X86Local::MRM7m:
1030 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1035 } // switch (Opcode)
1036 opcodeToSet = Opcode;
1038 case X86Local::XOPA:
1039 opcodeType = XOPA_MAP;
1040 if (needsModRMForDecode(Form))
1041 filter = new ModFilter(isRegFormat(Form));
1043 filter = new DumbFilter();
1044 opcodeToSet = Opcode;
1054 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1055 assert(Form == X86Local::RawFrm);
1056 opcodeType = ONEBYTE;
1057 filter = new ExactFilter(Opcode);
1058 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1062 opcodeType = ONEBYTE;
1064 #define EXTENSION_TABLE(n) case 0x##n:
1065 ONE_BYTE_EXTENSION_TABLES
1066 #undef EXTENSION_TABLE
1069 llvm_unreachable("Fell through the cracks of a single-byte "
1071 case X86Local::MRM0r:
1072 case X86Local::MRM1r:
1073 case X86Local::MRM2r:
1074 case X86Local::MRM3r:
1075 case X86Local::MRM4r:
1076 case X86Local::MRM5r:
1077 case X86Local::MRM6r:
1078 case X86Local::MRM7r:
1079 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1081 case X86Local::MRM0m:
1082 case X86Local::MRM1m:
1083 case X86Local::MRM2m:
1084 case X86Local::MRM3m:
1085 case X86Local::MRM4m:
1086 case X86Local::MRM5m:
1087 case X86Local::MRM6m:
1088 case X86Local::MRM7m:
1089 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1104 llvm_unreachable("Unhandled escape opcode form");
1105 case X86Local::MRM0r:
1106 case X86Local::MRM1r:
1107 case X86Local::MRM2r:
1108 case X86Local::MRM3r:
1109 case X86Local::MRM4r:
1110 case X86Local::MRM5r:
1111 case X86Local::MRM6r:
1112 case X86Local::MRM7r:
1113 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1115 case X86Local::MRM0m:
1116 case X86Local::MRM1m:
1117 case X86Local::MRM2m:
1118 case X86Local::MRM3m:
1119 case X86Local::MRM4m:
1120 case X86Local::MRM5m:
1121 case X86Local::MRM6m:
1122 case X86Local::MRM7m:
1123 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1128 if (needsModRMForDecode(Form))
1129 filter = new ModFilter(isRegFormat(Form));
1131 filter = new DumbFilter();
1133 } // switch (Opcode)
1134 opcodeToSet = Opcode;
1135 } // switch (Prefix)
1137 assert(opcodeType != (OpcodeType)-1 &&
1138 "Opcode type not set");
1139 assert(filter && "Filter not set");
1141 if (Form == X86Local::AddRegFrm) {
1142 assert(((opcodeToSet & 7) == 0) &&
1143 "ADDREG_FRM opcode not aligned");
1145 uint8_t currentOpcode;
1147 for (currentOpcode = opcodeToSet;
1148 currentOpcode < opcodeToSet + 8;
1150 tables.setTableFields(opcodeType,
1154 UID, Is32Bit, IgnoresVEX_L);
1156 tables.setTableFields(opcodeType,
1160 UID, Is32Bit, IgnoresVEX_L);
1168 #define TYPE(str, type) if (s == str) return type;
1169 OperandType RecognizableInstr::typeFromString(const std::string &s,
1171 bool hasREX_WPrefix,
1172 bool hasOpSizePrefix) {
1174 // For SSE instructions, we ignore the OpSize prefix and force operand
1176 TYPE("GR16", TYPE_R16)
1177 TYPE("GR32", TYPE_R32)
1178 TYPE("GR64", TYPE_R64)
1180 if(hasREX_WPrefix) {
1181 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1183 TYPE("GR32", TYPE_R32)
1185 if(!hasOpSizePrefix) {
1186 // For instructions without an OpSize prefix, a declared 16-bit register or
1187 // immediate encoding is special.
1188 TYPE("GR16", TYPE_R16)
1189 TYPE("i16imm", TYPE_IMM16)
1191 TYPE("i16mem", TYPE_Mv)
1192 TYPE("i16imm", TYPE_IMMv)
1193 TYPE("i16i8imm", TYPE_IMMv)
1194 TYPE("GR16", TYPE_Rv)
1195 TYPE("i32mem", TYPE_Mv)
1196 TYPE("i32imm", TYPE_IMMv)
1197 TYPE("i32i8imm", TYPE_IMM32)
1198 TYPE("u32u8imm", TYPE_IMM32)
1199 TYPE("GR32", TYPE_Rv)
1200 TYPE("GR32orGR64", TYPE_R32)
1201 TYPE("i64mem", TYPE_Mv)
1202 TYPE("i64i32imm", TYPE_IMM64)
1203 TYPE("i64i8imm", TYPE_IMM64)
1204 TYPE("GR64", TYPE_R64)
1205 TYPE("i8mem", TYPE_M8)
1206 TYPE("i8imm", TYPE_IMM8)
1207 TYPE("GR8", TYPE_R8)
1208 TYPE("VR128", TYPE_XMM128)
1209 TYPE("VR128X", TYPE_XMM128)
1210 TYPE("f128mem", TYPE_M128)
1211 TYPE("f256mem", TYPE_M256)
1212 TYPE("f512mem", TYPE_M512)
1213 TYPE("FR64", TYPE_XMM64)
1214 TYPE("FR64X", TYPE_XMM64)
1215 TYPE("f64mem", TYPE_M64FP)
1216 TYPE("sdmem", TYPE_M64FP)
1217 TYPE("FR32", TYPE_XMM32)
1218 TYPE("FR32X", TYPE_XMM32)
1219 TYPE("f32mem", TYPE_M32FP)
1220 TYPE("ssmem", TYPE_M32FP)
1221 TYPE("RST", TYPE_ST)
1222 TYPE("i128mem", TYPE_M128)
1223 TYPE("i256mem", TYPE_M256)
1224 TYPE("i512mem", TYPE_M512)
1225 TYPE("i64i32imm_pcrel", TYPE_REL64)
1226 TYPE("i16imm_pcrel", TYPE_REL16)
1227 TYPE("i32imm_pcrel", TYPE_REL32)
1228 TYPE("SSECC", TYPE_IMM3)
1229 TYPE("AVXCC", TYPE_IMM5)
1230 TYPE("AVX512RC", TYPE_IMM32)
1231 TYPE("brtarget", TYPE_RELv)
1232 TYPE("uncondbrtarget", TYPE_RELv)
1233 TYPE("brtarget8", TYPE_REL8)
1234 TYPE("f80mem", TYPE_M80FP)
1235 TYPE("lea32mem", TYPE_LEA)
1236 TYPE("lea64_32mem", TYPE_LEA)
1237 TYPE("lea64mem", TYPE_LEA)
1238 TYPE("VR64", TYPE_MM64)
1239 TYPE("i64imm", TYPE_IMMv)
1240 TYPE("opaque32mem", TYPE_M1616)
1241 TYPE("opaque48mem", TYPE_M1632)
1242 TYPE("opaque80mem", TYPE_M1664)
1243 TYPE("opaque512mem", TYPE_M512)
1244 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1245 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1246 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1247 TYPE("offset8", TYPE_MOFFS8)
1248 TYPE("offset16", TYPE_MOFFS16)
1249 TYPE("offset32", TYPE_MOFFS32)
1250 TYPE("offset64", TYPE_MOFFS64)
1251 TYPE("VR256", TYPE_XMM256)
1252 TYPE("VR256X", TYPE_XMM256)
1253 TYPE("VR512", TYPE_XMM512)
1254 TYPE("VK1", TYPE_VK1)
1255 TYPE("VK1WM", TYPE_VK1)
1256 TYPE("VK8", TYPE_VK8)
1257 TYPE("VK8WM", TYPE_VK8)
1258 TYPE("VK16", TYPE_VK16)
1259 TYPE("VK16WM", TYPE_VK16)
1260 TYPE("GR16_NOAX", TYPE_Rv)
1261 TYPE("GR32_NOAX", TYPE_Rv)
1262 TYPE("GR64_NOAX", TYPE_R64)
1263 TYPE("vx32mem", TYPE_M32)
1264 TYPE("vy32mem", TYPE_M32)
1265 TYPE("vz32mem", TYPE_M32)
1266 TYPE("vx64mem", TYPE_M64)
1267 TYPE("vy64mem", TYPE_M64)
1268 TYPE("vy64xmem", TYPE_M64)
1269 TYPE("vz64mem", TYPE_M64)
1270 errs() << "Unhandled type string " << s << "\n";
1271 llvm_unreachable("Unhandled type string");
1275 #define ENCODING(str, encoding) if (s == str) return encoding;
1276 OperandEncoding RecognizableInstr::immediateEncodingFromString
1277 (const std::string &s,
1278 bool hasOpSizePrefix) {
1279 if(!hasOpSizePrefix) {
1280 // For instructions without an OpSize prefix, a declared 16-bit register or
1281 // immediate encoding is special.
1282 ENCODING("i16imm", ENCODING_IW)
1284 ENCODING("i32i8imm", ENCODING_IB)
1285 ENCODING("u32u8imm", ENCODING_IB)
1286 ENCODING("SSECC", ENCODING_IB)
1287 ENCODING("AVXCC", ENCODING_IB)
1288 ENCODING("AVX512RC", ENCODING_IB)
1289 ENCODING("i16imm", ENCODING_Iv)
1290 ENCODING("i16i8imm", ENCODING_IB)
1291 ENCODING("i32imm", ENCODING_Iv)
1292 ENCODING("i64i32imm", ENCODING_ID)
1293 ENCODING("i64i8imm", ENCODING_IB)
1294 ENCODING("i8imm", ENCODING_IB)
1295 // This is not a typo. Instructions like BLENDVPD put
1296 // register IDs in 8-bit immediates nowadays.
1297 ENCODING("FR32", ENCODING_IB)
1298 ENCODING("FR64", ENCODING_IB)
1299 ENCODING("VR128", ENCODING_IB)
1300 ENCODING("VR256", ENCODING_IB)
1301 ENCODING("FR32X", ENCODING_IB)
1302 ENCODING("FR64X", ENCODING_IB)
1303 ENCODING("VR128X", ENCODING_IB)
1304 ENCODING("VR256X", ENCODING_IB)
1305 ENCODING("VR512", ENCODING_IB)
1306 errs() << "Unhandled immediate encoding " << s << "\n";
1307 llvm_unreachable("Unhandled immediate encoding");
1310 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1311 (const std::string &s,
1312 bool hasOpSizePrefix) {
1313 ENCODING("RST", ENCODING_FP)
1314 ENCODING("GR16", ENCODING_RM)
1315 ENCODING("GR32", ENCODING_RM)
1316 ENCODING("GR32orGR64", ENCODING_RM)
1317 ENCODING("GR64", ENCODING_RM)
1318 ENCODING("GR8", ENCODING_RM)
1319 ENCODING("VR128", ENCODING_RM)
1320 ENCODING("VR128X", ENCODING_RM)
1321 ENCODING("FR64", ENCODING_RM)
1322 ENCODING("FR32", ENCODING_RM)
1323 ENCODING("FR64X", ENCODING_RM)
1324 ENCODING("FR32X", ENCODING_RM)
1325 ENCODING("VR64", ENCODING_RM)
1326 ENCODING("VR256", ENCODING_RM)
1327 ENCODING("VR256X", ENCODING_RM)
1328 ENCODING("VR512", ENCODING_RM)
1329 ENCODING("VK1", ENCODING_RM)
1330 ENCODING("VK8", ENCODING_RM)
1331 ENCODING("VK16", ENCODING_RM)
1332 errs() << "Unhandled R/M register encoding " << s << "\n";
1333 llvm_unreachable("Unhandled R/M register encoding");
1336 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1337 (const std::string &s,
1338 bool hasOpSizePrefix) {
1339 ENCODING("GR16", ENCODING_REG)
1340 ENCODING("GR32", ENCODING_REG)
1341 ENCODING("GR32orGR64", ENCODING_REG)
1342 ENCODING("GR64", ENCODING_REG)
1343 ENCODING("GR8", ENCODING_REG)
1344 ENCODING("VR128", ENCODING_REG)
1345 ENCODING("FR64", ENCODING_REG)
1346 ENCODING("FR32", ENCODING_REG)
1347 ENCODING("VR64", ENCODING_REG)
1348 ENCODING("SEGMENT_REG", ENCODING_REG)
1349 ENCODING("DEBUG_REG", ENCODING_REG)
1350 ENCODING("CONTROL_REG", ENCODING_REG)
1351 ENCODING("VR256", ENCODING_REG)
1352 ENCODING("VR256X", ENCODING_REG)
1353 ENCODING("VR128X", ENCODING_REG)
1354 ENCODING("FR64X", ENCODING_REG)
1355 ENCODING("FR32X", ENCODING_REG)
1356 ENCODING("VR512", ENCODING_REG)
1357 ENCODING("VK1", ENCODING_REG)
1358 ENCODING("VK8", ENCODING_REG)
1359 ENCODING("VK16", ENCODING_REG)
1360 ENCODING("VK1WM", ENCODING_REG)
1361 ENCODING("VK8WM", ENCODING_REG)
1362 ENCODING("VK16WM", ENCODING_REG)
1363 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1364 llvm_unreachable("Unhandled reg/opcode register encoding");
1367 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1368 (const std::string &s,
1369 bool hasOpSizePrefix) {
1370 ENCODING("GR32", ENCODING_VVVV)
1371 ENCODING("GR64", ENCODING_VVVV)
1372 ENCODING("FR32", ENCODING_VVVV)
1373 ENCODING("FR64", ENCODING_VVVV)
1374 ENCODING("VR128", ENCODING_VVVV)
1375 ENCODING("VR256", ENCODING_VVVV)
1376 ENCODING("FR32X", ENCODING_VVVV)
1377 ENCODING("FR64X", ENCODING_VVVV)
1378 ENCODING("VR128X", ENCODING_VVVV)
1379 ENCODING("VR256X", ENCODING_VVVV)
1380 ENCODING("VR512", ENCODING_VVVV)
1381 ENCODING("VK1", ENCODING_VVVV)
1382 ENCODING("VK8", ENCODING_VVVV)
1383 ENCODING("VK16", ENCODING_VVVV)
1384 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1385 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1388 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1389 (const std::string &s,
1390 bool hasOpSizePrefix) {
1391 ENCODING("VK1WM", ENCODING_WRITEMASK)
1392 ENCODING("VK8WM", ENCODING_WRITEMASK)
1393 ENCODING("VK16WM", ENCODING_WRITEMASK)
1394 errs() << "Unhandled mask register encoding " << s << "\n";
1395 llvm_unreachable("Unhandled mask register encoding");
1398 OperandEncoding RecognizableInstr::memoryEncodingFromString
1399 (const std::string &s,
1400 bool hasOpSizePrefix) {
1401 ENCODING("i16mem", ENCODING_RM)
1402 ENCODING("i32mem", ENCODING_RM)
1403 ENCODING("i64mem", ENCODING_RM)
1404 ENCODING("i8mem", ENCODING_RM)
1405 ENCODING("ssmem", ENCODING_RM)
1406 ENCODING("sdmem", ENCODING_RM)
1407 ENCODING("f128mem", ENCODING_RM)
1408 ENCODING("f256mem", ENCODING_RM)
1409 ENCODING("f512mem", ENCODING_RM)
1410 ENCODING("f64mem", ENCODING_RM)
1411 ENCODING("f32mem", ENCODING_RM)
1412 ENCODING("i128mem", ENCODING_RM)
1413 ENCODING("i256mem", ENCODING_RM)
1414 ENCODING("i512mem", ENCODING_RM)
1415 ENCODING("f80mem", ENCODING_RM)
1416 ENCODING("lea32mem", ENCODING_RM)
1417 ENCODING("lea64_32mem", ENCODING_RM)
1418 ENCODING("lea64mem", ENCODING_RM)
1419 ENCODING("opaque32mem", ENCODING_RM)
1420 ENCODING("opaque48mem", ENCODING_RM)
1421 ENCODING("opaque80mem", ENCODING_RM)
1422 ENCODING("opaque512mem", ENCODING_RM)
1423 ENCODING("vx32mem", ENCODING_RM)
1424 ENCODING("vy32mem", ENCODING_RM)
1425 ENCODING("vz32mem", ENCODING_RM)
1426 ENCODING("vx64mem", ENCODING_RM)
1427 ENCODING("vy64mem", ENCODING_RM)
1428 ENCODING("vy64xmem", ENCODING_RM)
1429 ENCODING("vz64mem", ENCODING_RM)
1430 errs() << "Unhandled memory encoding " << s << "\n";
1431 llvm_unreachable("Unhandled memory encoding");
1434 OperandEncoding RecognizableInstr::relocationEncodingFromString
1435 (const std::string &s,
1436 bool hasOpSizePrefix) {
1437 if(!hasOpSizePrefix) {
1438 // For instructions without an OpSize prefix, a declared 16-bit register or
1439 // immediate encoding is special.
1440 ENCODING("i16imm", ENCODING_IW)
1442 ENCODING("i16imm", ENCODING_Iv)
1443 ENCODING("i16i8imm", ENCODING_IB)
1444 ENCODING("i32imm", ENCODING_Iv)
1445 ENCODING("i32i8imm", ENCODING_IB)
1446 ENCODING("i64i32imm", ENCODING_ID)
1447 ENCODING("i64i8imm", ENCODING_IB)
1448 ENCODING("i8imm", ENCODING_IB)
1449 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1450 ENCODING("i16imm_pcrel", ENCODING_IW)
1451 ENCODING("i32imm_pcrel", ENCODING_ID)
1452 ENCODING("brtarget", ENCODING_Iv)
1453 ENCODING("brtarget8", ENCODING_IB)
1454 ENCODING("i64imm", ENCODING_IO)
1455 ENCODING("offset8", ENCODING_Ia)
1456 ENCODING("offset16", ENCODING_Ia)
1457 ENCODING("offset32", ENCODING_Ia)
1458 ENCODING("offset64", ENCODING_Ia)
1459 errs() << "Unhandled relocation encoding " << s << "\n";
1460 llvm_unreachable("Unhandled relocation encoding");
1463 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1464 (const std::string &s,
1465 bool hasOpSizePrefix) {
1466 ENCODING("GR32", ENCODING_Rv)
1467 ENCODING("GR64", ENCODING_RO)
1468 ENCODING("GR16", ENCODING_Rv)
1469 ENCODING("GR8", ENCODING_RB)
1470 ENCODING("GR16_NOAX", ENCODING_Rv)
1471 ENCODING("GR32_NOAX", ENCODING_Rv)
1472 ENCODING("GR64_NOAX", ENCODING_RO)
1473 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1474 llvm_unreachable("Unhandled opcode modifier encoding");