1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
38 // A clone of X86 since we can't depend on something that is generated.
48 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
49 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
50 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
51 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
54 #define MAP(from, to) MRM_##from = to,
63 D8 = 3, D9 = 4, DA = 5, DB = 6,
64 DC = 7, DD = 8, DE = 9, DF = 10,
67 P_0F_AE = 16, P_0F_01 = 17
71 // If rows are added to the opcode extension tables, then corresponding entries
72 // must be added here.
74 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
75 // that byte to ONE_BYTE_EXTENSION_TABLES.
77 // If the row corresponds to two bytes where the first is 0f, add an entry for
78 // the second byte to TWO_BYTE_EXTENSION_TABLES.
80 // If the row corresponds to some other set of bytes, you will need to modify
81 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
82 // to the X86 TD files, except in two cases: if the first two bytes of such a
83 // new combination are 0f 38 or 0f 3a, you just have to add maps called
84 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
85 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
86 // in RecognizableInstr::emitDecodePath().
88 #define ONE_BYTE_EXTENSION_TABLES \
100 EXTENSION_TABLE(d2) \
101 EXTENSION_TABLE(d3) \
102 EXTENSION_TABLE(f6) \
103 EXTENSION_TABLE(f7) \
104 EXTENSION_TABLE(fe) \
107 #define TWO_BYTE_EXTENSION_TABLES \
108 EXTENSION_TABLE(00) \
109 EXTENSION_TABLE(01) \
110 EXTENSION_TABLE(18) \
111 EXTENSION_TABLE(71) \
112 EXTENSION_TABLE(72) \
113 EXTENSION_TABLE(73) \
114 EXTENSION_TABLE(ae) \
115 EXTENSION_TABLE(b9) \
116 EXTENSION_TABLE(ba) \
119 using namespace X86Disassembler;
121 /// needsModRMForDecode - Indicates whether a particular instruction requires a
122 /// ModR/M byte for the instruction to be properly decoded. For example, a
123 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
126 /// @param form - The form of the instruction.
127 /// @return - true if the form implies that a ModR/M byte is required, false
129 static bool needsModRMForDecode(uint8_t form) {
130 if (form == X86Local::MRMDestReg ||
131 form == X86Local::MRMDestMem ||
132 form == X86Local::MRMSrcReg ||
133 form == X86Local::MRMSrcMem ||
134 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
135 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
141 /// isRegFormat - Indicates whether a particular form requires the Mod field of
142 /// the ModR/M byte to be 0b11.
144 /// @param form - The form of the instruction.
145 /// @return - true if the form implies that Mod must be 0b11, false
147 static bool isRegFormat(uint8_t form) {
148 if (form == X86Local::MRMDestReg ||
149 form == X86Local::MRMSrcReg ||
150 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
156 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
157 /// Useful for switch statements and the like.
159 /// @param init - A reference to the BitsInit to be decoded.
160 /// @return - The field, with the first bit in the BitsInit as the lowest
162 static uint8_t byteFromBitsInit(BitsInit &init) {
163 int width = init.getNumBits();
165 assert(width <= 8 && "Field is too large for uint8_t!");
172 for (index = 0; index < width; index++) {
173 if (static_cast<BitInit*>(init.getBit(index))->getValue())
182 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
183 /// name of the field.
185 /// @param rec - The record from which to extract the value.
186 /// @param name - The name of the field in the record.
187 /// @return - The field, as translated by byteFromBitsInit().
188 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
189 BitsInit* bits = rec->getValueAsBitsInit(name);
190 return byteFromBitsInit(*bits);
193 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
194 const CodeGenInstruction &insn,
199 Name = Rec->getName();
200 Spec = &tables.specForUID(UID);
202 if (!Rec->isSubClassOf("X86Inst")) {
203 ShouldBeEmitted = false;
207 Prefix = byteFromRec(Rec, "Prefix");
208 Opcode = byteFromRec(Rec, "Opcode");
209 Form = byteFromRec(Rec, "FormBits");
210 SegOvr = byteFromRec(Rec, "SegOvrBits");
212 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
213 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
214 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
215 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
217 Name = Rec->getName();
218 AsmString = Rec->getValueAsString("AsmString");
220 Operands = &insn.OperandList;
222 IsSSE = HasOpSizePrefix && (Name.find("16") == Name.npos);
223 HasFROperands = false;
225 ShouldBeEmitted = true;
228 void RecognizableInstr::processInstr(DisassemblerTables &tables,
229 const CodeGenInstruction &insn,
232 RecognizableInstr recogInstr(tables, insn, uid);
234 recogInstr.emitInstructionSpecifier(tables);
236 if (recogInstr.shouldBeEmitted())
237 recogInstr.emitDecodePath(tables);
240 InstructionContext RecognizableInstr::insnContext() const {
241 InstructionContext insnContext;
243 if (Name.find("64") != Name.npos || HasREX_WPrefix) {
244 if (HasREX_WPrefix && HasOpSizePrefix)
245 insnContext = IC_64BIT_REXW_OPSIZE;
246 else if (HasOpSizePrefix)
247 insnContext = IC_64BIT_OPSIZE;
248 else if (HasREX_WPrefix && Prefix == X86Local::XS)
249 insnContext = IC_64BIT_REXW_XS;
250 else if (HasREX_WPrefix && Prefix == X86Local::XD)
251 insnContext = IC_64BIT_REXW_XD;
252 else if (Prefix == X86Local::XD)
253 insnContext = IC_64BIT_XD;
254 else if (Prefix == X86Local::XS)
255 insnContext = IC_64BIT_XS;
256 else if (HasREX_WPrefix)
257 insnContext = IC_64BIT_REXW;
259 insnContext = IC_64BIT;
262 insnContext = IC_OPSIZE;
263 else if (Prefix == X86Local::XD)
265 else if (Prefix == X86Local::XS)
274 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
275 // Filter out intrinsics
277 if (!Rec->isSubClassOf("X86Inst"))
278 return FILTER_STRONG;
280 if (Form == X86Local::Pseudo ||
282 return FILTER_STRONG;
284 // Filter out instructions with a LOCK prefix;
285 // prefer forms that do not have the prefix
289 // Filter out artificial instructions
291 if (Name.find("TAILJMP") != Name.npos ||
292 Name.find("_Int") != Name.npos ||
293 Name.find("_int") != Name.npos ||
294 Name.find("Int_") != Name.npos ||
295 Name.find("_NOREX") != Name.npos ||
296 Name.find("EH_RETURN") != Name.npos ||
297 Name.find("V_SET") != Name.npos ||
298 Name.find("LOCK_") != Name.npos ||
299 Name.find("WIN") != Name.npos)
300 return FILTER_STRONG;
304 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
306 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
309 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
311 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
313 if (Name.find("Fs") != Name.npos)
315 if (Name == "MOVLPDrr" ||
316 Name == "MOVLPSrr" ||
322 Name == "MOVSX16rm8" ||
323 Name == "MOVSX16rr8" ||
324 Name == "MOVZX16rm8" ||
325 Name == "MOVZX16rr8" ||
326 Name == "PUSH32i16" ||
327 Name == "PUSH64i16" ||
328 Name == "MOVPQI2QImr" ||
333 Name == "MMX_MOVD64rrv164" ||
334 Name == "CRC32m16" ||
335 Name == "MOV64ri64i32" ||
339 // Filter out instructions with segment override prefixes.
340 // They're too messy to handle now and we'll special case them if needed.
343 return FILTER_STRONG;
345 // Filter out instructions that can't be printed.
347 if (AsmString.size() == 0)
348 return FILTER_STRONG;
350 // Filter out instructions with subreg operands.
352 if (AsmString.find("subreg") != AsmString.npos)
353 return FILTER_STRONG;
355 assert(Form != X86Local::MRMInitReg &&
356 "FORMAT_MRMINITREG instruction not skipped");
358 if (HasFROperands && Name.find("MOV") != Name.npos &&
359 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
360 (Name.find("to") != Name.npos)))
363 return FILTER_NORMAL;
366 void RecognizableInstr::handleOperand(
368 unsigned &operandIndex,
369 unsigned &physicalOperandIndex,
370 unsigned &numPhysicalOperands,
371 unsigned *operandMapping,
372 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
374 if (physicalOperandIndex >= numPhysicalOperands)
377 assert(physicalOperandIndex < numPhysicalOperands);
380 while (operandMapping[operandIndex] != operandIndex) {
381 Spec->operands[operandIndex].encoding = ENCODING_DUP;
382 Spec->operands[operandIndex].type =
383 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
387 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
389 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
391 Spec->operands[operandIndex].type = typeFromString(typeName,
397 ++physicalOperandIndex;
400 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
403 if (!Rec->isSubClassOf("X86Inst"))
408 Spec->filtered = true;
411 ShouldBeEmitted = false;
417 Spec->insnContext = insnContext();
419 const std::vector<CodeGenInstruction::OperandInfo> &OperandList = *Operands;
421 unsigned operandIndex;
422 unsigned numOperands = OperandList.size();
423 unsigned numPhysicalOperands = 0;
425 // operandMapping maps from operands in OperandList to their originals.
426 // If operandMapping[i] != i, then the entry is a duplicate.
427 unsigned operandMapping[X86_MAX_OPERANDS];
429 bool hasFROperands = false;
431 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
433 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
434 if (OperandList[operandIndex].Constraints.size()) {
435 const CodeGenInstruction::ConstraintInfo &Constraint =
436 OperandList[operandIndex].Constraints[0];
437 if (Constraint.isTied()) {
438 operandMapping[operandIndex] = Constraint.getTiedOperand();
440 ++numPhysicalOperands;
441 operandMapping[operandIndex] = operandIndex;
444 ++numPhysicalOperands;
445 operandMapping[operandIndex] = operandIndex;
448 const std::string &recName = OperandList[operandIndex].Rec->getName();
450 if (recName.find("FR") != recName.npos)
451 hasFROperands = true;
454 if (hasFROperands && Name.find("MOV") != Name.npos &&
455 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
456 (Name.find("to") != Name.npos)))
457 ShouldBeEmitted = false;
459 if (!ShouldBeEmitted)
462 #define HANDLE_OPERAND(class) \
463 handleOperand(false, \
465 physicalOperandIndex, \
466 numPhysicalOperands, \
468 class##EncodingFromString);
470 #define HANDLE_OPTIONAL(class) \
471 handleOperand(true, \
473 physicalOperandIndex, \
474 numPhysicalOperands, \
476 class##EncodingFromString);
478 // operandIndex should always be < numOperands
480 // physicalOperandIndex should always be < numPhysicalOperands
481 unsigned physicalOperandIndex = 0;
484 case X86Local::RawFrm:
485 // Operand 1 (optional) is an address or immediate.
486 // Operand 2 (optional) is an immediate.
487 assert(numPhysicalOperands <= 2 &&
488 "Unexpected number of operands for RawFrm");
489 HANDLE_OPTIONAL(relocation)
490 HANDLE_OPTIONAL(immediate)
492 case X86Local::AddRegFrm:
493 // Operand 1 is added to the opcode.
494 // Operand 2 (optional) is an address.
495 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
496 "Unexpected number of operands for AddRegFrm");
497 HANDLE_OPERAND(opcodeModifier)
498 HANDLE_OPTIONAL(relocation)
500 case X86Local::MRMDestReg:
501 // Operand 1 is a register operand in the R/M field.
502 // Operand 2 is a register operand in the Reg/Opcode field.
503 // Operand 3 (optional) is an immediate.
504 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
505 "Unexpected number of operands for MRMDestRegFrm");
506 HANDLE_OPERAND(rmRegister)
507 HANDLE_OPERAND(roRegister)
508 HANDLE_OPTIONAL(immediate)
510 case X86Local::MRMDestMem:
511 // Operand 1 is a memory operand (possibly SIB-extended)
512 // Operand 2 is a register operand in the Reg/Opcode field.
513 // Operand 3 (optional) is an immediate.
514 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
515 "Unexpected number of operands for MRMDestMemFrm");
516 HANDLE_OPERAND(memory)
517 HANDLE_OPERAND(roRegister)
518 HANDLE_OPTIONAL(immediate)
520 case X86Local::MRMSrcReg:
521 // Operand 1 is a register operand in the Reg/Opcode field.
522 // Operand 2 is a register operand in the R/M field.
523 // Operand 3 (optional) is an immediate.
524 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
525 "Unexpected number of operands for MRMSrcRegFrm");
526 HANDLE_OPERAND(roRegister)
527 HANDLE_OPERAND(rmRegister)
528 HANDLE_OPTIONAL(immediate)
530 case X86Local::MRMSrcMem:
531 // Operand 1 is a register operand in the Reg/Opcode field.
532 // Operand 2 is a memory operand (possibly SIB-extended)
533 // Operand 3 (optional) is an immediate.
534 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
535 "Unexpected number of operands for MRMSrcMemFrm");
536 HANDLE_OPERAND(roRegister)
537 HANDLE_OPERAND(memory)
538 HANDLE_OPTIONAL(immediate)
540 case X86Local::MRM0r:
541 case X86Local::MRM1r:
542 case X86Local::MRM2r:
543 case X86Local::MRM3r:
544 case X86Local::MRM4r:
545 case X86Local::MRM5r:
546 case X86Local::MRM6r:
547 case X86Local::MRM7r:
548 // Operand 1 is a register operand in the R/M field.
549 // Operand 2 (optional) is an immediate or relocation.
550 assert(numPhysicalOperands <= 2 &&
551 "Unexpected number of operands for MRMnRFrm");
552 HANDLE_OPTIONAL(rmRegister)
553 HANDLE_OPTIONAL(relocation)
555 case X86Local::MRM0m:
556 case X86Local::MRM1m:
557 case X86Local::MRM2m:
558 case X86Local::MRM3m:
559 case X86Local::MRM4m:
560 case X86Local::MRM5m:
561 case X86Local::MRM6m:
562 case X86Local::MRM7m:
563 // Operand 1 is a memory operand (possibly SIB-extended)
564 // Operand 2 (optional) is an immediate or relocation.
565 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
566 "Unexpected number of operands for MRMnMFrm");
567 HANDLE_OPERAND(memory)
568 HANDLE_OPTIONAL(relocation)
570 case X86Local::MRMInitReg:
575 #undef HANDLE_OPERAND
576 #undef HANDLE_OPTIONAL
579 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
580 // Special cases where the LLVM tables are not complete
582 #define MAP(from, to) \
583 case X86Local::MRM_##from: \
584 filter = new ExactFilter(0x##from); \
587 #define EXACTCASE(class, name, lastbyte) \
588 if (Name == name) { \
589 tables.setTableFields(class, \
592 ExactFilter(lastbyte), \
594 Spec->modifierBase = Opcode; \
598 EXACTCASE(TWOBYTE, "INVEPT", 0x80)
599 EXACTCASE(TWOBYTE, "INVVPID", 0x81)
601 if (Name == "INVLPG") {
602 tables.setTableFields(TWOBYTE,
605 ExtendedFilter(false, 7),
607 Spec->modifierBase = Opcode;
611 OpcodeType opcodeType = (OpcodeType)-1;
613 ModRMFilter* filter = NULL;
614 uint8_t opcodeToSet = 0;
617 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
621 opcodeType = TWOBYTE;
624 #define EXTENSION_TABLE(n) case 0x##n:
625 TWO_BYTE_EXTENSION_TABLES
626 #undef EXTENSION_TABLE
629 llvm_unreachable("Unhandled two-byte extended opcode");
630 case X86Local::MRM0r:
631 case X86Local::MRM1r:
632 case X86Local::MRM2r:
633 case X86Local::MRM3r:
634 case X86Local::MRM4r:
635 case X86Local::MRM5r:
636 case X86Local::MRM6r:
637 case X86Local::MRM7r:
638 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
640 case X86Local::MRM0m:
641 case X86Local::MRM1m:
642 case X86Local::MRM2m:
643 case X86Local::MRM3m:
644 case X86Local::MRM4m:
645 case X86Local::MRM5m:
646 case X86Local::MRM6m:
647 case X86Local::MRM7m:
648 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
654 if (needsModRMForDecode(Form))
655 filter = new ModFilter(isRegFormat(Form));
657 filter = new DumbFilter();
661 opcodeToSet = Opcode;
664 opcodeType = THREEBYTE_38;
665 if (needsModRMForDecode(Form))
666 filter = new ModFilter(isRegFormat(Form));
668 filter = new DumbFilter();
669 opcodeToSet = Opcode;
672 opcodeType = THREEBYTE_3A;
673 if (needsModRMForDecode(Form))
674 filter = new ModFilter(isRegFormat(Form));
676 filter = new DumbFilter();
677 opcodeToSet = Opcode;
687 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
688 opcodeType = ONEBYTE;
689 if (Form == X86Local::AddRegFrm) {
690 Spec->modifierType = MODIFIER_MODRM;
691 Spec->modifierBase = Opcode;
692 filter = new AddRegEscapeFilter(Opcode);
694 filter = new EscapeFilter(true, Opcode);
696 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
699 opcodeType = ONEBYTE;
701 #define EXTENSION_TABLE(n) case 0x##n:
702 ONE_BYTE_EXTENSION_TABLES
703 #undef EXTENSION_TABLE
706 llvm_unreachable("Fell through the cracks of a single-byte "
708 case X86Local::MRM0r:
709 case X86Local::MRM1r:
710 case X86Local::MRM2r:
711 case X86Local::MRM3r:
712 case X86Local::MRM4r:
713 case X86Local::MRM5r:
714 case X86Local::MRM6r:
715 case X86Local::MRM7r:
716 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
718 case X86Local::MRM0m:
719 case X86Local::MRM1m:
720 case X86Local::MRM2m:
721 case X86Local::MRM3m:
722 case X86Local::MRM4m:
723 case X86Local::MRM5m:
724 case X86Local::MRM6m:
725 case X86Local::MRM7m:
726 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
739 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
742 if (needsModRMForDecode(Form))
743 filter = new ModFilter(isRegFormat(Form));
745 filter = new DumbFilter();
748 opcodeToSet = Opcode;
751 assert(opcodeType != (OpcodeType)-1 &&
752 "Opcode type not set");
753 assert(filter && "Filter not set");
755 if (Form == X86Local::AddRegFrm) {
756 if(Spec->modifierType != MODIFIER_MODRM) {
757 assert(opcodeToSet < 0xf9 &&
758 "Not enough room for all ADDREG_FRM operands");
760 uint8_t currentOpcode;
762 for (currentOpcode = opcodeToSet;
763 currentOpcode < opcodeToSet + 8;
765 tables.setTableFields(opcodeType,
771 Spec->modifierType = MODIFIER_OPCODE;
772 Spec->modifierBase = opcodeToSet;
774 // modifierBase was set where MODIFIER_MODRM was set
775 tables.setTableFields(opcodeType,
782 tables.setTableFields(opcodeType,
788 Spec->modifierType = MODIFIER_NONE;
789 Spec->modifierBase = opcodeToSet;
797 #define TYPE(str, type) if (s == str) return type;
798 OperandType RecognizableInstr::typeFromString(const std::string &s,
801 bool hasOpSizePrefix) {
803 // For SSE instructions, we ignore the OpSize prefix and force operand
805 TYPE("GR16", TYPE_R16)
806 TYPE("GR32", TYPE_R32)
807 TYPE("GR64", TYPE_R64)
810 // For instructions with a REX_W prefix, a declared 32-bit register encoding
812 TYPE("GR32", TYPE_R32)
814 if(!hasOpSizePrefix) {
815 // For instructions without an OpSize prefix, a declared 16-bit register or
816 // immediate encoding is special.
817 TYPE("GR16", TYPE_R16)
818 TYPE("i16imm", TYPE_IMM16)
820 TYPE("i16mem", TYPE_Mv)
821 TYPE("i16imm", TYPE_IMMv)
822 TYPE("i16i8imm", TYPE_IMMv)
823 TYPE("GR16", TYPE_Rv)
824 TYPE("i32mem", TYPE_Mv)
825 TYPE("i32imm", TYPE_IMMv)
826 TYPE("i32i8imm", TYPE_IMM32)
827 TYPE("GR32", TYPE_Rv)
828 TYPE("i64mem", TYPE_Mv)
829 TYPE("i64i32imm", TYPE_IMM64)
830 TYPE("i64i8imm", TYPE_IMM64)
831 TYPE("GR64", TYPE_R64)
832 TYPE("i8mem", TYPE_M8)
833 TYPE("i8imm", TYPE_IMM8)
835 TYPE("VR128", TYPE_XMM128)
836 TYPE("f128mem", TYPE_M128)
837 TYPE("FR64", TYPE_XMM64)
838 TYPE("f64mem", TYPE_M64FP)
839 TYPE("FR32", TYPE_XMM32)
840 TYPE("f32mem", TYPE_M32FP)
842 TYPE("i128mem", TYPE_M128)
843 TYPE("i64i32imm_pcrel", TYPE_REL64)
844 TYPE("i32imm_pcrel", TYPE_REL32)
845 TYPE("SSECC", TYPE_IMM8)
846 TYPE("brtarget", TYPE_RELv)
847 TYPE("brtarget8", TYPE_REL8)
848 TYPE("f80mem", TYPE_M80FP)
849 TYPE("lea32mem", TYPE_LEA)
850 TYPE("lea64_32mem", TYPE_LEA)
851 TYPE("lea64mem", TYPE_LEA)
852 TYPE("VR64", TYPE_MM64)
853 TYPE("i64imm", TYPE_IMMv)
854 TYPE("opaque32mem", TYPE_M1616)
855 TYPE("opaque48mem", TYPE_M1632)
856 TYPE("opaque80mem", TYPE_M1664)
857 TYPE("opaque512mem", TYPE_M512)
858 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
859 TYPE("DEBUG_REG", TYPE_DEBUGREG)
860 TYPE("CONTROL_REG_32", TYPE_CR32)
861 TYPE("CONTROL_REG_64", TYPE_CR64)
862 TYPE("offset8", TYPE_MOFFS8)
863 TYPE("offset16", TYPE_MOFFS16)
864 TYPE("offset32", TYPE_MOFFS32)
865 TYPE("offset64", TYPE_MOFFS64)
866 errs() << "Unhandled type string " << s << "\n";
867 llvm_unreachable("Unhandled type string");
871 #define ENCODING(str, encoding) if (s == str) return encoding;
872 OperandEncoding RecognizableInstr::immediateEncodingFromString
873 (const std::string &s,
874 bool hasOpSizePrefix) {
875 if(!hasOpSizePrefix) {
876 // For instructions without an OpSize prefix, a declared 16-bit register or
877 // immediate encoding is special.
878 ENCODING("i16imm", ENCODING_IW)
880 ENCODING("i32i8imm", ENCODING_IB)
881 ENCODING("SSECC", ENCODING_IB)
882 ENCODING("i16imm", ENCODING_Iv)
883 ENCODING("i16i8imm", ENCODING_IB)
884 ENCODING("i32imm", ENCODING_Iv)
885 ENCODING("i64i32imm", ENCODING_ID)
886 ENCODING("i64i8imm", ENCODING_IB)
887 ENCODING("i8imm", ENCODING_IB)
888 errs() << "Unhandled immediate encoding " << s << "\n";
889 llvm_unreachable("Unhandled immediate encoding");
892 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
893 (const std::string &s,
894 bool hasOpSizePrefix) {
895 ENCODING("GR16", ENCODING_RM)
896 ENCODING("GR32", ENCODING_RM)
897 ENCODING("GR64", ENCODING_RM)
898 ENCODING("GR8", ENCODING_RM)
899 ENCODING("VR128", ENCODING_RM)
900 ENCODING("FR64", ENCODING_RM)
901 ENCODING("FR32", ENCODING_RM)
902 ENCODING("VR64", ENCODING_RM)
903 errs() << "Unhandled R/M register encoding " << s << "\n";
904 llvm_unreachable("Unhandled R/M register encoding");
907 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
908 (const std::string &s,
909 bool hasOpSizePrefix) {
910 ENCODING("GR16", ENCODING_REG)
911 ENCODING("GR32", ENCODING_REG)
912 ENCODING("GR64", ENCODING_REG)
913 ENCODING("GR8", ENCODING_REG)
914 ENCODING("VR128", ENCODING_REG)
915 ENCODING("FR64", ENCODING_REG)
916 ENCODING("FR32", ENCODING_REG)
917 ENCODING("VR64", ENCODING_REG)
918 ENCODING("SEGMENT_REG", ENCODING_REG)
919 ENCODING("DEBUG_REG", ENCODING_REG)
920 ENCODING("CONTROL_REG_32", ENCODING_REG)
921 ENCODING("CONTROL_REG_64", ENCODING_REG)
922 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
923 llvm_unreachable("Unhandled reg/opcode register encoding");
926 OperandEncoding RecognizableInstr::memoryEncodingFromString
927 (const std::string &s,
928 bool hasOpSizePrefix) {
929 ENCODING("i16mem", ENCODING_RM)
930 ENCODING("i32mem", ENCODING_RM)
931 ENCODING("i64mem", ENCODING_RM)
932 ENCODING("i8mem", ENCODING_RM)
933 ENCODING("f128mem", ENCODING_RM)
934 ENCODING("f64mem", ENCODING_RM)
935 ENCODING("f32mem", ENCODING_RM)
936 ENCODING("i128mem", ENCODING_RM)
937 ENCODING("f80mem", ENCODING_RM)
938 ENCODING("lea32mem", ENCODING_RM)
939 ENCODING("lea64_32mem", ENCODING_RM)
940 ENCODING("lea64mem", ENCODING_RM)
941 ENCODING("opaque32mem", ENCODING_RM)
942 ENCODING("opaque48mem", ENCODING_RM)
943 ENCODING("opaque80mem", ENCODING_RM)
944 ENCODING("opaque512mem", ENCODING_RM)
945 errs() << "Unhandled memory encoding " << s << "\n";
946 llvm_unreachable("Unhandled memory encoding");
949 OperandEncoding RecognizableInstr::relocationEncodingFromString
950 (const std::string &s,
951 bool hasOpSizePrefix) {
952 if(!hasOpSizePrefix) {
953 // For instructions without an OpSize prefix, a declared 16-bit register or
954 // immediate encoding is special.
955 ENCODING("i16imm", ENCODING_IW)
957 ENCODING("i16imm", ENCODING_Iv)
958 ENCODING("i16i8imm", ENCODING_IB)
959 ENCODING("i32imm", ENCODING_Iv)
960 ENCODING("i32i8imm", ENCODING_IB)
961 ENCODING("i64i32imm", ENCODING_ID)
962 ENCODING("i64i8imm", ENCODING_IB)
963 ENCODING("i8imm", ENCODING_IB)
964 ENCODING("i64i32imm_pcrel", ENCODING_ID)
965 ENCODING("i32imm_pcrel", ENCODING_ID)
966 ENCODING("brtarget", ENCODING_Iv)
967 ENCODING("brtarget8", ENCODING_IB)
968 ENCODING("i64imm", ENCODING_IO)
969 ENCODING("offset8", ENCODING_Ia)
970 ENCODING("offset16", ENCODING_Ia)
971 ENCODING("offset32", ENCODING_Ia)
972 ENCODING("offset64", ENCODING_Ia)
973 errs() << "Unhandled relocation encoding " << s << "\n";
974 llvm_unreachable("Unhandled relocation encoding");
977 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
978 (const std::string &s,
979 bool hasOpSizePrefix) {
980 ENCODING("RST", ENCODING_I)
981 ENCODING("GR32", ENCODING_Rv)
982 ENCODING("GR64", ENCODING_RO)
983 ENCODING("GR16", ENCODING_Rv)
984 ENCODING("GR8", ENCODING_RB)
985 errs() << "Unhandled opcode modifier encoding " << s << "\n";
986 llvm_unreachable("Unhandled opcode modifier encoding");