1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
91 // A clone of X86 since we can't depend on something that is generated.
107 MRMXr = 14, MRMXm = 15,
108 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
109 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
110 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
111 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
112 #define MAP(from, to) MRM_##from = to,
119 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6
123 PS = 1, PD = 2, XS = 3, XD = 4
127 VEX = 1, XOP = 2, EVEX = 3
131 OpSize16 = 1, OpSize32 = 2
135 AdSize16 = 1, AdSize32 = 2, AdSize64 = 3
139 using namespace X86Disassembler;
141 /// isRegFormat - Indicates whether a particular form requires the Mod field of
142 /// the ModR/M byte to be 0b11.
144 /// @param form - The form of the instruction.
145 /// @return - true if the form implies that Mod must be 0b11, false
147 static bool isRegFormat(uint8_t form) {
148 return (form == X86Local::MRMDestReg ||
149 form == X86Local::MRMSrcReg ||
150 form == X86Local::MRMXr ||
151 (form >= X86Local::MRM0r && form <= X86Local::MRM7r));
154 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
155 /// Useful for switch statements and the like.
157 /// @param init - A reference to the BitsInit to be decoded.
158 /// @return - The field, with the first bit in the BitsInit as the lowest
160 static uint8_t byteFromBitsInit(BitsInit &init) {
161 int width = init.getNumBits();
163 assert(width <= 8 && "Field is too large for uint8_t!");
170 for (index = 0; index < width; index++) {
171 if (static_cast<BitInit*>(init.getBit(index))->getValue())
180 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
181 /// name of the field.
183 /// @param rec - The record from which to extract the value.
184 /// @param name - The name of the field in the record.
185 /// @return - The field, as translated by byteFromBitsInit().
186 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
187 BitsInit* bits = rec->getValueAsBitsInit(name);
188 return byteFromBitsInit(*bits);
191 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
192 const CodeGenInstruction &insn,
197 Name = Rec->getName();
198 Spec = &tables.specForUID(UID);
200 if (!Rec->isSubClassOf("X86Inst")) {
201 ShouldBeEmitted = false;
205 OpPrefix = byteFromRec(Rec, "OpPrefixBits");
206 OpMap = byteFromRec(Rec, "OpMapBits");
207 Opcode = byteFromRec(Rec, "Opcode");
208 Form = byteFromRec(Rec, "FormBits");
209 Encoding = byteFromRec(Rec, "OpEncBits");
211 OpSize = byteFromRec(Rec, "OpSizeBits");
212 AdSize = byteFromRec(Rec, "AdSizeBits");
213 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
214 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
215 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
216 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
217 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
218 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
219 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
220 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
221 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
222 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
223 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
224 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
225 CD8_Scale = byteFromRec(Rec, "CD8_Scale");
227 Name = Rec->getName();
228 AsmString = Rec->getValueAsString("AsmString");
230 Operands = &insn.Operands.OperandList;
232 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
234 // Check for 64-bit inst which does not require REX
237 // FIXME: Is there some better way to check for In64BitMode?
238 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
239 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
240 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
241 Predicates[i]->getName().find("In32Bit") != Name.npos) {
245 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
251 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
252 ShouldBeEmitted = false;
256 // Special case since there is no attribute class for 64-bit and VEX
257 if (Name == "VMASKMOVDQU64") {
258 ShouldBeEmitted = false;
262 ShouldBeEmitted = true;
265 void RecognizableInstr::processInstr(DisassemblerTables &tables,
266 const CodeGenInstruction &insn,
269 // Ignore "asm parser only" instructions.
270 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
273 RecognizableInstr recogInstr(tables, insn, uid);
275 if (recogInstr.shouldBeEmitted()) {
276 recogInstr.emitInstructionSpecifier();
277 recogInstr.emitDecodePath(tables);
281 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
282 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
283 (HasEVEX_KZ ? n##_KZ : \
284 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
286 InstructionContext RecognizableInstr::insnContext() const {
287 InstructionContext insnContext;
289 if (Encoding == X86Local::EVEX) {
290 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
291 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
292 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
295 if (HasVEX_LPrefix && HasVEX_WPrefix) {
296 if (OpPrefix == X86Local::PD)
297 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
298 else if (OpPrefix == X86Local::XS)
299 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
300 else if (OpPrefix == X86Local::XD)
301 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
302 else if (OpPrefix == X86Local::PS)
303 insnContext = EVEX_KB(IC_EVEX_L_W);
305 errs() << "Instruction does not use a prefix: " << Name << "\n";
306 llvm_unreachable("Invalid prefix");
308 } else if (HasVEX_LPrefix) {
310 if (OpPrefix == X86Local::PD)
311 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
312 else if (OpPrefix == X86Local::XS)
313 insnContext = EVEX_KB(IC_EVEX_L_XS);
314 else if (OpPrefix == X86Local::XD)
315 insnContext = EVEX_KB(IC_EVEX_L_XD);
316 else if (OpPrefix == X86Local::PS)
317 insnContext = EVEX_KB(IC_EVEX_L);
319 errs() << "Instruction does not use a prefix: " << Name << "\n";
320 llvm_unreachable("Invalid prefix");
323 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
325 if (OpPrefix == X86Local::PD)
326 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
327 else if (OpPrefix == X86Local::XS)
328 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
329 else if (OpPrefix == X86Local::XD)
330 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
331 else if (OpPrefix == X86Local::PS)
332 insnContext = EVEX_KB(IC_EVEX_L2_W);
334 errs() << "Instruction does not use a prefix: " << Name << "\n";
335 llvm_unreachable("Invalid prefix");
337 } else if (HasEVEX_L2Prefix) {
339 if (OpPrefix == X86Local::PD)
340 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
341 else if (OpPrefix == X86Local::XD)
342 insnContext = EVEX_KB(IC_EVEX_L2_XD);
343 else if (OpPrefix == X86Local::XS)
344 insnContext = EVEX_KB(IC_EVEX_L2_XS);
345 else if (OpPrefix == X86Local::PS)
346 insnContext = EVEX_KB(IC_EVEX_L2);
348 errs() << "Instruction does not use a prefix: " << Name << "\n";
349 llvm_unreachable("Invalid prefix");
352 else if (HasVEX_WPrefix) {
354 if (OpPrefix == X86Local::PD)
355 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
356 else if (OpPrefix == X86Local::XS)
357 insnContext = EVEX_KB(IC_EVEX_W_XS);
358 else if (OpPrefix == X86Local::XD)
359 insnContext = EVEX_KB(IC_EVEX_W_XD);
360 else if (OpPrefix == X86Local::PS)
361 insnContext = EVEX_KB(IC_EVEX_W);
363 errs() << "Instruction does not use a prefix: " << Name << "\n";
364 llvm_unreachable("Invalid prefix");
368 else if (OpPrefix == X86Local::PD)
369 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
370 else if (OpPrefix == X86Local::XD)
371 insnContext = EVEX_KB(IC_EVEX_XD);
372 else if (OpPrefix == X86Local::XS)
373 insnContext = EVEX_KB(IC_EVEX_XS);
375 insnContext = EVEX_KB(IC_EVEX);
377 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
378 if (HasVEX_LPrefix && HasVEX_WPrefix) {
379 if (OpPrefix == X86Local::PD)
380 insnContext = IC_VEX_L_W_OPSIZE;
381 else if (OpPrefix == X86Local::XS)
382 insnContext = IC_VEX_L_W_XS;
383 else if (OpPrefix == X86Local::XD)
384 insnContext = IC_VEX_L_W_XD;
385 else if (OpPrefix == X86Local::PS)
386 insnContext = IC_VEX_L_W;
388 errs() << "Instruction does not use a prefix: " << Name << "\n";
389 llvm_unreachable("Invalid prefix");
391 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
392 insnContext = IC_VEX_L_OPSIZE;
393 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix)
394 insnContext = IC_VEX_W_OPSIZE;
395 else if (OpPrefix == X86Local::PD)
396 insnContext = IC_VEX_OPSIZE;
397 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
398 insnContext = IC_VEX_L_XS;
399 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
400 insnContext = IC_VEX_L_XD;
401 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS)
402 insnContext = IC_VEX_W_XS;
403 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD)
404 insnContext = IC_VEX_W_XD;
405 else if (HasVEX_WPrefix && OpPrefix == X86Local::PS)
406 insnContext = IC_VEX_W;
407 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
408 insnContext = IC_VEX_L;
409 else if (OpPrefix == X86Local::XD)
410 insnContext = IC_VEX_XD;
411 else if (OpPrefix == X86Local::XS)
412 insnContext = IC_VEX_XS;
413 else if (OpPrefix == X86Local::PS)
414 insnContext = IC_VEX;
416 errs() << "Instruction does not use a prefix: " << Name << "\n";
417 llvm_unreachable("Invalid prefix");
419 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) {
420 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
421 insnContext = IC_64BIT_REXW_OPSIZE;
422 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32)
423 insnContext = IC_64BIT_REXW_ADSIZE;
424 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
425 insnContext = IC_64BIT_XD_OPSIZE;
426 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
427 insnContext = IC_64BIT_XS_OPSIZE;
428 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32)
429 insnContext = IC_64BIT_OPSIZE_ADSIZE;
430 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
431 insnContext = IC_64BIT_OPSIZE;
432 else if (AdSize == X86Local::AdSize32)
433 insnContext = IC_64BIT_ADSIZE;
434 else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
435 insnContext = IC_64BIT_REXW_XS;
436 else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
437 insnContext = IC_64BIT_REXW_XD;
438 else if (OpPrefix == X86Local::XD)
439 insnContext = IC_64BIT_XD;
440 else if (OpPrefix == X86Local::XS)
441 insnContext = IC_64BIT_XS;
442 else if (HasREX_WPrefix)
443 insnContext = IC_64BIT_REXW;
445 insnContext = IC_64BIT;
447 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
448 insnContext = IC_XD_OPSIZE;
449 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
450 insnContext = IC_XS_OPSIZE;
451 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16)
452 insnContext = IC_OPSIZE_ADSIZE;
453 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
454 insnContext = IC_OPSIZE;
455 else if (AdSize == X86Local::AdSize16)
456 insnContext = IC_ADSIZE;
457 else if (OpPrefix == X86Local::XD)
459 else if (OpPrefix == X86Local::XS)
468 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
469 // The scaling factor for AVX512 compressed displacement encoding is an
470 // instruction attribute. Adjust the ModRM encoding type to include the
471 // scale for compressed displacement.
472 if (encoding != ENCODING_RM || CD8_Scale == 0)
474 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
475 assert(encoding <= ENCODING_RM_CD64 && "Invalid CDisp scaling");
478 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
479 unsigned &physicalOperandIndex,
480 unsigned &numPhysicalOperands,
481 const unsigned *operandMapping,
482 OperandEncoding (*encodingFromString)
486 if (physicalOperandIndex >= numPhysicalOperands)
489 assert(physicalOperandIndex < numPhysicalOperands);
492 while (operandMapping[operandIndex] != operandIndex) {
493 Spec->operands[operandIndex].encoding = ENCODING_DUP;
494 Spec->operands[operandIndex].type =
495 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
499 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
501 OperandEncoding encoding = encodingFromString(typeName, OpSize);
502 // Adjust the encoding type for an operand based on the instruction.
503 adjustOperandEncoding(encoding);
504 Spec->operands[operandIndex].encoding = encoding;
505 Spec->operands[operandIndex].type = typeFromString(typeName,
506 HasREX_WPrefix, OpSize);
509 ++physicalOperandIndex;
512 void RecognizableInstr::emitInstructionSpecifier() {
515 Spec->insnContext = insnContext();
517 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
519 unsigned numOperands = OperandList.size();
520 unsigned numPhysicalOperands = 0;
522 // operandMapping maps from operands in OperandList to their originals.
523 // If operandMapping[i] != i, then the entry is a duplicate.
524 unsigned operandMapping[X86_MAX_OPERANDS];
525 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
527 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
528 if (!OperandList[operandIndex].Constraints.empty()) {
529 const CGIOperandList::ConstraintInfo &Constraint =
530 OperandList[operandIndex].Constraints[0];
531 if (Constraint.isTied()) {
532 operandMapping[operandIndex] = operandIndex;
533 operandMapping[Constraint.getTiedOperand()] = operandIndex;
535 ++numPhysicalOperands;
536 operandMapping[operandIndex] = operandIndex;
539 ++numPhysicalOperands;
540 operandMapping[operandIndex] = operandIndex;
544 #define HANDLE_OPERAND(class) \
545 handleOperand(false, \
547 physicalOperandIndex, \
548 numPhysicalOperands, \
550 class##EncodingFromString);
552 #define HANDLE_OPTIONAL(class) \
553 handleOperand(true, \
555 physicalOperandIndex, \
556 numPhysicalOperands, \
558 class##EncodingFromString);
560 // operandIndex should always be < numOperands
561 unsigned operandIndex = 0;
562 // physicalOperandIndex should always be < numPhysicalOperands
563 unsigned physicalOperandIndex = 0;
565 // Given the set of prefix bits, how many additional operands does the
567 unsigned additionalOperands = 0;
568 if (HasVEX_4V || HasVEX_4VOp3)
569 ++additionalOperands;
571 ++additionalOperands;
574 default: llvm_unreachable("Unhandled form");
575 case X86Local::RawFrmSrc:
576 HANDLE_OPERAND(relocation);
578 case X86Local::RawFrmDst:
579 HANDLE_OPERAND(relocation);
581 case X86Local::RawFrmDstSrc:
582 HANDLE_OPERAND(relocation);
583 HANDLE_OPERAND(relocation);
585 case X86Local::RawFrm:
586 // Operand 1 (optional) is an address or immediate.
587 // Operand 2 (optional) is an immediate.
588 assert(numPhysicalOperands <= 2 &&
589 "Unexpected number of operands for RawFrm");
590 HANDLE_OPTIONAL(relocation)
591 HANDLE_OPTIONAL(immediate)
593 case X86Local::RawFrmMemOffs:
594 // Operand 1 is an address.
595 HANDLE_OPERAND(relocation);
597 case X86Local::AddRegFrm:
598 // Operand 1 is added to the opcode.
599 // Operand 2 (optional) is an address.
600 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
601 "Unexpected number of operands for AddRegFrm");
602 HANDLE_OPERAND(opcodeModifier)
603 HANDLE_OPTIONAL(relocation)
605 case X86Local::MRMDestReg:
606 // Operand 1 is a register operand in the R/M field.
607 // - In AVX512 there may be a mask operand here -
608 // Operand 2 is a register operand in the Reg/Opcode field.
609 // - In AVX, there is a register operand in the VEX.vvvv field here -
610 // Operand 3 (optional) is an immediate.
611 assert(numPhysicalOperands >= 2 + additionalOperands &&
612 numPhysicalOperands <= 3 + additionalOperands &&
613 "Unexpected number of operands for MRMDestRegFrm");
615 HANDLE_OPERAND(rmRegister)
617 HANDLE_OPERAND(writemaskRegister)
620 // FIXME: In AVX, the register below becomes the one encoded
621 // in ModRMVEX and the one above the one in the VEX.VVVV field
622 HANDLE_OPERAND(vvvvRegister)
624 HANDLE_OPERAND(roRegister)
625 HANDLE_OPTIONAL(immediate)
627 case X86Local::MRMDestMem:
628 // Operand 1 is a memory operand (possibly SIB-extended)
629 // Operand 2 is a register operand in the Reg/Opcode field.
630 // - In AVX, there is a register operand in the VEX.vvvv field here -
631 // Operand 3 (optional) is an immediate.
632 assert(numPhysicalOperands >= 2 + additionalOperands &&
633 numPhysicalOperands <= 3 + additionalOperands &&
634 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
636 HANDLE_OPERAND(memory)
639 HANDLE_OPERAND(writemaskRegister)
642 // FIXME: In AVX, the register below becomes the one encoded
643 // in ModRMVEX and the one above the one in the VEX.VVVV field
644 HANDLE_OPERAND(vvvvRegister)
646 HANDLE_OPERAND(roRegister)
647 HANDLE_OPTIONAL(immediate)
649 case X86Local::MRMSrcReg:
650 // Operand 1 is a register operand in the Reg/Opcode field.
651 // Operand 2 is a register operand in the R/M field.
652 // - In AVX, there is a register operand in the VEX.vvvv field here -
653 // Operand 3 (optional) is an immediate.
654 // Operand 4 (optional) is an immediate.
656 assert(numPhysicalOperands >= 2 + additionalOperands &&
657 numPhysicalOperands <= 4 + additionalOperands &&
658 "Unexpected number of operands for MRMSrcRegFrm");
660 HANDLE_OPERAND(roRegister)
663 HANDLE_OPERAND(writemaskRegister)
666 // FIXME: In AVX, the register below becomes the one encoded
667 // in ModRMVEX and the one above the one in the VEX.VVVV field
668 HANDLE_OPERAND(vvvvRegister)
671 HANDLE_OPERAND(immediate)
673 HANDLE_OPERAND(rmRegister)
676 HANDLE_OPERAND(vvvvRegister)
678 if (!HasMemOp4Prefix)
679 HANDLE_OPTIONAL(immediate)
680 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
681 HANDLE_OPTIONAL(immediate)
683 case X86Local::MRMSrcMem:
684 // Operand 1 is a register operand in the Reg/Opcode field.
685 // Operand 2 is a memory operand (possibly SIB-extended)
686 // - In AVX, there is a register operand in the VEX.vvvv field here -
687 // Operand 3 (optional) is an immediate.
689 assert(numPhysicalOperands >= 2 + additionalOperands &&
690 numPhysicalOperands <= 4 + additionalOperands &&
691 "Unexpected number of operands for MRMSrcMemFrm");
693 HANDLE_OPERAND(roRegister)
696 HANDLE_OPERAND(writemaskRegister)
699 // FIXME: In AVX, the register below becomes the one encoded
700 // in ModRMVEX and the one above the one in the VEX.VVVV field
701 HANDLE_OPERAND(vvvvRegister)
704 HANDLE_OPERAND(immediate)
706 HANDLE_OPERAND(memory)
709 HANDLE_OPERAND(vvvvRegister)
711 if (!HasMemOp4Prefix)
712 HANDLE_OPTIONAL(immediate)
713 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
715 case X86Local::MRMXr:
716 case X86Local::MRM0r:
717 case X86Local::MRM1r:
718 case X86Local::MRM2r:
719 case X86Local::MRM3r:
720 case X86Local::MRM4r:
721 case X86Local::MRM5r:
722 case X86Local::MRM6r:
723 case X86Local::MRM7r:
724 // Operand 1 is a register operand in the R/M field.
725 // Operand 2 (optional) is an immediate or relocation.
726 // Operand 3 (optional) is an immediate.
727 assert(numPhysicalOperands >= 0 + additionalOperands &&
728 numPhysicalOperands <= 3 + additionalOperands &&
729 "Unexpected number of operands for MRMnr");
732 HANDLE_OPERAND(vvvvRegister)
735 HANDLE_OPERAND(writemaskRegister)
736 HANDLE_OPTIONAL(rmRegister)
737 HANDLE_OPTIONAL(relocation)
738 HANDLE_OPTIONAL(immediate)
740 case X86Local::MRMXm:
741 case X86Local::MRM0m:
742 case X86Local::MRM1m:
743 case X86Local::MRM2m:
744 case X86Local::MRM3m:
745 case X86Local::MRM4m:
746 case X86Local::MRM5m:
747 case X86Local::MRM6m:
748 case X86Local::MRM7m:
749 // Operand 1 is a memory operand (possibly SIB-extended)
750 // Operand 2 (optional) is an immediate or relocation.
751 assert(numPhysicalOperands >= 1 + additionalOperands &&
752 numPhysicalOperands <= 2 + additionalOperands &&
753 "Unexpected number of operands for MRMnm");
756 HANDLE_OPERAND(vvvvRegister)
758 HANDLE_OPERAND(writemaskRegister)
759 HANDLE_OPERAND(memory)
760 HANDLE_OPTIONAL(relocation)
762 case X86Local::RawFrmImm8:
763 // operand 1 is a 16-bit immediate
764 // operand 2 is an 8-bit immediate
765 assert(numPhysicalOperands == 2 &&
766 "Unexpected number of operands for X86Local::RawFrmImm8");
767 HANDLE_OPERAND(immediate)
768 HANDLE_OPERAND(immediate)
770 case X86Local::RawFrmImm16:
771 // operand 1 is a 16-bit immediate
772 // operand 2 is a 16-bit immediate
773 HANDLE_OPERAND(immediate)
774 HANDLE_OPERAND(immediate)
776 case X86Local::MRM_F8:
777 if (Opcode == 0xc6) {
778 assert(numPhysicalOperands == 1 &&
779 "Unexpected number of operands for X86Local::MRM_F8");
780 HANDLE_OPERAND(immediate)
781 } else if (Opcode == 0xc7) {
782 assert(numPhysicalOperands == 1 &&
783 "Unexpected number of operands for X86Local::MRM_F8");
784 HANDLE_OPERAND(relocation)
787 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2:
788 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8:
789 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB:
790 case X86Local::MRM_CF: case X86Local::MRM_D0: case X86Local::MRM_D1:
791 case X86Local::MRM_D4: case X86Local::MRM_D5: case X86Local::MRM_D6:
792 case X86Local::MRM_D7: case X86Local::MRM_D8: case X86Local::MRM_D9:
793 case X86Local::MRM_DA: case X86Local::MRM_DB: case X86Local::MRM_DC:
794 case X86Local::MRM_DD: case X86Local::MRM_DE: case X86Local::MRM_DF:
795 case X86Local::MRM_E0: case X86Local::MRM_E1: case X86Local::MRM_E2:
796 case X86Local::MRM_E3: case X86Local::MRM_E4: case X86Local::MRM_E5:
797 case X86Local::MRM_E8: case X86Local::MRM_E9: case X86Local::MRM_EA:
798 case X86Local::MRM_EB: case X86Local::MRM_EC: case X86Local::MRM_ED:
799 case X86Local::MRM_EE: case X86Local::MRM_F0: case X86Local::MRM_F1:
800 case X86Local::MRM_F2: case X86Local::MRM_F3: case X86Local::MRM_F4:
801 case X86Local::MRM_F5: case X86Local::MRM_F6: case X86Local::MRM_F7:
802 case X86Local::MRM_F9: case X86Local::MRM_FA: case X86Local::MRM_FB:
803 case X86Local::MRM_FC: case X86Local::MRM_FD: case X86Local::MRM_FE:
804 case X86Local::MRM_FF:
809 #undef HANDLE_OPERAND
810 #undef HANDLE_OPTIONAL
813 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
814 // Special cases where the LLVM tables are not complete
816 #define MAP(from, to) \
817 case X86Local::MRM_##from:
819 OpcodeType opcodeType = (OpcodeType)-1;
821 ModRMFilter* filter = nullptr;
822 uint8_t opcodeToSet = 0;
825 default: llvm_unreachable("Invalid map!");
834 default: llvm_unreachable("Unexpected map!");
835 case X86Local::OB: opcodeType = ONEBYTE; break;
836 case X86Local::TB: opcodeType = TWOBYTE; break;
837 case X86Local::T8: opcodeType = THREEBYTE_38; break;
838 case X86Local::TA: opcodeType = THREEBYTE_3A; break;
839 case X86Local::XOP8: opcodeType = XOP8_MAP; break;
840 case X86Local::XOP9: opcodeType = XOP9_MAP; break;
841 case X86Local::XOPA: opcodeType = XOPA_MAP; break;
846 filter = new DumbFilter();
848 case X86Local::MRMDestReg: case X86Local::MRMDestMem:
849 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem:
850 case X86Local::MRMXr: case X86Local::MRMXm:
851 filter = new ModFilter(isRegFormat(Form));
853 case X86Local::MRM0r: case X86Local::MRM1r:
854 case X86Local::MRM2r: case X86Local::MRM3r:
855 case X86Local::MRM4r: case X86Local::MRM5r:
856 case X86Local::MRM6r: case X86Local::MRM7r:
857 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
859 case X86Local::MRM0m: case X86Local::MRM1m:
860 case X86Local::MRM2m: case X86Local::MRM3m:
861 case X86Local::MRM4m: case X86Local::MRM5m:
862 case X86Local::MRM6m: case X86Local::MRM7m:
863 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
866 filter = new ExactFilter(0xC0 + Form - X86Local::MRM_C0); \
870 opcodeToSet = Opcode;
874 unsigned AddressSize = 0;
876 case X86Local::AdSize16: AddressSize = 16; break;
877 case X86Local::AdSize32: AddressSize = 32; break;
878 case X86Local::AdSize64: AddressSize = 64; break;
881 assert(opcodeType != (OpcodeType)-1 &&
882 "Opcode type not set");
883 assert(filter && "Filter not set");
885 if (Form == X86Local::AddRegFrm) {
886 assert(((opcodeToSet & 7) == 0) &&
887 "ADDREG_FRM opcode not aligned");
889 uint8_t currentOpcode;
891 for (currentOpcode = opcodeToSet;
892 currentOpcode < opcodeToSet + 8;
894 tables.setTableFields(opcodeType,
898 UID, Is32Bit, IgnoresVEX_L, AddressSize);
900 tables.setTableFields(opcodeType,
904 UID, Is32Bit, IgnoresVEX_L, AddressSize);
912 #define TYPE(str, type) if (s == str) return type;
913 OperandType RecognizableInstr::typeFromString(const std::string &s,
917 // For instructions with a REX_W prefix, a declared 32-bit register encoding
919 TYPE("GR32", TYPE_R32)
921 if(OpSize == X86Local::OpSize16) {
922 // For OpSize16 instructions, a declared 16-bit register or
923 // immediate encoding is special.
924 TYPE("GR16", TYPE_Rv)
925 TYPE("i16imm", TYPE_IMMv)
926 } else if(OpSize == X86Local::OpSize32) {
927 // For OpSize32 instructions, a declared 32-bit register or
928 // immediate encoding is special.
929 TYPE("GR32", TYPE_Rv)
931 TYPE("i16mem", TYPE_Mv)
932 TYPE("i16imm", TYPE_IMM16)
933 TYPE("i16i8imm", TYPE_IMMv)
934 TYPE("GR16", TYPE_R16)
935 TYPE("i32mem", TYPE_Mv)
936 TYPE("i32imm", TYPE_IMMv)
937 TYPE("i32i8imm", TYPE_IMM32)
938 TYPE("GR32", TYPE_R32)
939 TYPE("GR32orGR64", TYPE_R32)
940 TYPE("i64mem", TYPE_Mv)
941 TYPE("i64i32imm", TYPE_IMM64)
942 TYPE("i64i8imm", TYPE_IMM64)
943 TYPE("GR64", TYPE_R64)
944 TYPE("i8mem", TYPE_M8)
945 TYPE("i8imm", TYPE_IMM8)
946 TYPE("u8imm", TYPE_UIMM8)
947 TYPE("i32u8imm", TYPE_UIMM8)
949 TYPE("VR128", TYPE_XMM128)
950 TYPE("VR128X", TYPE_XMM128)
951 TYPE("f128mem", TYPE_M128)
952 TYPE("f256mem", TYPE_M256)
953 TYPE("f512mem", TYPE_M512)
954 TYPE("FR64", TYPE_XMM64)
955 TYPE("FR64X", TYPE_XMM64)
956 TYPE("f64mem", TYPE_M64FP)
957 TYPE("sdmem", TYPE_M64FP)
958 TYPE("FR32", TYPE_XMM32)
959 TYPE("FR32X", TYPE_XMM32)
960 TYPE("f32mem", TYPE_M32FP)
961 TYPE("ssmem", TYPE_M32FP)
963 TYPE("i128mem", TYPE_M128)
964 TYPE("i256mem", TYPE_M256)
965 TYPE("i512mem", TYPE_M512)
966 TYPE("i64i32imm_pcrel", TYPE_REL64)
967 TYPE("i16imm_pcrel", TYPE_REL16)
968 TYPE("i32imm_pcrel", TYPE_REL32)
969 TYPE("SSECC", TYPE_IMM3)
970 TYPE("XOPCC", TYPE_IMM3)
971 TYPE("AVXCC", TYPE_IMM5)
972 TYPE("AVX512ICC", TYPE_AVX512ICC)
973 TYPE("AVX512RC", TYPE_IMM32)
974 TYPE("brtarget32", TYPE_RELv)
975 TYPE("brtarget16", TYPE_RELv)
976 TYPE("brtarget8", TYPE_REL8)
977 TYPE("f80mem", TYPE_M80FP)
978 TYPE("lea64_32mem", TYPE_LEA)
979 TYPE("lea64mem", TYPE_LEA)
980 TYPE("VR64", TYPE_MM64)
981 TYPE("i64imm", TYPE_IMMv)
982 TYPE("anymem", TYPE_M)
983 TYPE("opaque32mem", TYPE_M1616)
984 TYPE("opaque48mem", TYPE_M1632)
985 TYPE("opaque80mem", TYPE_M1664)
986 TYPE("opaque512mem", TYPE_M512)
987 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
988 TYPE("DEBUG_REG", TYPE_DEBUGREG)
989 TYPE("CONTROL_REG", TYPE_CONTROLREG)
990 TYPE("srcidx8", TYPE_SRCIDX8)
991 TYPE("srcidx16", TYPE_SRCIDX16)
992 TYPE("srcidx32", TYPE_SRCIDX32)
993 TYPE("srcidx64", TYPE_SRCIDX64)
994 TYPE("dstidx8", TYPE_DSTIDX8)
995 TYPE("dstidx16", TYPE_DSTIDX16)
996 TYPE("dstidx32", TYPE_DSTIDX32)
997 TYPE("dstidx64", TYPE_DSTIDX64)
998 TYPE("offset16_8", TYPE_MOFFS8)
999 TYPE("offset16_16", TYPE_MOFFS16)
1000 TYPE("offset16_32", TYPE_MOFFS32)
1001 TYPE("offset32_8", TYPE_MOFFS8)
1002 TYPE("offset32_16", TYPE_MOFFS16)
1003 TYPE("offset32_32", TYPE_MOFFS32)
1004 TYPE("offset32_64", TYPE_MOFFS64)
1005 TYPE("offset64_8", TYPE_MOFFS8)
1006 TYPE("offset64_16", TYPE_MOFFS16)
1007 TYPE("offset64_32", TYPE_MOFFS32)
1008 TYPE("offset64_64", TYPE_MOFFS64)
1009 TYPE("VR256", TYPE_XMM256)
1010 TYPE("VR256X", TYPE_XMM256)
1011 TYPE("VR512", TYPE_XMM512)
1012 TYPE("VK1", TYPE_VK1)
1013 TYPE("VK1WM", TYPE_VK1)
1014 TYPE("VK2", TYPE_VK2)
1015 TYPE("VK2WM", TYPE_VK2)
1016 TYPE("VK4", TYPE_VK4)
1017 TYPE("VK4WM", TYPE_VK4)
1018 TYPE("VK8", TYPE_VK8)
1019 TYPE("VK8WM", TYPE_VK8)
1020 TYPE("VK16", TYPE_VK16)
1021 TYPE("VK16WM", TYPE_VK16)
1022 TYPE("VK32", TYPE_VK32)
1023 TYPE("VK32WM", TYPE_VK32)
1024 TYPE("VK64", TYPE_VK64)
1025 TYPE("VK64WM", TYPE_VK64)
1026 TYPE("GR16_NOAX", TYPE_Rv)
1027 TYPE("GR32_NOAX", TYPE_Rv)
1028 TYPE("GR64_NOAX", TYPE_R64)
1029 TYPE("vx32mem", TYPE_M32)
1030 TYPE("vy32mem", TYPE_M32)
1031 TYPE("vz32mem", TYPE_M32)
1032 TYPE("vx64mem", TYPE_M64)
1033 TYPE("vy64mem", TYPE_M64)
1034 TYPE("vy64xmem", TYPE_M64)
1035 TYPE("vz64mem", TYPE_M64)
1036 errs() << "Unhandled type string " << s << "\n";
1037 llvm_unreachable("Unhandled type string");
1041 #define ENCODING(str, encoding) if (s == str) return encoding;
1043 RecognizableInstr::immediateEncodingFromString(const std::string &s,
1045 if(OpSize != X86Local::OpSize16) {
1046 // For instructions without an OpSize prefix, a declared 16-bit register or
1047 // immediate encoding is special.
1048 ENCODING("i16imm", ENCODING_IW)
1050 ENCODING("i32i8imm", ENCODING_IB)
1051 ENCODING("SSECC", ENCODING_IB)
1052 ENCODING("XOPCC", ENCODING_IB)
1053 ENCODING("AVXCC", ENCODING_IB)
1054 ENCODING("AVX512ICC", ENCODING_IB)
1055 ENCODING("AVX512RC", ENCODING_IB)
1056 ENCODING("i16imm", ENCODING_Iv)
1057 ENCODING("i16i8imm", ENCODING_IB)
1058 ENCODING("i32imm", ENCODING_Iv)
1059 ENCODING("i64i32imm", ENCODING_ID)
1060 ENCODING("i64i8imm", ENCODING_IB)
1061 ENCODING("i8imm", ENCODING_IB)
1062 ENCODING("u8imm", ENCODING_IB)
1063 ENCODING("i32u8imm", ENCODING_IB)
1064 // This is not a typo. Instructions like BLENDVPD put
1065 // register IDs in 8-bit immediates nowadays.
1066 ENCODING("FR32", ENCODING_IB)
1067 ENCODING("FR64", ENCODING_IB)
1068 ENCODING("VR128", ENCODING_IB)
1069 ENCODING("VR256", ENCODING_IB)
1070 ENCODING("FR32X", ENCODING_IB)
1071 ENCODING("FR64X", ENCODING_IB)
1072 ENCODING("VR128X", ENCODING_IB)
1073 ENCODING("VR256X", ENCODING_IB)
1074 ENCODING("VR512", ENCODING_IB)
1075 errs() << "Unhandled immediate encoding " << s << "\n";
1076 llvm_unreachable("Unhandled immediate encoding");
1080 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1082 ENCODING("RST", ENCODING_FP)
1083 ENCODING("GR16", ENCODING_RM)
1084 ENCODING("GR32", ENCODING_RM)
1085 ENCODING("GR32orGR64", ENCODING_RM)
1086 ENCODING("GR64", ENCODING_RM)
1087 ENCODING("GR8", ENCODING_RM)
1088 ENCODING("VR128", ENCODING_RM)
1089 ENCODING("VR128X", ENCODING_RM)
1090 ENCODING("FR64", ENCODING_RM)
1091 ENCODING("FR32", ENCODING_RM)
1092 ENCODING("FR64X", ENCODING_RM)
1093 ENCODING("FR32X", ENCODING_RM)
1094 ENCODING("VR64", ENCODING_RM)
1095 ENCODING("VR256", ENCODING_RM)
1096 ENCODING("VR256X", ENCODING_RM)
1097 ENCODING("VR512", ENCODING_RM)
1098 ENCODING("VK1", ENCODING_RM)
1099 ENCODING("VK8", ENCODING_RM)
1100 ENCODING("VK16", ENCODING_RM)
1101 ENCODING("VK32", ENCODING_RM)
1102 ENCODING("VK64", ENCODING_RM)
1103 errs() << "Unhandled R/M register encoding " << s << "\n";
1104 llvm_unreachable("Unhandled R/M register encoding");
1108 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1110 ENCODING("GR16", ENCODING_REG)
1111 ENCODING("GR32", ENCODING_REG)
1112 ENCODING("GR32orGR64", ENCODING_REG)
1113 ENCODING("GR64", ENCODING_REG)
1114 ENCODING("GR8", ENCODING_REG)
1115 ENCODING("VR128", ENCODING_REG)
1116 ENCODING("FR64", ENCODING_REG)
1117 ENCODING("FR32", ENCODING_REG)
1118 ENCODING("VR64", ENCODING_REG)
1119 ENCODING("SEGMENT_REG", ENCODING_REG)
1120 ENCODING("DEBUG_REG", ENCODING_REG)
1121 ENCODING("CONTROL_REG", ENCODING_REG)
1122 ENCODING("VR256", ENCODING_REG)
1123 ENCODING("VR256X", ENCODING_REG)
1124 ENCODING("VR128X", ENCODING_REG)
1125 ENCODING("FR64X", ENCODING_REG)
1126 ENCODING("FR32X", ENCODING_REG)
1127 ENCODING("VR512", ENCODING_REG)
1128 ENCODING("VK1", ENCODING_REG)
1129 ENCODING("VK2", ENCODING_REG)
1130 ENCODING("VK4", ENCODING_REG)
1131 ENCODING("VK8", ENCODING_REG)
1132 ENCODING("VK16", ENCODING_REG)
1133 ENCODING("VK32", ENCODING_REG)
1134 ENCODING("VK64", ENCODING_REG)
1135 ENCODING("VK1WM", ENCODING_REG)
1136 ENCODING("VK8WM", ENCODING_REG)
1137 ENCODING("VK16WM", ENCODING_REG)
1138 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1139 llvm_unreachable("Unhandled reg/opcode register encoding");
1143 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1145 ENCODING("GR32", ENCODING_VVVV)
1146 ENCODING("GR64", ENCODING_VVVV)
1147 ENCODING("FR32", ENCODING_VVVV)
1148 ENCODING("FR64", ENCODING_VVVV)
1149 ENCODING("VR128", ENCODING_VVVV)
1150 ENCODING("VR256", ENCODING_VVVV)
1151 ENCODING("FR32X", ENCODING_VVVV)
1152 ENCODING("FR64X", ENCODING_VVVV)
1153 ENCODING("VR128X", ENCODING_VVVV)
1154 ENCODING("VR256X", ENCODING_VVVV)
1155 ENCODING("VR512", ENCODING_VVVV)
1156 ENCODING("VK1", ENCODING_VVVV)
1157 ENCODING("VK2", ENCODING_VVVV)
1158 ENCODING("VK4", ENCODING_VVVV)
1159 ENCODING("VK8", ENCODING_VVVV)
1160 ENCODING("VK16", ENCODING_VVVV)
1161 ENCODING("VK32", ENCODING_VVVV)
1162 ENCODING("VK64", ENCODING_VVVV)
1163 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1164 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1168 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1170 ENCODING("VK1WM", ENCODING_WRITEMASK)
1171 ENCODING("VK2WM", ENCODING_WRITEMASK)
1172 ENCODING("VK4WM", ENCODING_WRITEMASK)
1173 ENCODING("VK8WM", ENCODING_WRITEMASK)
1174 ENCODING("VK16WM", ENCODING_WRITEMASK)
1175 ENCODING("VK32WM", ENCODING_WRITEMASK)
1176 ENCODING("VK64WM", ENCODING_WRITEMASK)
1177 errs() << "Unhandled mask register encoding " << s << "\n";
1178 llvm_unreachable("Unhandled mask register encoding");
1182 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1184 ENCODING("i16mem", ENCODING_RM)
1185 ENCODING("i32mem", ENCODING_RM)
1186 ENCODING("i64mem", ENCODING_RM)
1187 ENCODING("i8mem", ENCODING_RM)
1188 ENCODING("ssmem", ENCODING_RM)
1189 ENCODING("sdmem", ENCODING_RM)
1190 ENCODING("f128mem", ENCODING_RM)
1191 ENCODING("f256mem", ENCODING_RM)
1192 ENCODING("f512mem", ENCODING_RM)
1193 ENCODING("f64mem", ENCODING_RM)
1194 ENCODING("f32mem", ENCODING_RM)
1195 ENCODING("i128mem", ENCODING_RM)
1196 ENCODING("i256mem", ENCODING_RM)
1197 ENCODING("i512mem", ENCODING_RM)
1198 ENCODING("f80mem", ENCODING_RM)
1199 ENCODING("lea64_32mem", ENCODING_RM)
1200 ENCODING("lea64mem", ENCODING_RM)
1201 ENCODING("anymem", ENCODING_RM)
1202 ENCODING("opaque32mem", ENCODING_RM)
1203 ENCODING("opaque48mem", ENCODING_RM)
1204 ENCODING("opaque80mem", ENCODING_RM)
1205 ENCODING("opaque512mem", ENCODING_RM)
1206 ENCODING("vx32mem", ENCODING_RM)
1207 ENCODING("vy32mem", ENCODING_RM)
1208 ENCODING("vz32mem", ENCODING_RM)
1209 ENCODING("vx64mem", ENCODING_RM)
1210 ENCODING("vy64mem", ENCODING_RM)
1211 ENCODING("vy64xmem", ENCODING_RM)
1212 ENCODING("vz64mem", ENCODING_RM)
1213 errs() << "Unhandled memory encoding " << s << "\n";
1214 llvm_unreachable("Unhandled memory encoding");
1218 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1220 if(OpSize != X86Local::OpSize16) {
1221 // For instructions without an OpSize prefix, a declared 16-bit register or
1222 // immediate encoding is special.
1223 ENCODING("i16imm", ENCODING_IW)
1225 ENCODING("i16imm", ENCODING_Iv)
1226 ENCODING("i16i8imm", ENCODING_IB)
1227 ENCODING("i32imm", ENCODING_Iv)
1228 ENCODING("i32i8imm", ENCODING_IB)
1229 ENCODING("i64i32imm", ENCODING_ID)
1230 ENCODING("i64i8imm", ENCODING_IB)
1231 ENCODING("i8imm", ENCODING_IB)
1232 ENCODING("u8imm", ENCODING_IB)
1233 ENCODING("i32u8imm", ENCODING_IB)
1234 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1235 ENCODING("i16imm_pcrel", ENCODING_IW)
1236 ENCODING("i32imm_pcrel", ENCODING_ID)
1237 ENCODING("brtarget32", ENCODING_Iv)
1238 ENCODING("brtarget16", ENCODING_Iv)
1239 ENCODING("brtarget8", ENCODING_IB)
1240 ENCODING("i64imm", ENCODING_IO)
1241 ENCODING("offset16_8", ENCODING_Ia)
1242 ENCODING("offset16_16", ENCODING_Ia)
1243 ENCODING("offset16_32", ENCODING_Ia)
1244 ENCODING("offset32_8", ENCODING_Ia)
1245 ENCODING("offset32_16", ENCODING_Ia)
1246 ENCODING("offset32_32", ENCODING_Ia)
1247 ENCODING("offset32_64", ENCODING_Ia)
1248 ENCODING("offset64_8", ENCODING_Ia)
1249 ENCODING("offset64_16", ENCODING_Ia)
1250 ENCODING("offset64_32", ENCODING_Ia)
1251 ENCODING("offset64_64", ENCODING_Ia)
1252 ENCODING("srcidx8", ENCODING_SI)
1253 ENCODING("srcidx16", ENCODING_SI)
1254 ENCODING("srcidx32", ENCODING_SI)
1255 ENCODING("srcidx64", ENCODING_SI)
1256 ENCODING("dstidx8", ENCODING_DI)
1257 ENCODING("dstidx16", ENCODING_DI)
1258 ENCODING("dstidx32", ENCODING_DI)
1259 ENCODING("dstidx64", ENCODING_DI)
1260 errs() << "Unhandled relocation encoding " << s << "\n";
1261 llvm_unreachable("Unhandled relocation encoding");
1265 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1267 ENCODING("GR32", ENCODING_Rv)
1268 ENCODING("GR64", ENCODING_RO)
1269 ENCODING("GR16", ENCODING_Rv)
1270 ENCODING("GR8", ENCODING_RB)
1271 ENCODING("GR16_NOAX", ENCODING_Rv)
1272 ENCODING("GR32_NOAX", ENCODING_Rv)
1273 ENCODING("GR64_NOAX", ENCODING_RO)
1274 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1275 llvm_unreachable("Unhandled opcode modifier encoding");