1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
66 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
67 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
68 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
69 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
72 #define MAP(from, to) MRM_##from = to,
79 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6,
80 D8 = 7, D9 = 8, DA = 9, DB = 10,
81 DC = 11, DD = 12, DE = 13, DF = 14,
86 PD = 1, XS = 2, XD = 3
90 VEX = 1, XOP = 2, EVEX = 3
94 OpSize16 = 1, OpSize32 = 2
98 // If rows are added to the opcode extension tables, then corresponding entries
99 // must be added here.
101 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
102 // that byte to ONE_BYTE_EXTENSION_TABLES.
104 // If the row corresponds to two bytes where the first is 0f, add an entry for
105 // the second byte to TWO_BYTE_EXTENSION_TABLES.
107 // If the row corresponds to some other set of bytes, you will need to modify
108 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
109 // to the X86 TD files, except in two cases: if the first two bytes of such a
110 // new combination are 0f 38 or 0f 3a, you just have to add maps called
111 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
112 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
113 // in RecognizableInstr::emitDecodePath().
115 #define ONE_BYTE_EXTENSION_TABLES \
116 EXTENSION_TABLE(80) \
117 EXTENSION_TABLE(81) \
118 EXTENSION_TABLE(82) \
119 EXTENSION_TABLE(83) \
120 EXTENSION_TABLE(8f) \
121 EXTENSION_TABLE(c0) \
122 EXTENSION_TABLE(c1) \
123 EXTENSION_TABLE(c6) \
124 EXTENSION_TABLE(c7) \
125 EXTENSION_TABLE(d0) \
126 EXTENSION_TABLE(d1) \
127 EXTENSION_TABLE(d2) \
128 EXTENSION_TABLE(d3) \
129 EXTENSION_TABLE(f6) \
130 EXTENSION_TABLE(f7) \
131 EXTENSION_TABLE(fe) \
134 #define TWO_BYTE_EXTENSION_TABLES \
135 EXTENSION_TABLE(00) \
136 EXTENSION_TABLE(01) \
137 EXTENSION_TABLE(0d) \
138 EXTENSION_TABLE(18) \
139 EXTENSION_TABLE(71) \
140 EXTENSION_TABLE(72) \
141 EXTENSION_TABLE(73) \
142 EXTENSION_TABLE(ae) \
143 EXTENSION_TABLE(ba) \
146 #define THREE_BYTE_38_EXTENSION_TABLES \
149 #define XOP9_MAP_EXTENSION_TABLES \
150 EXTENSION_TABLE(01) \
153 using namespace X86Disassembler;
155 /// needsModRMForDecode - Indicates whether a particular instruction requires a
156 /// ModR/M byte for the instruction to be properly decoded. For example, a
157 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
160 /// @param form - The form of the instruction.
161 /// @return - true if the form implies that a ModR/M byte is required, false
163 static bool needsModRMForDecode(uint8_t form) {
164 return (form == X86Local::MRMDestReg ||
165 form == X86Local::MRMDestMem ||
166 form == X86Local::MRMSrcReg ||
167 form == X86Local::MRMSrcMem ||
168 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
169 (form >= X86Local::MRM0m && form <= X86Local::MRM7m));
172 /// isRegFormat - Indicates whether a particular form requires the Mod field of
173 /// the ModR/M byte to be 0b11.
175 /// @param form - The form of the instruction.
176 /// @return - true if the form implies that Mod must be 0b11, false
178 static bool isRegFormat(uint8_t form) {
179 return (form == X86Local::MRMDestReg ||
180 form == X86Local::MRMSrcReg ||
181 (form >= X86Local::MRM0r && form <= X86Local::MRM7r));
184 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
185 /// Useful for switch statements and the like.
187 /// @param init - A reference to the BitsInit to be decoded.
188 /// @return - The field, with the first bit in the BitsInit as the lowest
190 static uint8_t byteFromBitsInit(BitsInit &init) {
191 int width = init.getNumBits();
193 assert(width <= 8 && "Field is too large for uint8_t!");
200 for (index = 0; index < width; index++) {
201 if (static_cast<BitInit*>(init.getBit(index))->getValue())
210 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
211 /// name of the field.
213 /// @param rec - The record from which to extract the value.
214 /// @param name - The name of the field in the record.
215 /// @return - The field, as translated by byteFromBitsInit().
216 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
217 BitsInit* bits = rec->getValueAsBitsInit(name);
218 return byteFromBitsInit(*bits);
221 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
222 const CodeGenInstruction &insn,
227 Name = Rec->getName();
228 Spec = &tables.specForUID(UID);
230 if (!Rec->isSubClassOf("X86Inst")) {
231 ShouldBeEmitted = false;
235 OpPrefix = byteFromRec(Rec->getValueAsDef("OpPrefix"), "Value");
236 OpMap = byteFromRec(Rec->getValueAsDef("OpMap"), "Value");
237 Opcode = byteFromRec(Rec, "Opcode");
238 Form = byteFromRec(Rec, "FormBits");
239 Encoding = byteFromRec(Rec->getValueAsDef("OpEnc"), "Value");
241 OpSize = byteFromRec(Rec->getValueAsDef("OpSize"), "Value");
242 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
243 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
244 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
245 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
246 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
247 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
248 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
249 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
250 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
251 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
252 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
253 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
254 HasREPPrefix = Rec->getValueAsBit("hasREPPrefix");
255 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
256 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
258 Name = Rec->getName();
259 AsmString = Rec->getValueAsString("AsmString");
261 Operands = &insn.Operands.OperandList;
263 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
265 // Check for 64-bit inst which does not require REX
268 // FIXME: Is there some better way to check for In64BitMode?
269 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
270 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
271 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
272 Predicates[i]->getName().find("In32Bit") != Name.npos) {
276 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
282 ShouldBeEmitted = true;
285 void RecognizableInstr::processInstr(DisassemblerTables &tables,
286 const CodeGenInstruction &insn,
289 // Ignore "asm parser only" instructions.
290 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
293 RecognizableInstr recogInstr(tables, insn, uid);
295 recogInstr.emitInstructionSpecifier();
297 if (recogInstr.shouldBeEmitted())
298 recogInstr.emitDecodePath(tables);
301 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
302 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
303 (HasEVEX_KZ ? n##_KZ : \
304 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
306 InstructionContext RecognizableInstr::insnContext() const {
307 InstructionContext insnContext;
309 if (Encoding == X86Local::EVEX) {
310 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
311 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
312 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
315 if (HasVEX_LPrefix && HasVEX_WPrefix) {
316 if (OpPrefix == X86Local::PD)
317 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
318 else if (OpPrefix == X86Local::XS)
319 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
320 else if (OpPrefix == X86Local::XD)
321 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
323 insnContext = EVEX_KB(IC_EVEX_L_W);
324 } else if (HasVEX_LPrefix) {
326 if (OpPrefix == X86Local::PD)
327 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
328 else if (OpPrefix == X86Local::XS)
329 insnContext = EVEX_KB(IC_EVEX_L_XS);
330 else if (OpPrefix == X86Local::XD)
331 insnContext = EVEX_KB(IC_EVEX_L_XD);
333 insnContext = EVEX_KB(IC_EVEX_L);
335 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
337 if (OpPrefix == X86Local::PD)
338 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
339 else if (OpPrefix == X86Local::XS)
340 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
341 else if (OpPrefix == X86Local::XD)
342 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
344 insnContext = EVEX_KB(IC_EVEX_L2_W);
345 } else if (HasEVEX_L2Prefix) {
347 if (OpPrefix == X86Local::PD)
348 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
349 else if (OpPrefix == X86Local::XD)
350 insnContext = EVEX_KB(IC_EVEX_L2_XD);
351 else if (OpPrefix == X86Local::XS)
352 insnContext = EVEX_KB(IC_EVEX_L2_XS);
354 insnContext = EVEX_KB(IC_EVEX_L2);
356 else if (HasVEX_WPrefix) {
358 if (OpPrefix == X86Local::PD)
359 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
360 else if (OpPrefix == X86Local::XS)
361 insnContext = EVEX_KB(IC_EVEX_W_XS);
362 else if (OpPrefix == X86Local::XD)
363 insnContext = EVEX_KB(IC_EVEX_W_XD);
365 insnContext = EVEX_KB(IC_EVEX_W);
368 else if (OpPrefix == X86Local::PD)
369 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
370 else if (OpPrefix == X86Local::XD)
371 insnContext = EVEX_KB(IC_EVEX_XD);
372 else if (OpPrefix == X86Local::XS)
373 insnContext = EVEX_KB(IC_EVEX_XS);
375 insnContext = EVEX_KB(IC_EVEX);
377 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
378 if (HasVEX_LPrefix && HasVEX_WPrefix) {
379 if (OpPrefix == X86Local::PD)
380 insnContext = IC_VEX_L_W_OPSIZE;
381 else if (OpPrefix == X86Local::XS)
382 insnContext = IC_VEX_L_W_XS;
383 else if (OpPrefix == X86Local::XD)
384 insnContext = IC_VEX_L_W_XD;
386 insnContext = IC_VEX_L_W;
387 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
388 insnContext = IC_VEX_L_OPSIZE;
389 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix)
390 insnContext = IC_VEX_W_OPSIZE;
391 else if (OpPrefix == X86Local::PD)
392 insnContext = IC_VEX_OPSIZE;
393 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
394 insnContext = IC_VEX_L_XS;
395 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
396 insnContext = IC_VEX_L_XD;
397 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS)
398 insnContext = IC_VEX_W_XS;
399 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD)
400 insnContext = IC_VEX_W_XD;
401 else if (HasVEX_WPrefix)
402 insnContext = IC_VEX_W;
403 else if (HasVEX_LPrefix)
404 insnContext = IC_VEX_L;
405 else if (OpPrefix == X86Local::XD)
406 insnContext = IC_VEX_XD;
407 else if (OpPrefix == X86Local::XS)
408 insnContext = IC_VEX_XS;
410 insnContext = IC_VEX;
411 } else if (Is64Bit || HasREX_WPrefix) {
412 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
413 insnContext = IC_64BIT_REXW_OPSIZE;
414 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
415 insnContext = IC_64BIT_XD_OPSIZE;
416 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
417 insnContext = IC_64BIT_XS_OPSIZE;
418 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
419 insnContext = IC_64BIT_OPSIZE;
420 else if (HasAdSizePrefix)
421 insnContext = IC_64BIT_ADSIZE;
422 else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
423 insnContext = IC_64BIT_REXW_XS;
424 else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
425 insnContext = IC_64BIT_REXW_XD;
426 else if (OpPrefix == X86Local::XD)
427 insnContext = IC_64BIT_XD;
428 else if (OpPrefix == X86Local::XS)
429 insnContext = IC_64BIT_XS;
430 else if (HasREX_WPrefix)
431 insnContext = IC_64BIT_REXW;
433 insnContext = IC_64BIT;
435 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
436 insnContext = IC_XD_OPSIZE;
437 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
438 insnContext = IC_XS_OPSIZE;
439 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
440 insnContext = IC_OPSIZE;
441 else if (HasAdSizePrefix)
442 insnContext = IC_ADSIZE;
443 else if (OpPrefix == X86Local::XD)
445 else if (OpPrefix == X86Local::XS || HasREPPrefix)
454 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
459 // Filter out intrinsics
461 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
463 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
464 return FILTER_STRONG;
467 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
468 // printed as a separate "instruction".
476 // Filter out instructions with a LOCK prefix;
477 // prefer forms that do not have the prefix
483 if (Name == "VMASKMOVDQU64")
486 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
487 // For now, just prefer the REP versions.
488 if (Name == "XACQUIRE_PREFIX" ||
489 Name == "XRELEASE_PREFIX")
492 return FILTER_NORMAL;
495 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
496 unsigned &physicalOperandIndex,
497 unsigned &numPhysicalOperands,
498 const unsigned *operandMapping,
499 OperandEncoding (*encodingFromString)
503 if (physicalOperandIndex >= numPhysicalOperands)
506 assert(physicalOperandIndex < numPhysicalOperands);
509 while (operandMapping[operandIndex] != operandIndex) {
510 Spec->operands[operandIndex].encoding = ENCODING_DUP;
511 Spec->operands[operandIndex].type =
512 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
516 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
518 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
520 Spec->operands[operandIndex].type = typeFromString(typeName,
521 HasREX_WPrefix, OpSize);
524 ++physicalOperandIndex;
527 void RecognizableInstr::emitInstructionSpecifier() {
530 if (!ShouldBeEmitted)
535 Spec->filtered = true;
538 ShouldBeEmitted = false;
544 Spec->insnContext = insnContext();
546 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
548 unsigned numOperands = OperandList.size();
549 unsigned numPhysicalOperands = 0;
551 // operandMapping maps from operands in OperandList to their originals.
552 // If operandMapping[i] != i, then the entry is a duplicate.
553 unsigned operandMapping[X86_MAX_OPERANDS];
554 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
556 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
557 if (OperandList[operandIndex].Constraints.size()) {
558 const CGIOperandList::ConstraintInfo &Constraint =
559 OperandList[operandIndex].Constraints[0];
560 if (Constraint.isTied()) {
561 operandMapping[operandIndex] = operandIndex;
562 operandMapping[Constraint.getTiedOperand()] = operandIndex;
564 ++numPhysicalOperands;
565 operandMapping[operandIndex] = operandIndex;
568 ++numPhysicalOperands;
569 operandMapping[operandIndex] = operandIndex;
573 #define HANDLE_OPERAND(class) \
574 handleOperand(false, \
576 physicalOperandIndex, \
577 numPhysicalOperands, \
579 class##EncodingFromString);
581 #define HANDLE_OPTIONAL(class) \
582 handleOperand(true, \
584 physicalOperandIndex, \
585 numPhysicalOperands, \
587 class##EncodingFromString);
589 // operandIndex should always be < numOperands
590 unsigned operandIndex = 0;
591 // physicalOperandIndex should always be < numPhysicalOperands
592 unsigned physicalOperandIndex = 0;
595 default: llvm_unreachable("Unhandled form");
596 case X86Local::RawFrmSrc:
597 HANDLE_OPERAND(relocation);
599 case X86Local::RawFrmDst:
600 HANDLE_OPERAND(relocation);
602 case X86Local::RawFrmDstSrc:
603 HANDLE_OPERAND(relocation);
604 HANDLE_OPERAND(relocation);
606 case X86Local::RawFrm:
607 // Operand 1 (optional) is an address or immediate.
608 // Operand 2 (optional) is an immediate.
609 assert(numPhysicalOperands <= 2 &&
610 "Unexpected number of operands for RawFrm");
611 HANDLE_OPTIONAL(relocation)
612 HANDLE_OPTIONAL(immediate)
614 case X86Local::RawFrmMemOffs:
615 // Operand 1 is an address.
616 HANDLE_OPERAND(relocation);
618 case X86Local::AddRegFrm:
619 // Operand 1 is added to the opcode.
620 // Operand 2 (optional) is an address.
621 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
622 "Unexpected number of operands for AddRegFrm");
623 HANDLE_OPERAND(opcodeModifier)
624 HANDLE_OPTIONAL(relocation)
626 case X86Local::MRMDestReg:
627 // Operand 1 is a register operand in the R/M field.
628 // Operand 2 is a register operand in the Reg/Opcode field.
629 // - In AVX, there is a register operand in the VEX.vvvv field here -
630 // Operand 3 (optional) is an immediate.
632 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
633 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
635 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
636 "Unexpected number of operands for MRMDestRegFrm");
638 HANDLE_OPERAND(rmRegister)
641 // FIXME: In AVX, the register below becomes the one encoded
642 // in ModRMVEX and the one above the one in the VEX.VVVV field
643 HANDLE_OPERAND(vvvvRegister)
645 HANDLE_OPERAND(roRegister)
646 HANDLE_OPTIONAL(immediate)
648 case X86Local::MRMDestMem:
649 // Operand 1 is a memory operand (possibly SIB-extended)
650 // Operand 2 is a register operand in the Reg/Opcode field.
651 // - In AVX, there is a register operand in the VEX.vvvv field here -
652 // Operand 3 (optional) is an immediate.
654 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
655 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
657 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
658 "Unexpected number of operands for MRMDestMemFrm");
659 HANDLE_OPERAND(memory)
662 HANDLE_OPERAND(writemaskRegister)
665 // FIXME: In AVX, the register below becomes the one encoded
666 // in ModRMVEX and the one above the one in the VEX.VVVV field
667 HANDLE_OPERAND(vvvvRegister)
669 HANDLE_OPERAND(roRegister)
670 HANDLE_OPTIONAL(immediate)
672 case X86Local::MRMSrcReg:
673 // Operand 1 is a register operand in the Reg/Opcode field.
674 // Operand 2 is a register operand in the R/M field.
675 // - In AVX, there is a register operand in the VEX.vvvv field here -
676 // Operand 3 (optional) is an immediate.
677 // Operand 4 (optional) is an immediate.
679 if (HasVEX_4V || HasVEX_4VOp3)
680 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
681 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
683 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
684 "Unexpected number of operands for MRMSrcRegFrm");
686 HANDLE_OPERAND(roRegister)
689 HANDLE_OPERAND(writemaskRegister)
692 // FIXME: In AVX, the register below becomes the one encoded
693 // in ModRMVEX and the one above the one in the VEX.VVVV field
694 HANDLE_OPERAND(vvvvRegister)
697 HANDLE_OPERAND(immediate)
699 HANDLE_OPERAND(rmRegister)
702 HANDLE_OPERAND(vvvvRegister)
704 if (!HasMemOp4Prefix)
705 HANDLE_OPTIONAL(immediate)
706 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
707 HANDLE_OPTIONAL(immediate)
709 case X86Local::MRMSrcMem:
710 // Operand 1 is a register operand in the Reg/Opcode field.
711 // Operand 2 is a memory operand (possibly SIB-extended)
712 // - In AVX, there is a register operand in the VEX.vvvv field here -
713 // Operand 3 (optional) is an immediate.
715 if (HasVEX_4V || HasVEX_4VOp3)
716 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
717 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
719 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
720 "Unexpected number of operands for MRMSrcMemFrm");
722 HANDLE_OPERAND(roRegister)
725 HANDLE_OPERAND(writemaskRegister)
728 // FIXME: In AVX, the register below becomes the one encoded
729 // in ModRMVEX and the one above the one in the VEX.VVVV field
730 HANDLE_OPERAND(vvvvRegister)
733 HANDLE_OPERAND(immediate)
735 HANDLE_OPERAND(memory)
738 HANDLE_OPERAND(vvvvRegister)
740 if (!HasMemOp4Prefix)
741 HANDLE_OPTIONAL(immediate)
742 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
744 case X86Local::MRM0r:
745 case X86Local::MRM1r:
746 case X86Local::MRM2r:
747 case X86Local::MRM3r:
748 case X86Local::MRM4r:
749 case X86Local::MRM5r:
750 case X86Local::MRM6r:
751 case X86Local::MRM7r:
753 // Operand 1 is a register operand in the R/M field.
754 // Operand 2 (optional) is an immediate or relocation.
755 // Operand 3 (optional) is an immediate.
756 unsigned kOp = (HasEVEX_K) ? 1:0;
757 unsigned Op4v = (HasVEX_4V) ? 1:0;
758 if (numPhysicalOperands > 3 + kOp + Op4v)
759 llvm_unreachable("Unexpected number of operands for MRMnr");
762 HANDLE_OPERAND(vvvvRegister)
765 HANDLE_OPERAND(writemaskRegister)
766 HANDLE_OPTIONAL(rmRegister)
767 HANDLE_OPTIONAL(relocation)
768 HANDLE_OPTIONAL(immediate)
770 case X86Local::MRM0m:
771 case X86Local::MRM1m:
772 case X86Local::MRM2m:
773 case X86Local::MRM3m:
774 case X86Local::MRM4m:
775 case X86Local::MRM5m:
776 case X86Local::MRM6m:
777 case X86Local::MRM7m:
779 // Operand 1 is a memory operand (possibly SIB-extended)
780 // Operand 2 (optional) is an immediate or relocation.
781 unsigned kOp = (HasEVEX_K) ? 1:0;
782 unsigned Op4v = (HasVEX_4V) ? 1:0;
783 if (numPhysicalOperands < 1 + kOp + Op4v ||
784 numPhysicalOperands > 2 + kOp + Op4v)
785 llvm_unreachable("Unexpected number of operands for MRMnm");
788 HANDLE_OPERAND(vvvvRegister)
790 HANDLE_OPERAND(writemaskRegister)
791 HANDLE_OPERAND(memory)
792 HANDLE_OPTIONAL(relocation)
794 case X86Local::RawFrmImm8:
795 // operand 1 is a 16-bit immediate
796 // operand 2 is an 8-bit immediate
797 assert(numPhysicalOperands == 2 &&
798 "Unexpected number of operands for X86Local::RawFrmImm8");
799 HANDLE_OPERAND(immediate)
800 HANDLE_OPERAND(immediate)
802 case X86Local::RawFrmImm16:
803 // operand 1 is a 16-bit immediate
804 // operand 2 is a 16-bit immediate
805 HANDLE_OPERAND(immediate)
806 HANDLE_OPERAND(immediate)
808 case X86Local::MRM_F8:
809 if (Opcode == 0xc6) {
810 assert(numPhysicalOperands == 1 &&
811 "Unexpected number of operands for X86Local::MRM_F8");
812 HANDLE_OPERAND(immediate)
813 } else if (Opcode == 0xc7) {
814 assert(numPhysicalOperands == 1 &&
815 "Unexpected number of operands for X86Local::MRM_F8");
816 HANDLE_OPERAND(relocation)
819 case X86Local::MRM_C1:
820 case X86Local::MRM_C2:
821 case X86Local::MRM_C3:
822 case X86Local::MRM_C4:
823 case X86Local::MRM_C8:
824 case X86Local::MRM_C9:
825 case X86Local::MRM_CA:
826 case X86Local::MRM_CB:
827 case X86Local::MRM_E8:
828 case X86Local::MRM_F0:
829 case X86Local::MRM_F9:
830 case X86Local::MRM_D0:
831 case X86Local::MRM_D1:
832 case X86Local::MRM_D4:
833 case X86Local::MRM_D5:
834 case X86Local::MRM_D6:
835 case X86Local::MRM_D8:
836 case X86Local::MRM_D9:
837 case X86Local::MRM_DA:
838 case X86Local::MRM_DB:
839 case X86Local::MRM_DC:
840 case X86Local::MRM_DD:
841 case X86Local::MRM_DE:
842 case X86Local::MRM_DF:
847 #undef HANDLE_OPERAND
848 #undef HANDLE_OPTIONAL
851 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
852 // Special cases where the LLVM tables are not complete
854 #define MAP(from, to) \
855 case X86Local::MRM_##from: \
856 filter = new ExactFilter(0x##from); \
859 OpcodeType opcodeType = (OpcodeType)-1;
861 ModRMFilter* filter = NULL;
862 uint8_t opcodeToSet = 0;
865 default: llvm_unreachable("Invalid map!");
866 // Extended two-byte opcodes can start with 66 0f, f2 0f, f3 0f, or 0f
868 opcodeType = TWOBYTE;
872 if (needsModRMForDecode(Form))
873 filter = new ModFilter(isRegFormat(Form));
875 filter = new DumbFilter();
877 #define EXTENSION_TABLE(n) case 0x##n:
878 TWO_BYTE_EXTENSION_TABLES
879 #undef EXTENSION_TABLE
882 llvm_unreachable("Unhandled two-byte extended opcode");
883 case X86Local::MRM0r:
884 case X86Local::MRM1r:
885 case X86Local::MRM2r:
886 case X86Local::MRM3r:
887 case X86Local::MRM4r:
888 case X86Local::MRM5r:
889 case X86Local::MRM6r:
890 case X86Local::MRM7r:
891 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
893 case X86Local::MRM0m:
894 case X86Local::MRM1m:
895 case X86Local::MRM2m:
896 case X86Local::MRM3m:
897 case X86Local::MRM4m:
898 case X86Local::MRM5m:
899 case X86Local::MRM6m:
900 case X86Local::MRM7m:
901 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
907 opcodeToSet = Opcode;
910 opcodeType = THREEBYTE_38;
913 if (needsModRMForDecode(Form))
914 filter = new ModFilter(isRegFormat(Form));
916 filter = new DumbFilter();
918 #define EXTENSION_TABLE(n) case 0x##n:
919 THREE_BYTE_38_EXTENSION_TABLES
920 #undef EXTENSION_TABLE
923 llvm_unreachable("Unhandled two-byte extended opcode");
924 case X86Local::MRM0r:
925 case X86Local::MRM1r:
926 case X86Local::MRM2r:
927 case X86Local::MRM3r:
928 case X86Local::MRM4r:
929 case X86Local::MRM5r:
930 case X86Local::MRM6r:
931 case X86Local::MRM7r:
932 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
934 case X86Local::MRM0m:
935 case X86Local::MRM1m:
936 case X86Local::MRM2m:
937 case X86Local::MRM3m:
938 case X86Local::MRM4m:
939 case X86Local::MRM5m:
940 case X86Local::MRM6m:
941 case X86Local::MRM7m:
942 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
948 opcodeToSet = Opcode;
951 opcodeType = THREEBYTE_3A;
952 if (needsModRMForDecode(Form))
953 filter = new ModFilter(isRegFormat(Form));
955 filter = new DumbFilter();
956 opcodeToSet = Opcode;
959 opcodeType = THREEBYTE_A6;
960 if (needsModRMForDecode(Form))
961 filter = new ModFilter(isRegFormat(Form));
963 filter = new DumbFilter();
964 opcodeToSet = Opcode;
967 opcodeType = THREEBYTE_A7;
968 if (needsModRMForDecode(Form))
969 filter = new ModFilter(isRegFormat(Form));
971 filter = new DumbFilter();
972 opcodeToSet = Opcode;
975 opcodeType = XOP8_MAP;
976 if (needsModRMForDecode(Form))
977 filter = new ModFilter(isRegFormat(Form));
979 filter = new DumbFilter();
980 opcodeToSet = Opcode;
983 opcodeType = XOP9_MAP;
986 if (needsModRMForDecode(Form))
987 filter = new ModFilter(isRegFormat(Form));
989 filter = new DumbFilter();
991 #define EXTENSION_TABLE(n) case 0x##n:
992 XOP9_MAP_EXTENSION_TABLES
993 #undef EXTENSION_TABLE
996 llvm_unreachable("Unhandled XOP9 extended opcode");
997 case X86Local::MRM0r:
998 case X86Local::MRM1r:
999 case X86Local::MRM2r:
1000 case X86Local::MRM3r:
1001 case X86Local::MRM4r:
1002 case X86Local::MRM5r:
1003 case X86Local::MRM6r:
1004 case X86Local::MRM7r:
1005 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1007 case X86Local::MRM0m:
1008 case X86Local::MRM1m:
1009 case X86Local::MRM2m:
1010 case X86Local::MRM3m:
1011 case X86Local::MRM4m:
1012 case X86Local::MRM5m:
1013 case X86Local::MRM6m:
1014 case X86Local::MRM7m:
1015 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1020 } // switch (Opcode)
1021 opcodeToSet = Opcode;
1023 case X86Local::XOPA:
1024 opcodeType = XOPA_MAP;
1025 if (needsModRMForDecode(Form))
1026 filter = new ModFilter(isRegFormat(Form));
1028 filter = new DumbFilter();
1029 opcodeToSet = Opcode;
1039 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1040 assert(Form == X86Local::RawFrm);
1041 opcodeType = ONEBYTE;
1042 filter = new ExactFilter(Opcode);
1043 opcodeToSet = 0xd8 + (OpMap - X86Local::D8);
1046 opcodeType = ONEBYTE;
1048 #define EXTENSION_TABLE(n) case 0x##n:
1049 ONE_BYTE_EXTENSION_TABLES
1050 #undef EXTENSION_TABLE
1053 llvm_unreachable("Fell through the cracks of a single-byte "
1055 case X86Local::MRM0r:
1056 case X86Local::MRM1r:
1057 case X86Local::MRM2r:
1058 case X86Local::MRM3r:
1059 case X86Local::MRM4r:
1060 case X86Local::MRM5r:
1061 case X86Local::MRM6r:
1062 case X86Local::MRM7r:
1063 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1065 case X86Local::MRM0m:
1066 case X86Local::MRM1m:
1067 case X86Local::MRM2m:
1068 case X86Local::MRM3m:
1069 case X86Local::MRM4m:
1070 case X86Local::MRM5m:
1071 case X86Local::MRM6m:
1072 case X86Local::MRM7m:
1073 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1088 llvm_unreachable("Unhandled escape opcode form");
1089 case X86Local::MRM0r:
1090 case X86Local::MRM1r:
1091 case X86Local::MRM2r:
1092 case X86Local::MRM3r:
1093 case X86Local::MRM4r:
1094 case X86Local::MRM5r:
1095 case X86Local::MRM6r:
1096 case X86Local::MRM7r:
1097 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1099 case X86Local::MRM0m:
1100 case X86Local::MRM1m:
1101 case X86Local::MRM2m:
1102 case X86Local::MRM3m:
1103 case X86Local::MRM4m:
1104 case X86Local::MRM5m:
1105 case X86Local::MRM6m:
1106 case X86Local::MRM7m:
1107 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1112 if (needsModRMForDecode(Form))
1113 filter = new ModFilter(isRegFormat(Form));
1115 filter = new DumbFilter();
1117 } // switch (Opcode)
1118 opcodeToSet = Opcode;
1121 assert(opcodeType != (OpcodeType)-1 &&
1122 "Opcode type not set");
1123 assert(filter && "Filter not set");
1125 if (Form == X86Local::AddRegFrm) {
1126 assert(((opcodeToSet & 7) == 0) &&
1127 "ADDREG_FRM opcode not aligned");
1129 uint8_t currentOpcode;
1131 for (currentOpcode = opcodeToSet;
1132 currentOpcode < opcodeToSet + 8;
1134 tables.setTableFields(opcodeType,
1138 UID, Is32Bit, IgnoresVEX_L);
1140 tables.setTableFields(opcodeType,
1144 UID, Is32Bit, IgnoresVEX_L);
1152 #define TYPE(str, type) if (s == str) return type;
1153 OperandType RecognizableInstr::typeFromString(const std::string &s,
1154 bool hasREX_WPrefix,
1156 if(hasREX_WPrefix) {
1157 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1159 TYPE("GR32", TYPE_R32)
1161 if(OpSize == X86Local::OpSize16) {
1162 // For OpSize16 instructions, a declared 16-bit register or
1163 // immediate encoding is special.
1164 TYPE("GR16", TYPE_Rv)
1165 TYPE("i16imm", TYPE_IMMv)
1166 } else if(OpSize == X86Local::OpSize32) {
1167 // For OpSize32 instructions, a declared 32-bit register or
1168 // immediate encoding is special.
1169 TYPE("GR32", TYPE_Rv)
1171 TYPE("i16mem", TYPE_Mv)
1172 TYPE("i16imm", TYPE_IMM16)
1173 TYPE("i16i8imm", TYPE_IMMv)
1174 TYPE("GR16", TYPE_R16)
1175 TYPE("i32mem", TYPE_Mv)
1176 TYPE("i32imm", TYPE_IMMv)
1177 TYPE("i32i8imm", TYPE_IMM32)
1178 TYPE("u32u8imm", TYPE_IMM32)
1179 TYPE("GR32", TYPE_R32)
1180 TYPE("GR32orGR64", TYPE_R32)
1181 TYPE("i64mem", TYPE_Mv)
1182 TYPE("i64i32imm", TYPE_IMM64)
1183 TYPE("i64i8imm", TYPE_IMM64)
1184 TYPE("GR64", TYPE_R64)
1185 TYPE("i8mem", TYPE_M8)
1186 TYPE("i8imm", TYPE_IMM8)
1187 TYPE("GR8", TYPE_R8)
1188 TYPE("VR128", TYPE_XMM128)
1189 TYPE("VR128X", TYPE_XMM128)
1190 TYPE("f128mem", TYPE_M128)
1191 TYPE("f256mem", TYPE_M256)
1192 TYPE("f512mem", TYPE_M512)
1193 TYPE("FR64", TYPE_XMM64)
1194 TYPE("FR64X", TYPE_XMM64)
1195 TYPE("f64mem", TYPE_M64FP)
1196 TYPE("sdmem", TYPE_M64FP)
1197 TYPE("FR32", TYPE_XMM32)
1198 TYPE("FR32X", TYPE_XMM32)
1199 TYPE("f32mem", TYPE_M32FP)
1200 TYPE("ssmem", TYPE_M32FP)
1201 TYPE("RST", TYPE_ST)
1202 TYPE("i128mem", TYPE_M128)
1203 TYPE("i256mem", TYPE_M256)
1204 TYPE("i512mem", TYPE_M512)
1205 TYPE("i64i32imm_pcrel", TYPE_REL64)
1206 TYPE("i16imm_pcrel", TYPE_REL16)
1207 TYPE("i32imm_pcrel", TYPE_REL32)
1208 TYPE("SSECC", TYPE_IMM3)
1209 TYPE("AVXCC", TYPE_IMM5)
1210 TYPE("AVX512RC", TYPE_IMM32)
1211 TYPE("brtarget", TYPE_RELv)
1212 TYPE("uncondbrtarget", TYPE_RELv)
1213 TYPE("brtarget8", TYPE_REL8)
1214 TYPE("f80mem", TYPE_M80FP)
1215 TYPE("lea32mem", TYPE_LEA)
1216 TYPE("lea64_32mem", TYPE_LEA)
1217 TYPE("lea64mem", TYPE_LEA)
1218 TYPE("VR64", TYPE_MM64)
1219 TYPE("i64imm", TYPE_IMMv)
1220 TYPE("opaque32mem", TYPE_M1616)
1221 TYPE("opaque48mem", TYPE_M1632)
1222 TYPE("opaque80mem", TYPE_M1664)
1223 TYPE("opaque512mem", TYPE_M512)
1224 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1225 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1226 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1227 TYPE("srcidx8", TYPE_SRCIDX8)
1228 TYPE("srcidx16", TYPE_SRCIDX16)
1229 TYPE("srcidx32", TYPE_SRCIDX32)
1230 TYPE("srcidx64", TYPE_SRCIDX64)
1231 TYPE("dstidx8", TYPE_DSTIDX8)
1232 TYPE("dstidx16", TYPE_DSTIDX16)
1233 TYPE("dstidx32", TYPE_DSTIDX32)
1234 TYPE("dstidx64", TYPE_DSTIDX64)
1235 TYPE("offset8", TYPE_MOFFS8)
1236 TYPE("offset16", TYPE_MOFFS16)
1237 TYPE("offset32", TYPE_MOFFS32)
1238 TYPE("offset64", TYPE_MOFFS64)
1239 TYPE("VR256", TYPE_XMM256)
1240 TYPE("VR256X", TYPE_XMM256)
1241 TYPE("VR512", TYPE_XMM512)
1242 TYPE("VK1", TYPE_VK1)
1243 TYPE("VK1WM", TYPE_VK1)
1244 TYPE("VK8", TYPE_VK8)
1245 TYPE("VK8WM", TYPE_VK8)
1246 TYPE("VK16", TYPE_VK16)
1247 TYPE("VK16WM", TYPE_VK16)
1248 TYPE("GR16_NOAX", TYPE_Rv)
1249 TYPE("GR32_NOAX", TYPE_Rv)
1250 TYPE("GR64_NOAX", TYPE_R64)
1251 TYPE("vx32mem", TYPE_M32)
1252 TYPE("vy32mem", TYPE_M32)
1253 TYPE("vz32mem", TYPE_M32)
1254 TYPE("vx64mem", TYPE_M64)
1255 TYPE("vy64mem", TYPE_M64)
1256 TYPE("vy64xmem", TYPE_M64)
1257 TYPE("vz64mem", TYPE_M64)
1258 errs() << "Unhandled type string " << s << "\n";
1259 llvm_unreachable("Unhandled type string");
1263 #define ENCODING(str, encoding) if (s == str) return encoding;
1265 RecognizableInstr::immediateEncodingFromString(const std::string &s,
1267 if(OpSize != X86Local::OpSize16) {
1268 // For instructions without an OpSize prefix, a declared 16-bit register or
1269 // immediate encoding is special.
1270 ENCODING("i16imm", ENCODING_IW)
1272 ENCODING("i32i8imm", ENCODING_IB)
1273 ENCODING("u32u8imm", ENCODING_IB)
1274 ENCODING("SSECC", ENCODING_IB)
1275 ENCODING("AVXCC", ENCODING_IB)
1276 ENCODING("AVX512RC", ENCODING_IB)
1277 ENCODING("i16imm", ENCODING_Iv)
1278 ENCODING("i16i8imm", ENCODING_IB)
1279 ENCODING("i32imm", ENCODING_Iv)
1280 ENCODING("i64i32imm", ENCODING_ID)
1281 ENCODING("i64i8imm", ENCODING_IB)
1282 ENCODING("i8imm", ENCODING_IB)
1283 // This is not a typo. Instructions like BLENDVPD put
1284 // register IDs in 8-bit immediates nowadays.
1285 ENCODING("FR32", ENCODING_IB)
1286 ENCODING("FR64", ENCODING_IB)
1287 ENCODING("VR128", ENCODING_IB)
1288 ENCODING("VR256", ENCODING_IB)
1289 ENCODING("FR32X", ENCODING_IB)
1290 ENCODING("FR64X", ENCODING_IB)
1291 ENCODING("VR128X", ENCODING_IB)
1292 ENCODING("VR256X", ENCODING_IB)
1293 ENCODING("VR512", ENCODING_IB)
1294 errs() << "Unhandled immediate encoding " << s << "\n";
1295 llvm_unreachable("Unhandled immediate encoding");
1299 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1301 ENCODING("RST", ENCODING_FP)
1302 ENCODING("GR16", ENCODING_RM)
1303 ENCODING("GR32", ENCODING_RM)
1304 ENCODING("GR32orGR64", ENCODING_RM)
1305 ENCODING("GR64", ENCODING_RM)
1306 ENCODING("GR8", ENCODING_RM)
1307 ENCODING("VR128", ENCODING_RM)
1308 ENCODING("VR128X", ENCODING_RM)
1309 ENCODING("FR64", ENCODING_RM)
1310 ENCODING("FR32", ENCODING_RM)
1311 ENCODING("FR64X", ENCODING_RM)
1312 ENCODING("FR32X", ENCODING_RM)
1313 ENCODING("VR64", ENCODING_RM)
1314 ENCODING("VR256", ENCODING_RM)
1315 ENCODING("VR256X", ENCODING_RM)
1316 ENCODING("VR512", ENCODING_RM)
1317 ENCODING("VK1", ENCODING_RM)
1318 ENCODING("VK8", ENCODING_RM)
1319 ENCODING("VK16", ENCODING_RM)
1320 errs() << "Unhandled R/M register encoding " << s << "\n";
1321 llvm_unreachable("Unhandled R/M register encoding");
1325 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1327 ENCODING("GR16", ENCODING_REG)
1328 ENCODING("GR32", ENCODING_REG)
1329 ENCODING("GR32orGR64", ENCODING_REG)
1330 ENCODING("GR64", ENCODING_REG)
1331 ENCODING("GR8", ENCODING_REG)
1332 ENCODING("VR128", ENCODING_REG)
1333 ENCODING("FR64", ENCODING_REG)
1334 ENCODING("FR32", ENCODING_REG)
1335 ENCODING("VR64", ENCODING_REG)
1336 ENCODING("SEGMENT_REG", ENCODING_REG)
1337 ENCODING("DEBUG_REG", ENCODING_REG)
1338 ENCODING("CONTROL_REG", ENCODING_REG)
1339 ENCODING("VR256", ENCODING_REG)
1340 ENCODING("VR256X", ENCODING_REG)
1341 ENCODING("VR128X", ENCODING_REG)
1342 ENCODING("FR64X", ENCODING_REG)
1343 ENCODING("FR32X", ENCODING_REG)
1344 ENCODING("VR512", ENCODING_REG)
1345 ENCODING("VK1", ENCODING_REG)
1346 ENCODING("VK8", ENCODING_REG)
1347 ENCODING("VK16", ENCODING_REG)
1348 ENCODING("VK1WM", ENCODING_REG)
1349 ENCODING("VK8WM", ENCODING_REG)
1350 ENCODING("VK16WM", ENCODING_REG)
1351 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1352 llvm_unreachable("Unhandled reg/opcode register encoding");
1356 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1358 ENCODING("GR32", ENCODING_VVVV)
1359 ENCODING("GR64", ENCODING_VVVV)
1360 ENCODING("FR32", ENCODING_VVVV)
1361 ENCODING("FR64", ENCODING_VVVV)
1362 ENCODING("VR128", ENCODING_VVVV)
1363 ENCODING("VR256", ENCODING_VVVV)
1364 ENCODING("FR32X", ENCODING_VVVV)
1365 ENCODING("FR64X", ENCODING_VVVV)
1366 ENCODING("VR128X", ENCODING_VVVV)
1367 ENCODING("VR256X", ENCODING_VVVV)
1368 ENCODING("VR512", ENCODING_VVVV)
1369 ENCODING("VK1", ENCODING_VVVV)
1370 ENCODING("VK8", ENCODING_VVVV)
1371 ENCODING("VK16", ENCODING_VVVV)
1372 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1373 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1377 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1379 ENCODING("VK1WM", ENCODING_WRITEMASK)
1380 ENCODING("VK8WM", ENCODING_WRITEMASK)
1381 ENCODING("VK16WM", ENCODING_WRITEMASK)
1382 errs() << "Unhandled mask register encoding " << s << "\n";
1383 llvm_unreachable("Unhandled mask register encoding");
1387 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1389 ENCODING("i16mem", ENCODING_RM)
1390 ENCODING("i32mem", ENCODING_RM)
1391 ENCODING("i64mem", ENCODING_RM)
1392 ENCODING("i8mem", ENCODING_RM)
1393 ENCODING("ssmem", ENCODING_RM)
1394 ENCODING("sdmem", ENCODING_RM)
1395 ENCODING("f128mem", ENCODING_RM)
1396 ENCODING("f256mem", ENCODING_RM)
1397 ENCODING("f512mem", ENCODING_RM)
1398 ENCODING("f64mem", ENCODING_RM)
1399 ENCODING("f32mem", ENCODING_RM)
1400 ENCODING("i128mem", ENCODING_RM)
1401 ENCODING("i256mem", ENCODING_RM)
1402 ENCODING("i512mem", ENCODING_RM)
1403 ENCODING("f80mem", ENCODING_RM)
1404 ENCODING("lea32mem", ENCODING_RM)
1405 ENCODING("lea64_32mem", ENCODING_RM)
1406 ENCODING("lea64mem", ENCODING_RM)
1407 ENCODING("opaque32mem", ENCODING_RM)
1408 ENCODING("opaque48mem", ENCODING_RM)
1409 ENCODING("opaque80mem", ENCODING_RM)
1410 ENCODING("opaque512mem", ENCODING_RM)
1411 ENCODING("vx32mem", ENCODING_RM)
1412 ENCODING("vy32mem", ENCODING_RM)
1413 ENCODING("vz32mem", ENCODING_RM)
1414 ENCODING("vx64mem", ENCODING_RM)
1415 ENCODING("vy64mem", ENCODING_RM)
1416 ENCODING("vy64xmem", ENCODING_RM)
1417 ENCODING("vz64mem", ENCODING_RM)
1418 errs() << "Unhandled memory encoding " << s << "\n";
1419 llvm_unreachable("Unhandled memory encoding");
1423 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1425 if(OpSize != X86Local::OpSize16) {
1426 // For instructions without an OpSize prefix, a declared 16-bit register or
1427 // immediate encoding is special.
1428 ENCODING("i16imm", ENCODING_IW)
1430 ENCODING("i16imm", ENCODING_Iv)
1431 ENCODING("i16i8imm", ENCODING_IB)
1432 ENCODING("i32imm", ENCODING_Iv)
1433 ENCODING("i32i8imm", ENCODING_IB)
1434 ENCODING("i64i32imm", ENCODING_ID)
1435 ENCODING("i64i8imm", ENCODING_IB)
1436 ENCODING("i8imm", ENCODING_IB)
1437 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1438 ENCODING("i16imm_pcrel", ENCODING_IW)
1439 ENCODING("i32imm_pcrel", ENCODING_ID)
1440 ENCODING("brtarget", ENCODING_Iv)
1441 ENCODING("brtarget8", ENCODING_IB)
1442 ENCODING("i64imm", ENCODING_IO)
1443 ENCODING("offset8", ENCODING_Ia)
1444 ENCODING("offset16", ENCODING_Ia)
1445 ENCODING("offset32", ENCODING_Ia)
1446 ENCODING("offset64", ENCODING_Ia)
1447 ENCODING("srcidx8", ENCODING_SI)
1448 ENCODING("srcidx16", ENCODING_SI)
1449 ENCODING("srcidx32", ENCODING_SI)
1450 ENCODING("srcidx64", ENCODING_SI)
1451 ENCODING("dstidx8", ENCODING_DI)
1452 ENCODING("dstidx16", ENCODING_DI)
1453 ENCODING("dstidx32", ENCODING_DI)
1454 ENCODING("dstidx64", ENCODING_DI)
1455 errs() << "Unhandled relocation encoding " << s << "\n";
1456 llvm_unreachable("Unhandled relocation encoding");
1460 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1462 ENCODING("GR32", ENCODING_Rv)
1463 ENCODING("GR64", ENCODING_RO)
1464 ENCODING("GR16", ENCODING_Rv)
1465 ENCODING("GR8", ENCODING_RB)
1466 ENCODING("GR16_NOAX", ENCODING_Rv)
1467 ENCODING("GR32_NOAX", ENCODING_Rv)
1468 ENCODING("GR64_NOAX", ENCODING_RO)
1469 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1470 llvm_unreachable("Unhandled opcode modifier encoding");