1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
80 // A clone of X86 since we can't depend on something that is generated.
96 MRMXr = 14, MRMXm = 15,
97 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
98 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
99 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
100 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
101 #define MAP(from, to) MRM_##from = to,
108 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6
112 PS = 1, PD = 2, XS = 3, XD = 4
116 VEX = 1, XOP = 2, EVEX = 3
120 OpSize16 = 1, OpSize32 = 2
124 using namespace X86Disassembler;
126 /// isRegFormat - Indicates whether a particular form requires the Mod field of
127 /// the ModR/M byte to be 0b11.
129 /// @param form - The form of the instruction.
130 /// @return - true if the form implies that Mod must be 0b11, false
132 static bool isRegFormat(uint8_t form) {
133 return (form == X86Local::MRMDestReg ||
134 form == X86Local::MRMSrcReg ||
135 form == X86Local::MRMXr ||
136 (form >= X86Local::MRM0r && form <= X86Local::MRM7r));
139 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
140 /// Useful for switch statements and the like.
142 /// @param init - A reference to the BitsInit to be decoded.
143 /// @return - The field, with the first bit in the BitsInit as the lowest
145 static uint8_t byteFromBitsInit(BitsInit &init) {
146 int width = init.getNumBits();
148 assert(width <= 8 && "Field is too large for uint8_t!");
155 for (index = 0; index < width; index++) {
156 if (static_cast<BitInit*>(init.getBit(index))->getValue())
165 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
166 /// name of the field.
168 /// @param rec - The record from which to extract the value.
169 /// @param name - The name of the field in the record.
170 /// @return - The field, as translated by byteFromBitsInit().
171 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
172 BitsInit* bits = rec->getValueAsBitsInit(name);
173 return byteFromBitsInit(*bits);
176 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
177 const CodeGenInstruction &insn,
182 Name = Rec->getName();
183 Spec = &tables.specForUID(UID);
185 if (!Rec->isSubClassOf("X86Inst")) {
186 ShouldBeEmitted = false;
190 OpPrefix = byteFromRec(Rec, "OpPrefixBits");
191 OpMap = byteFromRec(Rec, "OpMapBits");
192 Opcode = byteFromRec(Rec, "Opcode");
193 Form = byteFromRec(Rec, "FormBits");
194 Encoding = byteFromRec(Rec, "OpEncBits");
196 OpSize = byteFromRec(Rec, "OpSizeBits");
197 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
198 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
199 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
200 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
201 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
202 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
203 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
204 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
205 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
206 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
207 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
208 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
209 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
210 CD8_Scale = byteFromRec(Rec, "CD8_Scale");
212 Name = Rec->getName();
213 AsmString = Rec->getValueAsString("AsmString");
215 Operands = &insn.Operands.OperandList;
217 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
219 // Check for 64-bit inst which does not require REX
222 // FIXME: Is there some better way to check for In64BitMode?
223 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
224 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
225 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
226 Predicates[i]->getName().find("In32Bit") != Name.npos) {
230 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
236 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
237 ShouldBeEmitted = false;
241 // Special case since there is no attribute class for 64-bit and VEX
242 if (Name == "VMASKMOVDQU64") {
243 ShouldBeEmitted = false;
247 ShouldBeEmitted = true;
250 void RecognizableInstr::processInstr(DisassemblerTables &tables,
251 const CodeGenInstruction &insn,
254 // Ignore "asm parser only" instructions.
255 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
258 RecognizableInstr recogInstr(tables, insn, uid);
260 if (recogInstr.shouldBeEmitted()) {
261 recogInstr.emitInstructionSpecifier();
262 recogInstr.emitDecodePath(tables);
266 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
267 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
268 (HasEVEX_KZ ? n##_KZ : \
269 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
271 InstructionContext RecognizableInstr::insnContext() const {
272 InstructionContext insnContext;
274 if (Encoding == X86Local::EVEX) {
275 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
276 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
277 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
280 if (HasVEX_LPrefix && HasVEX_WPrefix) {
281 if (OpPrefix == X86Local::PD)
282 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
283 else if (OpPrefix == X86Local::XS)
284 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
285 else if (OpPrefix == X86Local::XD)
286 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
287 else if (OpPrefix == X86Local::PS)
288 insnContext = EVEX_KB(IC_EVEX_L_W);
290 errs() << "Instruction does not use a prefix: " << Name << "\n";
291 llvm_unreachable("Invalid prefix");
293 } else if (HasVEX_LPrefix) {
295 if (OpPrefix == X86Local::PD)
296 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
297 else if (OpPrefix == X86Local::XS)
298 insnContext = EVEX_KB(IC_EVEX_L_XS);
299 else if (OpPrefix == X86Local::XD)
300 insnContext = EVEX_KB(IC_EVEX_L_XD);
301 else if (OpPrefix == X86Local::PS)
302 insnContext = EVEX_KB(IC_EVEX_L);
304 errs() << "Instruction does not use a prefix: " << Name << "\n";
305 llvm_unreachable("Invalid prefix");
308 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
310 if (OpPrefix == X86Local::PD)
311 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
312 else if (OpPrefix == X86Local::XS)
313 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
314 else if (OpPrefix == X86Local::XD)
315 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
316 else if (OpPrefix == X86Local::PS)
317 insnContext = EVEX_KB(IC_EVEX_L2_W);
319 errs() << "Instruction does not use a prefix: " << Name << "\n";
320 llvm_unreachable("Invalid prefix");
322 } else if (HasEVEX_L2Prefix) {
324 if (OpPrefix == X86Local::PD)
325 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
326 else if (OpPrefix == X86Local::XD)
327 insnContext = EVEX_KB(IC_EVEX_L2_XD);
328 else if (OpPrefix == X86Local::XS)
329 insnContext = EVEX_KB(IC_EVEX_L2_XS);
330 else if (OpPrefix == X86Local::PS)
331 insnContext = EVEX_KB(IC_EVEX_L2);
333 errs() << "Instruction does not use a prefix: " << Name << "\n";
334 llvm_unreachable("Invalid prefix");
337 else if (HasVEX_WPrefix) {
339 if (OpPrefix == X86Local::PD)
340 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
341 else if (OpPrefix == X86Local::XS)
342 insnContext = EVEX_KB(IC_EVEX_W_XS);
343 else if (OpPrefix == X86Local::XD)
344 insnContext = EVEX_KB(IC_EVEX_W_XD);
345 else if (OpPrefix == X86Local::PS)
346 insnContext = EVEX_KB(IC_EVEX_W);
348 errs() << "Instruction does not use a prefix: " << Name << "\n";
349 llvm_unreachable("Invalid prefix");
353 else if (OpPrefix == X86Local::PD)
354 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
355 else if (OpPrefix == X86Local::XD)
356 insnContext = EVEX_KB(IC_EVEX_XD);
357 else if (OpPrefix == X86Local::XS)
358 insnContext = EVEX_KB(IC_EVEX_XS);
360 insnContext = EVEX_KB(IC_EVEX);
362 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
363 if (HasVEX_LPrefix && HasVEX_WPrefix) {
364 if (OpPrefix == X86Local::PD)
365 insnContext = IC_VEX_L_W_OPSIZE;
366 else if (OpPrefix == X86Local::XS)
367 insnContext = IC_VEX_L_W_XS;
368 else if (OpPrefix == X86Local::XD)
369 insnContext = IC_VEX_L_W_XD;
370 else if (OpPrefix == X86Local::PS)
371 insnContext = IC_VEX_L_W;
373 errs() << "Instruction does not use a prefix: " << Name << "\n";
374 llvm_unreachable("Invalid prefix");
376 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
377 insnContext = IC_VEX_L_OPSIZE;
378 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix)
379 insnContext = IC_VEX_W_OPSIZE;
380 else if (OpPrefix == X86Local::PD)
381 insnContext = IC_VEX_OPSIZE;
382 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
383 insnContext = IC_VEX_L_XS;
384 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
385 insnContext = IC_VEX_L_XD;
386 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS)
387 insnContext = IC_VEX_W_XS;
388 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD)
389 insnContext = IC_VEX_W_XD;
390 else if (HasVEX_WPrefix && OpPrefix == X86Local::PS)
391 insnContext = IC_VEX_W;
392 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
393 insnContext = IC_VEX_L;
394 else if (OpPrefix == X86Local::XD)
395 insnContext = IC_VEX_XD;
396 else if (OpPrefix == X86Local::XS)
397 insnContext = IC_VEX_XS;
398 else if (OpPrefix == X86Local::PS)
399 insnContext = IC_VEX;
401 errs() << "Instruction does not use a prefix: " << Name << "\n";
402 llvm_unreachable("Invalid prefix");
404 } else if (Is64Bit || HasREX_WPrefix) {
405 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
406 insnContext = IC_64BIT_REXW_OPSIZE;
407 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
408 insnContext = IC_64BIT_XD_OPSIZE;
409 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
410 insnContext = IC_64BIT_XS_OPSIZE;
411 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
412 insnContext = IC_64BIT_OPSIZE;
413 else if (HasAdSizePrefix)
414 insnContext = IC_64BIT_ADSIZE;
415 else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
416 insnContext = IC_64BIT_REXW_XS;
417 else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
418 insnContext = IC_64BIT_REXW_XD;
419 else if (OpPrefix == X86Local::XD)
420 insnContext = IC_64BIT_XD;
421 else if (OpPrefix == X86Local::XS)
422 insnContext = IC_64BIT_XS;
423 else if (HasREX_WPrefix)
424 insnContext = IC_64BIT_REXW;
426 insnContext = IC_64BIT;
428 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
429 insnContext = IC_XD_OPSIZE;
430 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
431 insnContext = IC_XS_OPSIZE;
432 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
433 insnContext = IC_OPSIZE;
434 else if (HasAdSizePrefix)
435 insnContext = IC_ADSIZE;
436 else if (OpPrefix == X86Local::XD)
438 else if (OpPrefix == X86Local::XS)
447 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
448 // The scaling factor for AVX512 compressed displacement encoding is an
449 // instruction attribute. Adjust the ModRM encoding type to include the
450 // scale for compressed displacement.
451 if (encoding != ENCODING_RM || CD8_Scale == 0)
453 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
454 assert(encoding <= ENCODING_RM_CD64 && "Invalid CDisp scaling");
457 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
458 unsigned &physicalOperandIndex,
459 unsigned &numPhysicalOperands,
460 const unsigned *operandMapping,
461 OperandEncoding (*encodingFromString)
465 if (physicalOperandIndex >= numPhysicalOperands)
468 assert(physicalOperandIndex < numPhysicalOperands);
471 while (operandMapping[operandIndex] != operandIndex) {
472 Spec->operands[operandIndex].encoding = ENCODING_DUP;
473 Spec->operands[operandIndex].type =
474 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
478 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
480 OperandEncoding encoding = encodingFromString(typeName, OpSize);
481 // Adjust the encoding type for an operand based on the instruction.
482 adjustOperandEncoding(encoding);
483 Spec->operands[operandIndex].encoding = encoding;
484 Spec->operands[operandIndex].type = typeFromString(typeName,
485 HasREX_WPrefix, OpSize);
488 ++physicalOperandIndex;
491 void RecognizableInstr::emitInstructionSpecifier() {
494 Spec->insnContext = insnContext();
496 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
498 unsigned numOperands = OperandList.size();
499 unsigned numPhysicalOperands = 0;
501 // operandMapping maps from operands in OperandList to their originals.
502 // If operandMapping[i] != i, then the entry is a duplicate.
503 unsigned operandMapping[X86_MAX_OPERANDS];
504 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
506 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
507 if (OperandList[operandIndex].Constraints.size()) {
508 const CGIOperandList::ConstraintInfo &Constraint =
509 OperandList[operandIndex].Constraints[0];
510 if (Constraint.isTied()) {
511 operandMapping[operandIndex] = operandIndex;
512 operandMapping[Constraint.getTiedOperand()] = operandIndex;
514 ++numPhysicalOperands;
515 operandMapping[operandIndex] = operandIndex;
518 ++numPhysicalOperands;
519 operandMapping[operandIndex] = operandIndex;
523 #define HANDLE_OPERAND(class) \
524 handleOperand(false, \
526 physicalOperandIndex, \
527 numPhysicalOperands, \
529 class##EncodingFromString);
531 #define HANDLE_OPTIONAL(class) \
532 handleOperand(true, \
534 physicalOperandIndex, \
535 numPhysicalOperands, \
537 class##EncodingFromString);
539 // operandIndex should always be < numOperands
540 unsigned operandIndex = 0;
541 // physicalOperandIndex should always be < numPhysicalOperands
542 unsigned physicalOperandIndex = 0;
544 // Given the set of prefix bits, how many additional operands does the
546 unsigned additionalOperands = 0;
547 if (HasVEX_4V || HasVEX_4VOp3)
548 ++additionalOperands;
550 ++additionalOperands;
553 default: llvm_unreachable("Unhandled form");
554 case X86Local::RawFrmSrc:
555 HANDLE_OPERAND(relocation);
557 case X86Local::RawFrmDst:
558 HANDLE_OPERAND(relocation);
560 case X86Local::RawFrmDstSrc:
561 HANDLE_OPERAND(relocation);
562 HANDLE_OPERAND(relocation);
564 case X86Local::RawFrm:
565 // Operand 1 (optional) is an address or immediate.
566 // Operand 2 (optional) is an immediate.
567 assert(numPhysicalOperands <= 2 &&
568 "Unexpected number of operands for RawFrm");
569 HANDLE_OPTIONAL(relocation)
570 HANDLE_OPTIONAL(immediate)
572 case X86Local::RawFrmMemOffs:
573 // Operand 1 is an address.
574 HANDLE_OPERAND(relocation);
576 case X86Local::AddRegFrm:
577 // Operand 1 is added to the opcode.
578 // Operand 2 (optional) is an address.
579 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
580 "Unexpected number of operands for AddRegFrm");
581 HANDLE_OPERAND(opcodeModifier)
582 HANDLE_OPTIONAL(relocation)
584 case X86Local::MRMDestReg:
585 // Operand 1 is a register operand in the R/M field.
586 // - In AVX512 there may be a mask operand here -
587 // Operand 2 is a register operand in the Reg/Opcode field.
588 // - In AVX, there is a register operand in the VEX.vvvv field here -
589 // Operand 3 (optional) is an immediate.
590 assert(numPhysicalOperands >= 2 + additionalOperands &&
591 numPhysicalOperands <= 3 + additionalOperands &&
592 "Unexpected number of operands for MRMDestRegFrm");
594 HANDLE_OPERAND(rmRegister)
597 // FIXME: In AVX, the register below becomes the one encoded
598 // in ModRMVEX and the one above the one in the VEX.VVVV field
599 HANDLE_OPERAND(vvvvRegister)
601 HANDLE_OPERAND(roRegister)
602 HANDLE_OPTIONAL(immediate)
604 case X86Local::MRMDestMem:
605 // Operand 1 is a memory operand (possibly SIB-extended)
606 // Operand 2 is a register operand in the Reg/Opcode field.
607 // - In AVX, there is a register operand in the VEX.vvvv field here -
608 // Operand 3 (optional) is an immediate.
609 assert(numPhysicalOperands >= 2 + additionalOperands &&
610 numPhysicalOperands <= 3 + additionalOperands &&
611 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
613 HANDLE_OPERAND(memory)
616 HANDLE_OPERAND(writemaskRegister)
619 // FIXME: In AVX, the register below becomes the one encoded
620 // in ModRMVEX and the one above the one in the VEX.VVVV field
621 HANDLE_OPERAND(vvvvRegister)
623 HANDLE_OPERAND(roRegister)
624 HANDLE_OPTIONAL(immediate)
626 case X86Local::MRMSrcReg:
627 // Operand 1 is a register operand in the Reg/Opcode field.
628 // Operand 2 is a register operand in the R/M field.
629 // - In AVX, there is a register operand in the VEX.vvvv field here -
630 // Operand 3 (optional) is an immediate.
631 // Operand 4 (optional) is an immediate.
633 assert(numPhysicalOperands >= 2 + additionalOperands &&
634 numPhysicalOperands <= 4 + additionalOperands &&
635 "Unexpected number of operands for MRMSrcRegFrm");
637 HANDLE_OPERAND(roRegister)
640 HANDLE_OPERAND(writemaskRegister)
643 // FIXME: In AVX, the register below becomes the one encoded
644 // in ModRMVEX and the one above the one in the VEX.VVVV field
645 HANDLE_OPERAND(vvvvRegister)
648 HANDLE_OPERAND(immediate)
650 HANDLE_OPERAND(rmRegister)
653 HANDLE_OPERAND(vvvvRegister)
655 if (!HasMemOp4Prefix)
656 HANDLE_OPTIONAL(immediate)
657 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
658 HANDLE_OPTIONAL(immediate)
660 case X86Local::MRMSrcMem:
661 // Operand 1 is a register operand in the Reg/Opcode field.
662 // Operand 2 is a memory operand (possibly SIB-extended)
663 // - In AVX, there is a register operand in the VEX.vvvv field here -
664 // Operand 3 (optional) is an immediate.
666 assert(numPhysicalOperands >= 2 + additionalOperands &&
667 numPhysicalOperands <= 4 + additionalOperands &&
668 "Unexpected number of operands for MRMSrcMemFrm");
670 HANDLE_OPERAND(roRegister)
673 HANDLE_OPERAND(writemaskRegister)
676 // FIXME: In AVX, the register below becomes the one encoded
677 // in ModRMVEX and the one above the one in the VEX.VVVV field
678 HANDLE_OPERAND(vvvvRegister)
681 HANDLE_OPERAND(immediate)
683 HANDLE_OPERAND(memory)
686 HANDLE_OPERAND(vvvvRegister)
688 if (!HasMemOp4Prefix)
689 HANDLE_OPTIONAL(immediate)
690 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
692 case X86Local::MRMXr:
693 case X86Local::MRM0r:
694 case X86Local::MRM1r:
695 case X86Local::MRM2r:
696 case X86Local::MRM3r:
697 case X86Local::MRM4r:
698 case X86Local::MRM5r:
699 case X86Local::MRM6r:
700 case X86Local::MRM7r:
701 // Operand 1 is a register operand in the R/M field.
702 // Operand 2 (optional) is an immediate or relocation.
703 // Operand 3 (optional) is an immediate.
704 assert(numPhysicalOperands >= 0 + additionalOperands &&
705 numPhysicalOperands <= 3 + additionalOperands &&
706 "Unexpected number of operands for MRMnr");
709 HANDLE_OPERAND(vvvvRegister)
712 HANDLE_OPERAND(writemaskRegister)
713 HANDLE_OPTIONAL(rmRegister)
714 HANDLE_OPTIONAL(relocation)
715 HANDLE_OPTIONAL(immediate)
717 case X86Local::MRMXm:
718 case X86Local::MRM0m:
719 case X86Local::MRM1m:
720 case X86Local::MRM2m:
721 case X86Local::MRM3m:
722 case X86Local::MRM4m:
723 case X86Local::MRM5m:
724 case X86Local::MRM6m:
725 case X86Local::MRM7m:
726 // Operand 1 is a memory operand (possibly SIB-extended)
727 // Operand 2 (optional) is an immediate or relocation.
728 assert(numPhysicalOperands >= 1 + additionalOperands &&
729 numPhysicalOperands <= 2 + additionalOperands &&
730 "Unexpected number of operands for MRMnm");
733 HANDLE_OPERAND(vvvvRegister)
735 HANDLE_OPERAND(writemaskRegister)
736 HANDLE_OPERAND(memory)
737 HANDLE_OPTIONAL(relocation)
739 case X86Local::RawFrmImm8:
740 // operand 1 is a 16-bit immediate
741 // operand 2 is an 8-bit immediate
742 assert(numPhysicalOperands == 2 &&
743 "Unexpected number of operands for X86Local::RawFrmImm8");
744 HANDLE_OPERAND(immediate)
745 HANDLE_OPERAND(immediate)
747 case X86Local::RawFrmImm16:
748 // operand 1 is a 16-bit immediate
749 // operand 2 is a 16-bit immediate
750 HANDLE_OPERAND(immediate)
751 HANDLE_OPERAND(immediate)
753 case X86Local::MRM_F8:
754 if (Opcode == 0xc6) {
755 assert(numPhysicalOperands == 1 &&
756 "Unexpected number of operands for X86Local::MRM_F8");
757 HANDLE_OPERAND(immediate)
758 } else if (Opcode == 0xc7) {
759 assert(numPhysicalOperands == 1 &&
760 "Unexpected number of operands for X86Local::MRM_F8");
761 HANDLE_OPERAND(relocation)
764 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2:
765 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8:
766 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB:
767 case X86Local::MRM_CF: case X86Local::MRM_D0: case X86Local::MRM_D1:
768 case X86Local::MRM_D4: case X86Local::MRM_D5: case X86Local::MRM_D6:
769 case X86Local::MRM_D7: case X86Local::MRM_D8: case X86Local::MRM_D9:
770 case X86Local::MRM_DA: case X86Local::MRM_DB: case X86Local::MRM_DC:
771 case X86Local::MRM_DD: case X86Local::MRM_DE: case X86Local::MRM_DF:
772 case X86Local::MRM_E0: case X86Local::MRM_E1: case X86Local::MRM_E2:
773 case X86Local::MRM_E3: case X86Local::MRM_E4: case X86Local::MRM_E5:
774 case X86Local::MRM_E8: case X86Local::MRM_E9: case X86Local::MRM_EA:
775 case X86Local::MRM_EB: case X86Local::MRM_EC: case X86Local::MRM_ED:
776 case X86Local::MRM_EE: case X86Local::MRM_F0: case X86Local::MRM_F1:
777 case X86Local::MRM_F2: case X86Local::MRM_F3: case X86Local::MRM_F4:
778 case X86Local::MRM_F5: case X86Local::MRM_F6: case X86Local::MRM_F7:
779 case X86Local::MRM_F9: case X86Local::MRM_FA: case X86Local::MRM_FB:
780 case X86Local::MRM_FC: case X86Local::MRM_FD: case X86Local::MRM_FE:
781 case X86Local::MRM_FF:
786 #undef HANDLE_OPERAND
787 #undef HANDLE_OPTIONAL
790 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
791 // Special cases where the LLVM tables are not complete
793 #define MAP(from, to) \
794 case X86Local::MRM_##from: \
795 filter = new ExactFilter(0x##from); \
798 OpcodeType opcodeType = (OpcodeType)-1;
800 ModRMFilter* filter = nullptr;
801 uint8_t opcodeToSet = 0;
804 default: llvm_unreachable("Invalid map!");
813 default: llvm_unreachable("Unexpected map!");
814 case X86Local::OB: opcodeType = ONEBYTE; break;
815 case X86Local::TB: opcodeType = TWOBYTE; break;
816 case X86Local::T8: opcodeType = THREEBYTE_38; break;
817 case X86Local::TA: opcodeType = THREEBYTE_3A; break;
818 case X86Local::XOP8: opcodeType = XOP8_MAP; break;
819 case X86Local::XOP9: opcodeType = XOP9_MAP; break;
820 case X86Local::XOPA: opcodeType = XOPA_MAP; break;
825 filter = new DumbFilter();
827 case X86Local::MRMDestReg: case X86Local::MRMDestMem:
828 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem:
829 case X86Local::MRMXr: case X86Local::MRMXm:
830 filter = new ModFilter(isRegFormat(Form));
832 case X86Local::MRM0r: case X86Local::MRM1r:
833 case X86Local::MRM2r: case X86Local::MRM3r:
834 case X86Local::MRM4r: case X86Local::MRM5r:
835 case X86Local::MRM6r: case X86Local::MRM7r:
836 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
838 case X86Local::MRM0m: case X86Local::MRM1m:
839 case X86Local::MRM2m: case X86Local::MRM3m:
840 case X86Local::MRM4m: case X86Local::MRM5m:
841 case X86Local::MRM6m: case X86Local::MRM7m:
842 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
847 opcodeToSet = Opcode;
851 assert(opcodeType != (OpcodeType)-1 &&
852 "Opcode type not set");
853 assert(filter && "Filter not set");
855 if (Form == X86Local::AddRegFrm) {
856 assert(((opcodeToSet & 7) == 0) &&
857 "ADDREG_FRM opcode not aligned");
859 uint8_t currentOpcode;
861 for (currentOpcode = opcodeToSet;
862 currentOpcode < opcodeToSet + 8;
864 tables.setTableFields(opcodeType,
868 UID, Is32Bit, IgnoresVEX_L);
870 tables.setTableFields(opcodeType,
874 UID, Is32Bit, IgnoresVEX_L);
882 #define TYPE(str, type) if (s == str) return type;
883 OperandType RecognizableInstr::typeFromString(const std::string &s,
887 // For instructions with a REX_W prefix, a declared 32-bit register encoding
889 TYPE("GR32", TYPE_R32)
891 if(OpSize == X86Local::OpSize16) {
892 // For OpSize16 instructions, a declared 16-bit register or
893 // immediate encoding is special.
894 TYPE("GR16", TYPE_Rv)
895 TYPE("i16imm", TYPE_IMMv)
896 } else if(OpSize == X86Local::OpSize32) {
897 // For OpSize32 instructions, a declared 32-bit register or
898 // immediate encoding is special.
899 TYPE("GR32", TYPE_Rv)
901 TYPE("i16mem", TYPE_Mv)
902 TYPE("i16imm", TYPE_IMM16)
903 TYPE("i16i8imm", TYPE_IMMv)
904 TYPE("GR16", TYPE_R16)
905 TYPE("i32mem", TYPE_Mv)
906 TYPE("i32imm", TYPE_IMMv)
907 TYPE("i32i8imm", TYPE_IMM32)
908 TYPE("GR32", TYPE_R32)
909 TYPE("GR32orGR64", TYPE_R32)
910 TYPE("i64mem", TYPE_Mv)
911 TYPE("i64i32imm", TYPE_IMM64)
912 TYPE("i64i8imm", TYPE_IMM64)
913 TYPE("GR64", TYPE_R64)
914 TYPE("i8mem", TYPE_M8)
915 TYPE("i8imm", TYPE_IMM8)
917 TYPE("VR128", TYPE_XMM128)
918 TYPE("VR128X", TYPE_XMM128)
919 TYPE("f128mem", TYPE_M128)
920 TYPE("f256mem", TYPE_M256)
921 TYPE("f512mem", TYPE_M512)
922 TYPE("FR64", TYPE_XMM64)
923 TYPE("FR64X", TYPE_XMM64)
924 TYPE("f64mem", TYPE_M64FP)
925 TYPE("sdmem", TYPE_M64FP)
926 TYPE("FR32", TYPE_XMM32)
927 TYPE("FR32X", TYPE_XMM32)
928 TYPE("f32mem", TYPE_M32FP)
929 TYPE("ssmem", TYPE_M32FP)
931 TYPE("i128mem", TYPE_M128)
932 TYPE("i256mem", TYPE_M256)
933 TYPE("i512mem", TYPE_M512)
934 TYPE("i64i32imm_pcrel", TYPE_REL64)
935 TYPE("i16imm_pcrel", TYPE_REL16)
936 TYPE("i32imm_pcrel", TYPE_REL32)
937 TYPE("SSECC", TYPE_IMM3)
938 TYPE("AVXCC", TYPE_IMM5)
939 TYPE("AVX512RC", TYPE_IMM32)
940 TYPE("brtarget", TYPE_RELv)
941 TYPE("uncondbrtarget", TYPE_RELv)
942 TYPE("brtarget8", TYPE_REL8)
943 TYPE("f80mem", TYPE_M80FP)
944 TYPE("lea32mem", TYPE_LEA)
945 TYPE("lea64_32mem", TYPE_LEA)
946 TYPE("lea64mem", TYPE_LEA)
947 TYPE("VR64", TYPE_MM64)
948 TYPE("i64imm", TYPE_IMMv)
949 TYPE("opaque32mem", TYPE_M1616)
950 TYPE("opaque48mem", TYPE_M1632)
951 TYPE("opaque80mem", TYPE_M1664)
952 TYPE("opaque512mem", TYPE_M512)
953 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
954 TYPE("DEBUG_REG", TYPE_DEBUGREG)
955 TYPE("CONTROL_REG", TYPE_CONTROLREG)
956 TYPE("srcidx8", TYPE_SRCIDX8)
957 TYPE("srcidx16", TYPE_SRCIDX16)
958 TYPE("srcidx32", TYPE_SRCIDX32)
959 TYPE("srcidx64", TYPE_SRCIDX64)
960 TYPE("dstidx8", TYPE_DSTIDX8)
961 TYPE("dstidx16", TYPE_DSTIDX16)
962 TYPE("dstidx32", TYPE_DSTIDX32)
963 TYPE("dstidx64", TYPE_DSTIDX64)
964 TYPE("offset8", TYPE_MOFFS8)
965 TYPE("offset16", TYPE_MOFFS16)
966 TYPE("offset32", TYPE_MOFFS32)
967 TYPE("offset64", TYPE_MOFFS64)
968 TYPE("VR256", TYPE_XMM256)
969 TYPE("VR256X", TYPE_XMM256)
970 TYPE("VR512", TYPE_XMM512)
971 TYPE("VK1", TYPE_VK1)
972 TYPE("VK1WM", TYPE_VK1)
973 TYPE("VK2", TYPE_VK2)
974 TYPE("VK2WM", TYPE_VK2)
975 TYPE("VK4", TYPE_VK4)
976 TYPE("VK4WM", TYPE_VK4)
977 TYPE("VK8", TYPE_VK8)
978 TYPE("VK8WM", TYPE_VK8)
979 TYPE("VK16", TYPE_VK16)
980 TYPE("VK16WM", TYPE_VK16)
981 TYPE("VK32", TYPE_VK32)
982 TYPE("VK32WM", TYPE_VK32)
983 TYPE("VK64", TYPE_VK64)
984 TYPE("VK64WM", TYPE_VK64)
985 TYPE("GR16_NOAX", TYPE_Rv)
986 TYPE("GR32_NOAX", TYPE_Rv)
987 TYPE("GR64_NOAX", TYPE_R64)
988 TYPE("vx32mem", TYPE_M32)
989 TYPE("vy32mem", TYPE_M32)
990 TYPE("vz32mem", TYPE_M32)
991 TYPE("vx64mem", TYPE_M64)
992 TYPE("vy64mem", TYPE_M64)
993 TYPE("vy64xmem", TYPE_M64)
994 TYPE("vz64mem", TYPE_M64)
995 errs() << "Unhandled type string " << s << "\n";
996 llvm_unreachable("Unhandled type string");
1000 #define ENCODING(str, encoding) if (s == str) return encoding;
1002 RecognizableInstr::immediateEncodingFromString(const std::string &s,
1004 if(OpSize != X86Local::OpSize16) {
1005 // For instructions without an OpSize prefix, a declared 16-bit register or
1006 // immediate encoding is special.
1007 ENCODING("i16imm", ENCODING_IW)
1009 ENCODING("i32i8imm", ENCODING_IB)
1010 ENCODING("SSECC", ENCODING_IB)
1011 ENCODING("AVXCC", ENCODING_IB)
1012 ENCODING("AVX512RC", ENCODING_IB)
1013 ENCODING("i16imm", ENCODING_Iv)
1014 ENCODING("i16i8imm", ENCODING_IB)
1015 ENCODING("i32imm", ENCODING_Iv)
1016 ENCODING("i64i32imm", ENCODING_ID)
1017 ENCODING("i64i8imm", ENCODING_IB)
1018 ENCODING("i8imm", ENCODING_IB)
1019 // This is not a typo. Instructions like BLENDVPD put
1020 // register IDs in 8-bit immediates nowadays.
1021 ENCODING("FR32", ENCODING_IB)
1022 ENCODING("FR64", ENCODING_IB)
1023 ENCODING("VR128", ENCODING_IB)
1024 ENCODING("VR256", ENCODING_IB)
1025 ENCODING("FR32X", ENCODING_IB)
1026 ENCODING("FR64X", ENCODING_IB)
1027 ENCODING("VR128X", ENCODING_IB)
1028 ENCODING("VR256X", ENCODING_IB)
1029 ENCODING("VR512", ENCODING_IB)
1030 errs() << "Unhandled immediate encoding " << s << "\n";
1031 llvm_unreachable("Unhandled immediate encoding");
1035 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1037 ENCODING("RST", ENCODING_FP)
1038 ENCODING("GR16", ENCODING_RM)
1039 ENCODING("GR32", ENCODING_RM)
1040 ENCODING("GR32orGR64", ENCODING_RM)
1041 ENCODING("GR64", ENCODING_RM)
1042 ENCODING("GR8", ENCODING_RM)
1043 ENCODING("VR128", ENCODING_RM)
1044 ENCODING("VR128X", ENCODING_RM)
1045 ENCODING("FR64", ENCODING_RM)
1046 ENCODING("FR32", ENCODING_RM)
1047 ENCODING("FR64X", ENCODING_RM)
1048 ENCODING("FR32X", ENCODING_RM)
1049 ENCODING("VR64", ENCODING_RM)
1050 ENCODING("VR256", ENCODING_RM)
1051 ENCODING("VR256X", ENCODING_RM)
1052 ENCODING("VR512", ENCODING_RM)
1053 ENCODING("VK1", ENCODING_RM)
1054 ENCODING("VK8", ENCODING_RM)
1055 ENCODING("VK16", ENCODING_RM)
1056 ENCODING("VK32", ENCODING_RM)
1057 ENCODING("VK64", ENCODING_RM)
1058 errs() << "Unhandled R/M register encoding " << s << "\n";
1059 llvm_unreachable("Unhandled R/M register encoding");
1063 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1065 ENCODING("GR16", ENCODING_REG)
1066 ENCODING("GR32", ENCODING_REG)
1067 ENCODING("GR32orGR64", ENCODING_REG)
1068 ENCODING("GR64", ENCODING_REG)
1069 ENCODING("GR8", ENCODING_REG)
1070 ENCODING("VR128", ENCODING_REG)
1071 ENCODING("FR64", ENCODING_REG)
1072 ENCODING("FR32", ENCODING_REG)
1073 ENCODING("VR64", ENCODING_REG)
1074 ENCODING("SEGMENT_REG", ENCODING_REG)
1075 ENCODING("DEBUG_REG", ENCODING_REG)
1076 ENCODING("CONTROL_REG", ENCODING_REG)
1077 ENCODING("VR256", ENCODING_REG)
1078 ENCODING("VR256X", ENCODING_REG)
1079 ENCODING("VR128X", ENCODING_REG)
1080 ENCODING("FR64X", ENCODING_REG)
1081 ENCODING("FR32X", ENCODING_REG)
1082 ENCODING("VR512", ENCODING_REG)
1083 ENCODING("VK1", ENCODING_REG)
1084 ENCODING("VK2", ENCODING_REG)
1085 ENCODING("VK4", ENCODING_REG)
1086 ENCODING("VK8", ENCODING_REG)
1087 ENCODING("VK16", ENCODING_REG)
1088 ENCODING("VK32", ENCODING_REG)
1089 ENCODING("VK64", ENCODING_REG)
1090 ENCODING("VK1WM", ENCODING_REG)
1091 ENCODING("VK8WM", ENCODING_REG)
1092 ENCODING("VK16WM", ENCODING_REG)
1093 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1094 llvm_unreachable("Unhandled reg/opcode register encoding");
1098 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1100 ENCODING("GR32", ENCODING_VVVV)
1101 ENCODING("GR64", ENCODING_VVVV)
1102 ENCODING("FR32", ENCODING_VVVV)
1103 ENCODING("FR64", ENCODING_VVVV)
1104 ENCODING("VR128", ENCODING_VVVV)
1105 ENCODING("VR256", ENCODING_VVVV)
1106 ENCODING("FR32X", ENCODING_VVVV)
1107 ENCODING("FR64X", ENCODING_VVVV)
1108 ENCODING("VR128X", ENCODING_VVVV)
1109 ENCODING("VR256X", ENCODING_VVVV)
1110 ENCODING("VR512", ENCODING_VVVV)
1111 ENCODING("VK1", ENCODING_VVVV)
1112 ENCODING("VK2", ENCODING_VVVV)
1113 ENCODING("VK4", ENCODING_VVVV)
1114 ENCODING("VK8", ENCODING_VVVV)
1115 ENCODING("VK16", ENCODING_VVVV)
1116 ENCODING("VK32", ENCODING_VVVV)
1117 ENCODING("VK64", ENCODING_VVVV)
1118 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1119 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1123 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1125 ENCODING("VK1WM", ENCODING_WRITEMASK)
1126 ENCODING("VK2WM", ENCODING_WRITEMASK)
1127 ENCODING("VK4WM", ENCODING_WRITEMASK)
1128 ENCODING("VK8WM", ENCODING_WRITEMASK)
1129 ENCODING("VK16WM", ENCODING_WRITEMASK)
1130 ENCODING("VK32WM", ENCODING_WRITEMASK)
1131 ENCODING("VK64WM", ENCODING_WRITEMASK)
1132 errs() << "Unhandled mask register encoding " << s << "\n";
1133 llvm_unreachable("Unhandled mask register encoding");
1137 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1139 ENCODING("i16mem", ENCODING_RM)
1140 ENCODING("i32mem", ENCODING_RM)
1141 ENCODING("i64mem", ENCODING_RM)
1142 ENCODING("i8mem", ENCODING_RM)
1143 ENCODING("ssmem", ENCODING_RM)
1144 ENCODING("sdmem", ENCODING_RM)
1145 ENCODING("f128mem", ENCODING_RM)
1146 ENCODING("f256mem", ENCODING_RM)
1147 ENCODING("f512mem", ENCODING_RM)
1148 ENCODING("f64mem", ENCODING_RM)
1149 ENCODING("f32mem", ENCODING_RM)
1150 ENCODING("i128mem", ENCODING_RM)
1151 ENCODING("i256mem", ENCODING_RM)
1152 ENCODING("i512mem", ENCODING_RM)
1153 ENCODING("f80mem", ENCODING_RM)
1154 ENCODING("lea32mem", ENCODING_RM)
1155 ENCODING("lea64_32mem", ENCODING_RM)
1156 ENCODING("lea64mem", ENCODING_RM)
1157 ENCODING("opaque32mem", ENCODING_RM)
1158 ENCODING("opaque48mem", ENCODING_RM)
1159 ENCODING("opaque80mem", ENCODING_RM)
1160 ENCODING("opaque512mem", ENCODING_RM)
1161 ENCODING("vx32mem", ENCODING_RM)
1162 ENCODING("vy32mem", ENCODING_RM)
1163 ENCODING("vz32mem", ENCODING_RM)
1164 ENCODING("vx64mem", ENCODING_RM)
1165 ENCODING("vy64mem", ENCODING_RM)
1166 ENCODING("vy64xmem", ENCODING_RM)
1167 ENCODING("vz64mem", ENCODING_RM)
1168 errs() << "Unhandled memory encoding " << s << "\n";
1169 llvm_unreachable("Unhandled memory encoding");
1173 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1175 if(OpSize != X86Local::OpSize16) {
1176 // For instructions without an OpSize prefix, a declared 16-bit register or
1177 // immediate encoding is special.
1178 ENCODING("i16imm", ENCODING_IW)
1180 ENCODING("i16imm", ENCODING_Iv)
1181 ENCODING("i16i8imm", ENCODING_IB)
1182 ENCODING("i32imm", ENCODING_Iv)
1183 ENCODING("i32i8imm", ENCODING_IB)
1184 ENCODING("i64i32imm", ENCODING_ID)
1185 ENCODING("i64i8imm", ENCODING_IB)
1186 ENCODING("i8imm", ENCODING_IB)
1187 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1188 ENCODING("i16imm_pcrel", ENCODING_IW)
1189 ENCODING("i32imm_pcrel", ENCODING_ID)
1190 ENCODING("brtarget", ENCODING_Iv)
1191 ENCODING("brtarget8", ENCODING_IB)
1192 ENCODING("i64imm", ENCODING_IO)
1193 ENCODING("offset8", ENCODING_Ia)
1194 ENCODING("offset16", ENCODING_Ia)
1195 ENCODING("offset32", ENCODING_Ia)
1196 ENCODING("offset64", ENCODING_Ia)
1197 ENCODING("srcidx8", ENCODING_SI)
1198 ENCODING("srcidx16", ENCODING_SI)
1199 ENCODING("srcidx32", ENCODING_SI)
1200 ENCODING("srcidx64", ENCODING_SI)
1201 ENCODING("dstidx8", ENCODING_DI)
1202 ENCODING("dstidx16", ENCODING_DI)
1203 ENCODING("dstidx32", ENCODING_DI)
1204 ENCODING("dstidx64", ENCODING_DI)
1205 errs() << "Unhandled relocation encoding " << s << "\n";
1206 llvm_unreachable("Unhandled relocation encoding");
1210 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1212 ENCODING("GR32", ENCODING_Rv)
1213 ENCODING("GR64", ENCODING_RO)
1214 ENCODING("GR16", ENCODING_Rv)
1215 ENCODING("GR8", ENCODING_RB)
1216 ENCODING("GR16_NOAX", ENCODING_Rv)
1217 ENCODING("GR32_NOAX", ENCODING_Rv)
1218 ENCODING("GR64_NOAX", ENCODING_RO)
1219 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1220 llvm_unreachable("Unhandled opcode modifier encoding");