1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
135 #define THREE_BYTE_38_EXTENSION_TABLES \
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
233 SegOvr = byteFromRec(Rec, "SegOvrBits");
235 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
236 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
237 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
238 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
239 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
240 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
242 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
243 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
244 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
245 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
247 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
248 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
249 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
250 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
252 Name = Rec->getName();
253 AsmString = Rec->getValueAsString("AsmString");
255 Operands = &insn.Operands.OperandList;
257 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
258 (Name.find("CRC32") != Name.npos);
259 HasFROperands = hasFROperands();
260 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
262 // Check for 64-bit inst which does not require REX
265 // FIXME: Is there some better way to check for In64BitMode?
266 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
267 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
268 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
269 Predicates[i]->getName().find("In32Bit") != Name.npos) {
273 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
278 // FIXME: These instructions aren't marked as 64-bit in any way
279 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
280 Rec->getName() == "POPFS64" ||
281 Rec->getName() == "POPGS64" ||
282 Rec->getName() == "PUSHFS64" ||
283 Rec->getName() == "PUSHGS64" ||
284 Rec->getName() == "REX64_PREFIX" ||
285 Rec->getName().find("MOV64") != Name.npos ||
286 Rec->getName().find("PUSH64") != Name.npos ||
287 Rec->getName().find("POP64") != Name.npos;
289 ShouldBeEmitted = true;
292 void RecognizableInstr::processInstr(DisassemblerTables &tables,
293 const CodeGenInstruction &insn,
296 // Ignore "asm parser only" instructions.
297 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
300 RecognizableInstr recogInstr(tables, insn, uid);
302 recogInstr.emitInstructionSpecifier();
304 if (recogInstr.shouldBeEmitted())
305 recogInstr.emitDecodePath(tables);
308 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
309 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
310 (HasEVEX_KZ ? n##_KZ : \
311 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
313 InstructionContext RecognizableInstr::insnContext() const {
314 InstructionContext insnContext;
317 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
318 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
319 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
322 if (HasVEX_LPrefix && HasVEX_WPrefix) {
324 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
325 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
326 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
327 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
328 Prefix == X86Local::TAXD)
329 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
331 insnContext = EVEX_KB(IC_EVEX_L_W);
332 } else if (HasVEX_LPrefix) {
335 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
336 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
337 insnContext = EVEX_KB(IC_EVEX_L_XS);
338 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
339 Prefix == X86Local::TAXD)
340 insnContext = EVEX_KB(IC_EVEX_L_XD);
342 insnContext = EVEX_KB(IC_EVEX_L);
344 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
347 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
348 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
349 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
350 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
351 Prefix == X86Local::TAXD)
352 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
354 insnContext = EVEX_KB(IC_EVEX_L2_W);
355 } else if (HasEVEX_L2Prefix) {
358 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
359 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
360 Prefix == X86Local::TAXD)
361 insnContext = EVEX_KB(IC_EVEX_L2_XD);
362 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
363 insnContext = EVEX_KB(IC_EVEX_L2_XS);
365 insnContext = EVEX_KB(IC_EVEX_L2);
367 else if (HasVEX_WPrefix) {
370 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
371 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
372 insnContext = EVEX_KB(IC_EVEX_W_XS);
373 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
374 Prefix == X86Local::TAXD)
375 insnContext = EVEX_KB(IC_EVEX_W_XD);
377 insnContext = EVEX_KB(IC_EVEX_W);
380 else if (HasOpSizePrefix)
381 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
382 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
383 Prefix == X86Local::TAXD)
384 insnContext = EVEX_KB(IC_EVEX_XD);
385 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
386 insnContext = EVEX_KB(IC_EVEX_XS);
388 insnContext = EVEX_KB(IC_EVEX);
390 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
391 if (HasVEX_LPrefix && HasVEX_WPrefix) {
393 insnContext = IC_VEX_L_W_OPSIZE;
394 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
395 insnContext = IC_VEX_L_W_XS;
396 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
397 Prefix == X86Local::TAXD)
398 insnContext = IC_VEX_L_W_XD;
400 insnContext = IC_VEX_L_W;
401 } else if (HasOpSizePrefix && HasVEX_LPrefix)
402 insnContext = IC_VEX_L_OPSIZE;
403 else if (HasOpSizePrefix && HasVEX_WPrefix)
404 insnContext = IC_VEX_W_OPSIZE;
405 else if (HasOpSizePrefix)
406 insnContext = IC_VEX_OPSIZE;
407 else if (HasVEX_LPrefix &&
408 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
409 insnContext = IC_VEX_L_XS;
410 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
411 Prefix == X86Local::T8XD ||
412 Prefix == X86Local::TAXD))
413 insnContext = IC_VEX_L_XD;
414 else if (HasVEX_WPrefix &&
415 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
416 insnContext = IC_VEX_W_XS;
417 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
418 Prefix == X86Local::T8XD ||
419 Prefix == X86Local::TAXD))
420 insnContext = IC_VEX_W_XD;
421 else if (HasVEX_WPrefix)
422 insnContext = IC_VEX_W;
423 else if (HasVEX_LPrefix)
424 insnContext = IC_VEX_L;
425 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
426 Prefix == X86Local::TAXD)
427 insnContext = IC_VEX_XD;
428 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
429 insnContext = IC_VEX_XS;
431 insnContext = IC_VEX;
432 } else if (Is64Bit || HasREX_WPrefix) {
433 if (HasREX_WPrefix && HasOpSizePrefix)
434 insnContext = IC_64BIT_REXW_OPSIZE;
435 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
436 Prefix == X86Local::T8XD ||
437 Prefix == X86Local::TAXD))
438 insnContext = IC_64BIT_XD_OPSIZE;
439 else if (HasOpSizePrefix &&
440 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
441 insnContext = IC_64BIT_XS_OPSIZE;
442 else if (HasOpSizePrefix)
443 insnContext = IC_64BIT_OPSIZE;
444 else if (HasAdSizePrefix)
445 insnContext = IC_64BIT_ADSIZE;
446 else if (HasREX_WPrefix &&
447 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
448 insnContext = IC_64BIT_REXW_XS;
449 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
450 Prefix == X86Local::T8XD ||
451 Prefix == X86Local::TAXD))
452 insnContext = IC_64BIT_REXW_XD;
453 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
454 Prefix == X86Local::TAXD)
455 insnContext = IC_64BIT_XD;
456 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
457 insnContext = IC_64BIT_XS;
458 else if (HasREX_WPrefix)
459 insnContext = IC_64BIT_REXW;
461 insnContext = IC_64BIT;
463 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
464 Prefix == X86Local::T8XD ||
465 Prefix == X86Local::TAXD))
466 insnContext = IC_XD_OPSIZE;
467 else if (HasOpSizePrefix &&
468 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
469 insnContext = IC_XS_OPSIZE;
470 else if (HasOpSizePrefix)
471 insnContext = IC_OPSIZE;
472 else if (HasAdSizePrefix)
473 insnContext = IC_ADSIZE;
474 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
475 Prefix == X86Local::TAXD)
477 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
478 Prefix == X86Local::REP)
487 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
492 // Filter out intrinsics
494 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
496 if (Form == X86Local::Pseudo ||
497 (IsCodeGenOnly && Name.find("_REV") == Name.npos &&
498 Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos))
499 return FILTER_STRONG;
502 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
503 // printed as a separate "instruction".
505 // Filter out instructions with segment override prefixes.
506 // They're too messy to handle now and we'll special case them if needed.
509 return FILTER_STRONG;
517 // Filter out instructions with a LOCK prefix;
518 // prefer forms that do not have the prefix
522 // Filter out alternate forms of AVX instructions
523 if (Name.find("_alt") != Name.npos ||
524 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
525 Name.find("_64mr") != Name.npos ||
526 Name.find("rr64") != Name.npos)
531 if (Name == "PUSH64i16" ||
532 Name == "MOVPQI2QImr" ||
533 Name == "VMOVPQI2QImr" ||
534 Name == "VMASKMOVDQU64")
537 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
538 // For now, just prefer the REP versions.
539 if (Name == "XACQUIRE_PREFIX" ||
540 Name == "XRELEASE_PREFIX")
543 return FILTER_NORMAL;
546 bool RecognizableInstr::hasFROperands() const {
547 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
548 unsigned numOperands = OperandList.size();
550 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
551 const std::string &recName = OperandList[operandIndex].Rec->getName();
553 if (recName.find("FR") != recName.npos)
559 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
560 unsigned &physicalOperandIndex,
561 unsigned &numPhysicalOperands,
562 const unsigned *operandMapping,
563 OperandEncoding (*encodingFromString)
565 bool hasOpSizePrefix)) {
567 if (physicalOperandIndex >= numPhysicalOperands)
570 assert(physicalOperandIndex < numPhysicalOperands);
573 while (operandMapping[operandIndex] != operandIndex) {
574 Spec->operands[operandIndex].encoding = ENCODING_DUP;
575 Spec->operands[operandIndex].type =
576 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
580 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
582 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
584 Spec->operands[operandIndex].type = typeFromString(typeName,
590 ++physicalOperandIndex;
593 void RecognizableInstr::emitInstructionSpecifier() {
596 if (!ShouldBeEmitted)
601 Spec->filtered = true;
604 ShouldBeEmitted = false;
610 Spec->insnContext = insnContext();
612 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
614 unsigned numOperands = OperandList.size();
615 unsigned numPhysicalOperands = 0;
617 // operandMapping maps from operands in OperandList to their originals.
618 // If operandMapping[i] != i, then the entry is a duplicate.
619 unsigned operandMapping[X86_MAX_OPERANDS];
620 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
622 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
623 if (OperandList[operandIndex].Constraints.size()) {
624 const CGIOperandList::ConstraintInfo &Constraint =
625 OperandList[operandIndex].Constraints[0];
626 if (Constraint.isTied()) {
627 operandMapping[operandIndex] = operandIndex;
628 operandMapping[Constraint.getTiedOperand()] = operandIndex;
630 ++numPhysicalOperands;
631 operandMapping[operandIndex] = operandIndex;
634 ++numPhysicalOperands;
635 operandMapping[operandIndex] = operandIndex;
639 #define HANDLE_OPERAND(class) \
640 handleOperand(false, \
642 physicalOperandIndex, \
643 numPhysicalOperands, \
645 class##EncodingFromString);
647 #define HANDLE_OPTIONAL(class) \
648 handleOperand(true, \
650 physicalOperandIndex, \
651 numPhysicalOperands, \
653 class##EncodingFromString);
655 // operandIndex should always be < numOperands
656 unsigned operandIndex = 0;
657 // physicalOperandIndex should always be < numPhysicalOperands
658 unsigned physicalOperandIndex = 0;
661 case X86Local::RawFrm:
662 // Operand 1 (optional) is an address or immediate.
663 // Operand 2 (optional) is an immediate.
664 assert(numPhysicalOperands <= 2 &&
665 "Unexpected number of operands for RawFrm");
666 HANDLE_OPTIONAL(relocation)
667 HANDLE_OPTIONAL(immediate)
669 case X86Local::AddRegFrm:
670 // Operand 1 is added to the opcode.
671 // Operand 2 (optional) is an address.
672 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
673 "Unexpected number of operands for AddRegFrm");
674 HANDLE_OPERAND(opcodeModifier)
675 HANDLE_OPTIONAL(relocation)
677 case X86Local::MRMDestReg:
678 // Operand 1 is a register operand in the R/M field.
679 // Operand 2 is a register operand in the Reg/Opcode field.
680 // - In AVX, there is a register operand in the VEX.vvvv field here -
681 // Operand 3 (optional) is an immediate.
683 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
684 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
686 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
687 "Unexpected number of operands for MRMDestRegFrm");
689 HANDLE_OPERAND(rmRegister)
692 // FIXME: In AVX, the register below becomes the one encoded
693 // in ModRMVEX and the one above the one in the VEX.VVVV field
694 HANDLE_OPERAND(vvvvRegister)
696 HANDLE_OPERAND(roRegister)
697 HANDLE_OPTIONAL(immediate)
699 case X86Local::MRMDestMem:
700 // Operand 1 is a memory operand (possibly SIB-extended)
701 // Operand 2 is a register operand in the Reg/Opcode field.
702 // - In AVX, there is a register operand in the VEX.vvvv field here -
703 // Operand 3 (optional) is an immediate.
705 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
706 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
708 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
709 "Unexpected number of operands for MRMDestMemFrm");
710 HANDLE_OPERAND(memory)
713 HANDLE_OPERAND(writemaskRegister)
716 // FIXME: In AVX, the register below becomes the one encoded
717 // in ModRMVEX and the one above the one in the VEX.VVVV field
718 HANDLE_OPERAND(vvvvRegister)
720 HANDLE_OPERAND(roRegister)
721 HANDLE_OPTIONAL(immediate)
723 case X86Local::MRMSrcReg:
724 // Operand 1 is a register operand in the Reg/Opcode field.
725 // Operand 2 is a register operand in the R/M field.
726 // - In AVX, there is a register operand in the VEX.vvvv field here -
727 // Operand 3 (optional) is an immediate.
728 // Operand 4 (optional) is an immediate.
730 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
731 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
732 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
734 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
735 "Unexpected number of operands for MRMSrcRegFrm");
737 HANDLE_OPERAND(roRegister)
740 HANDLE_OPERAND(writemaskRegister)
743 // FIXME: In AVX, the register below becomes the one encoded
744 // in ModRMVEX and the one above the one in the VEX.VVVV field
745 HANDLE_OPERAND(vvvvRegister)
748 HANDLE_OPERAND(immediate)
750 HANDLE_OPERAND(rmRegister)
752 if (HasVEX_4VOp3Prefix)
753 HANDLE_OPERAND(vvvvRegister)
755 if (!HasMemOp4Prefix)
756 HANDLE_OPTIONAL(immediate)
757 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
758 HANDLE_OPTIONAL(immediate)
760 case X86Local::MRMSrcMem:
761 // Operand 1 is a register operand in the Reg/Opcode field.
762 // Operand 2 is a memory operand (possibly SIB-extended)
763 // - In AVX, there is a register operand in the VEX.vvvv field here -
764 // Operand 3 (optional) is an immediate.
766 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
767 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
768 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
770 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
771 "Unexpected number of operands for MRMSrcMemFrm");
773 HANDLE_OPERAND(roRegister)
776 HANDLE_OPERAND(writemaskRegister)
779 // FIXME: In AVX, the register below becomes the one encoded
780 // in ModRMVEX and the one above the one in the VEX.VVVV field
781 HANDLE_OPERAND(vvvvRegister)
784 HANDLE_OPERAND(immediate)
786 HANDLE_OPERAND(memory)
788 if (HasVEX_4VOp3Prefix)
789 HANDLE_OPERAND(vvvvRegister)
791 if (!HasMemOp4Prefix)
792 HANDLE_OPTIONAL(immediate)
793 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
795 case X86Local::MRM0r:
796 case X86Local::MRM1r:
797 case X86Local::MRM2r:
798 case X86Local::MRM3r:
799 case X86Local::MRM4r:
800 case X86Local::MRM5r:
801 case X86Local::MRM6r:
802 case X86Local::MRM7r:
804 // Operand 1 is a register operand in the R/M field.
805 // Operand 2 (optional) is an immediate or relocation.
806 // Operand 3 (optional) is an immediate.
807 unsigned kOp = (HasEVEX_K) ? 1:0;
808 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
809 if (numPhysicalOperands > 3 + kOp + Op4v)
810 llvm_unreachable("Unexpected number of operands for MRMnr");
813 HANDLE_OPERAND(vvvvRegister)
816 HANDLE_OPERAND(writemaskRegister)
817 HANDLE_OPTIONAL(rmRegister)
818 HANDLE_OPTIONAL(relocation)
819 HANDLE_OPTIONAL(immediate)
821 case X86Local::MRM0m:
822 case X86Local::MRM1m:
823 case X86Local::MRM2m:
824 case X86Local::MRM3m:
825 case X86Local::MRM4m:
826 case X86Local::MRM5m:
827 case X86Local::MRM6m:
828 case X86Local::MRM7m:
830 // Operand 1 is a memory operand (possibly SIB-extended)
831 // Operand 2 (optional) is an immediate or relocation.
832 unsigned kOp = (HasEVEX_K) ? 1:0;
833 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
834 if (numPhysicalOperands < 1 + kOp + Op4v ||
835 numPhysicalOperands > 2 + kOp + Op4v)
836 llvm_unreachable("Unexpected number of operands for MRMnm");
839 HANDLE_OPERAND(vvvvRegister)
841 HANDLE_OPERAND(writemaskRegister)
842 HANDLE_OPERAND(memory)
843 HANDLE_OPTIONAL(relocation)
845 case X86Local::RawFrmImm8:
846 // operand 1 is a 16-bit immediate
847 // operand 2 is an 8-bit immediate
848 assert(numPhysicalOperands == 2 &&
849 "Unexpected number of operands for X86Local::RawFrmImm8");
850 HANDLE_OPERAND(immediate)
851 HANDLE_OPERAND(immediate)
853 case X86Local::RawFrmImm16:
854 // operand 1 is a 16-bit immediate
855 // operand 2 is a 16-bit immediate
856 HANDLE_OPERAND(immediate)
857 HANDLE_OPERAND(immediate)
859 case X86Local::MRM_F8:
860 if (Opcode == 0xc6) {
861 assert(numPhysicalOperands == 1 &&
862 "Unexpected number of operands for X86Local::MRM_F8");
863 HANDLE_OPERAND(immediate)
864 } else if (Opcode == 0xc7) {
865 assert(numPhysicalOperands == 1 &&
866 "Unexpected number of operands for X86Local::MRM_F8");
867 HANDLE_OPERAND(relocation)
870 case X86Local::MRMInitReg:
875 #undef HANDLE_OPERAND
876 #undef HANDLE_OPTIONAL
879 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
880 // Special cases where the LLVM tables are not complete
882 #define MAP(from, to) \
883 case X86Local::MRM_##from: \
884 filter = new ExactFilter(0x##from); \
887 OpcodeType opcodeType = (OpcodeType)-1;
889 ModRMFilter* filter = NULL;
890 uint8_t opcodeToSet = 0;
893 default: llvm_unreachable("Invalid prefix!");
894 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
898 opcodeType = TWOBYTE;
902 if (needsModRMForDecode(Form))
903 filter = new ModFilter(isRegFormat(Form));
905 filter = new DumbFilter();
907 #define EXTENSION_TABLE(n) case 0x##n:
908 TWO_BYTE_EXTENSION_TABLES
909 #undef EXTENSION_TABLE
912 llvm_unreachable("Unhandled two-byte extended opcode");
913 case X86Local::MRM0r:
914 case X86Local::MRM1r:
915 case X86Local::MRM2r:
916 case X86Local::MRM3r:
917 case X86Local::MRM4r:
918 case X86Local::MRM5r:
919 case X86Local::MRM6r:
920 case X86Local::MRM7r:
921 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
923 case X86Local::MRM0m:
924 case X86Local::MRM1m:
925 case X86Local::MRM2m:
926 case X86Local::MRM3m:
927 case X86Local::MRM4m:
928 case X86Local::MRM5m:
929 case X86Local::MRM6m:
930 case X86Local::MRM7m:
931 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
937 opcodeToSet = Opcode;
942 opcodeType = THREEBYTE_38;
945 if (needsModRMForDecode(Form))
946 filter = new ModFilter(isRegFormat(Form));
948 filter = new DumbFilter();
950 #define EXTENSION_TABLE(n) case 0x##n:
951 THREE_BYTE_38_EXTENSION_TABLES
952 #undef EXTENSION_TABLE
955 llvm_unreachable("Unhandled two-byte extended opcode");
956 case X86Local::MRM0r:
957 case X86Local::MRM1r:
958 case X86Local::MRM2r:
959 case X86Local::MRM3r:
960 case X86Local::MRM4r:
961 case X86Local::MRM5r:
962 case X86Local::MRM6r:
963 case X86Local::MRM7r:
964 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
966 case X86Local::MRM0m:
967 case X86Local::MRM1m:
968 case X86Local::MRM2m:
969 case X86Local::MRM3m:
970 case X86Local::MRM4m:
971 case X86Local::MRM5m:
972 case X86Local::MRM6m:
973 case X86Local::MRM7m:
974 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
980 opcodeToSet = Opcode;
984 opcodeType = THREEBYTE_3A;
985 if (needsModRMForDecode(Form))
986 filter = new ModFilter(isRegFormat(Form));
988 filter = new DumbFilter();
989 opcodeToSet = Opcode;
992 opcodeType = THREEBYTE_A6;
993 if (needsModRMForDecode(Form))
994 filter = new ModFilter(isRegFormat(Form));
996 filter = new DumbFilter();
997 opcodeToSet = Opcode;
1000 opcodeType = THREEBYTE_A7;
1001 if (needsModRMForDecode(Form))
1002 filter = new ModFilter(isRegFormat(Form));
1004 filter = new DumbFilter();
1005 opcodeToSet = Opcode;
1007 case X86Local::XOP8:
1008 opcodeType = XOP8_MAP;
1009 if (needsModRMForDecode(Form))
1010 filter = new ModFilter(isRegFormat(Form));
1012 filter = new DumbFilter();
1013 opcodeToSet = Opcode;
1015 case X86Local::XOP9:
1016 opcodeType = XOP9_MAP;
1019 if (needsModRMForDecode(Form))
1020 filter = new ModFilter(isRegFormat(Form));
1022 filter = new DumbFilter();
1024 #define EXTENSION_TABLE(n) case 0x##n:
1025 XOP9_MAP_EXTENSION_TABLES
1026 #undef EXTENSION_TABLE
1029 llvm_unreachable("Unhandled XOP9 extended opcode");
1030 case X86Local::MRM0r:
1031 case X86Local::MRM1r:
1032 case X86Local::MRM2r:
1033 case X86Local::MRM3r:
1034 case X86Local::MRM4r:
1035 case X86Local::MRM5r:
1036 case X86Local::MRM6r:
1037 case X86Local::MRM7r:
1038 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1040 case X86Local::MRM0m:
1041 case X86Local::MRM1m:
1042 case X86Local::MRM2m:
1043 case X86Local::MRM3m:
1044 case X86Local::MRM4m:
1045 case X86Local::MRM5m:
1046 case X86Local::MRM6m:
1047 case X86Local::MRM7m:
1048 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1053 } // switch (Opcode)
1054 opcodeToSet = Opcode;
1056 case X86Local::XOPA:
1057 opcodeType = XOPA_MAP;
1058 if (needsModRMForDecode(Form))
1059 filter = new ModFilter(isRegFormat(Form));
1061 filter = new DumbFilter();
1062 opcodeToSet = Opcode;
1072 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1073 assert(Form == X86Local::RawFrm);
1074 opcodeType = ONEBYTE;
1075 filter = new ExactFilter(Opcode);
1076 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1080 opcodeType = ONEBYTE;
1082 #define EXTENSION_TABLE(n) case 0x##n:
1083 ONE_BYTE_EXTENSION_TABLES
1084 #undef EXTENSION_TABLE
1087 llvm_unreachable("Fell through the cracks of a single-byte "
1089 case X86Local::MRM0r:
1090 case X86Local::MRM1r:
1091 case X86Local::MRM2r:
1092 case X86Local::MRM3r:
1093 case X86Local::MRM4r:
1094 case X86Local::MRM5r:
1095 case X86Local::MRM6r:
1096 case X86Local::MRM7r:
1097 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1099 case X86Local::MRM0m:
1100 case X86Local::MRM1m:
1101 case X86Local::MRM2m:
1102 case X86Local::MRM3m:
1103 case X86Local::MRM4m:
1104 case X86Local::MRM5m:
1105 case X86Local::MRM6m:
1106 case X86Local::MRM7m:
1107 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1122 llvm_unreachable("Unhandled escape opcode form");
1123 case X86Local::MRM0r:
1124 case X86Local::MRM1r:
1125 case X86Local::MRM2r:
1126 case X86Local::MRM3r:
1127 case X86Local::MRM4r:
1128 case X86Local::MRM5r:
1129 case X86Local::MRM6r:
1130 case X86Local::MRM7r:
1131 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1133 case X86Local::MRM0m:
1134 case X86Local::MRM1m:
1135 case X86Local::MRM2m:
1136 case X86Local::MRM3m:
1137 case X86Local::MRM4m:
1138 case X86Local::MRM5m:
1139 case X86Local::MRM6m:
1140 case X86Local::MRM7m:
1141 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1146 if (needsModRMForDecode(Form))
1147 filter = new ModFilter(isRegFormat(Form));
1149 filter = new DumbFilter();
1151 } // switch (Opcode)
1152 opcodeToSet = Opcode;
1153 } // switch (Prefix)
1155 assert(opcodeType != (OpcodeType)-1 &&
1156 "Opcode type not set");
1157 assert(filter && "Filter not set");
1159 if (Form == X86Local::AddRegFrm) {
1160 assert(((opcodeToSet & 7) == 0) &&
1161 "ADDREG_FRM opcode not aligned");
1163 uint8_t currentOpcode;
1165 for (currentOpcode = opcodeToSet;
1166 currentOpcode < opcodeToSet + 8;
1168 tables.setTableFields(opcodeType,
1172 UID, Is32Bit, IgnoresVEX_L);
1174 tables.setTableFields(opcodeType,
1178 UID, Is32Bit, IgnoresVEX_L);
1186 #define TYPE(str, type) if (s == str) return type;
1187 OperandType RecognizableInstr::typeFromString(const std::string &s,
1189 bool hasREX_WPrefix,
1190 bool hasOpSizePrefix) {
1192 // For SSE instructions, we ignore the OpSize prefix and force operand
1194 TYPE("GR16", TYPE_R16)
1195 TYPE("GR32", TYPE_R32)
1196 TYPE("GR64", TYPE_R64)
1198 if(hasREX_WPrefix) {
1199 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1201 TYPE("GR32", TYPE_R32)
1203 if(!hasOpSizePrefix) {
1204 // For instructions without an OpSize prefix, a declared 16-bit register or
1205 // immediate encoding is special.
1206 TYPE("GR16", TYPE_R16)
1207 TYPE("i16imm", TYPE_IMM16)
1209 TYPE("i16mem", TYPE_Mv)
1210 TYPE("i16imm", TYPE_IMMv)
1211 TYPE("i16i8imm", TYPE_IMMv)
1212 TYPE("GR16", TYPE_Rv)
1213 TYPE("i32mem", TYPE_Mv)
1214 TYPE("i32imm", TYPE_IMMv)
1215 TYPE("i32i8imm", TYPE_IMM32)
1216 TYPE("u32u8imm", TYPE_IMM32)
1217 TYPE("GR32", TYPE_Rv)
1218 TYPE("GR32orGR64", TYPE_R32)
1219 TYPE("i64mem", TYPE_Mv)
1220 TYPE("i64i32imm", TYPE_IMM64)
1221 TYPE("i64i8imm", TYPE_IMM64)
1222 TYPE("GR64", TYPE_R64)
1223 TYPE("i8mem", TYPE_M8)
1224 TYPE("i8imm", TYPE_IMM8)
1225 TYPE("GR8", TYPE_R8)
1226 TYPE("VR128", TYPE_XMM128)
1227 TYPE("VR128X", TYPE_XMM128)
1228 TYPE("f128mem", TYPE_M128)
1229 TYPE("f256mem", TYPE_M256)
1230 TYPE("f512mem", TYPE_M512)
1231 TYPE("FR64", TYPE_XMM64)
1232 TYPE("FR64X", TYPE_XMM64)
1233 TYPE("f64mem", TYPE_M64FP)
1234 TYPE("sdmem", TYPE_M64FP)
1235 TYPE("FR32", TYPE_XMM32)
1236 TYPE("FR32X", TYPE_XMM32)
1237 TYPE("f32mem", TYPE_M32FP)
1238 TYPE("ssmem", TYPE_M32FP)
1239 TYPE("RST", TYPE_ST)
1240 TYPE("i128mem", TYPE_M128)
1241 TYPE("i256mem", TYPE_M256)
1242 TYPE("i512mem", TYPE_M512)
1243 TYPE("i64i32imm_pcrel", TYPE_REL64)
1244 TYPE("i16imm_pcrel", TYPE_REL16)
1245 TYPE("i32imm_pcrel", TYPE_REL32)
1246 TYPE("SSECC", TYPE_IMM3)
1247 TYPE("AVXCC", TYPE_IMM5)
1248 TYPE("AVX512RC", TYPE_IMM32)
1249 TYPE("brtarget", TYPE_RELv)
1250 TYPE("uncondbrtarget", TYPE_RELv)
1251 TYPE("brtarget8", TYPE_REL8)
1252 TYPE("f80mem", TYPE_M80FP)
1253 TYPE("lea32mem", TYPE_LEA)
1254 TYPE("lea64_32mem", TYPE_LEA)
1255 TYPE("lea64mem", TYPE_LEA)
1256 TYPE("VR64", TYPE_MM64)
1257 TYPE("i64imm", TYPE_IMMv)
1258 TYPE("opaque32mem", TYPE_M1616)
1259 TYPE("opaque48mem", TYPE_M1632)
1260 TYPE("opaque80mem", TYPE_M1664)
1261 TYPE("opaque512mem", TYPE_M512)
1262 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1263 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1264 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1265 TYPE("offset8", TYPE_MOFFS8)
1266 TYPE("offset16", TYPE_MOFFS16)
1267 TYPE("offset32", TYPE_MOFFS32)
1268 TYPE("offset64", TYPE_MOFFS64)
1269 TYPE("VR256", TYPE_XMM256)
1270 TYPE("VR256X", TYPE_XMM256)
1271 TYPE("VR512", TYPE_XMM512)
1272 TYPE("VK1", TYPE_VK1)
1273 TYPE("VK1WM", TYPE_VK1)
1274 TYPE("VK8", TYPE_VK8)
1275 TYPE("VK8WM", TYPE_VK8)
1276 TYPE("VK16", TYPE_VK16)
1277 TYPE("VK16WM", TYPE_VK16)
1278 TYPE("GR16_NOAX", TYPE_Rv)
1279 TYPE("GR32_NOAX", TYPE_Rv)
1280 TYPE("GR64_NOAX", TYPE_R64)
1281 TYPE("vx32mem", TYPE_M32)
1282 TYPE("vy32mem", TYPE_M32)
1283 TYPE("vz32mem", TYPE_M32)
1284 TYPE("vx64mem", TYPE_M64)
1285 TYPE("vy64mem", TYPE_M64)
1286 TYPE("vy64xmem", TYPE_M64)
1287 TYPE("vz64mem", TYPE_M64)
1288 errs() << "Unhandled type string " << s << "\n";
1289 llvm_unreachable("Unhandled type string");
1293 #define ENCODING(str, encoding) if (s == str) return encoding;
1294 OperandEncoding RecognizableInstr::immediateEncodingFromString
1295 (const std::string &s,
1296 bool hasOpSizePrefix) {
1297 if(!hasOpSizePrefix) {
1298 // For instructions without an OpSize prefix, a declared 16-bit register or
1299 // immediate encoding is special.
1300 ENCODING("i16imm", ENCODING_IW)
1302 ENCODING("i32i8imm", ENCODING_IB)
1303 ENCODING("u32u8imm", ENCODING_IB)
1304 ENCODING("SSECC", ENCODING_IB)
1305 ENCODING("AVXCC", ENCODING_IB)
1306 ENCODING("AVX512RC", ENCODING_IB)
1307 ENCODING("i16imm", ENCODING_Iv)
1308 ENCODING("i16i8imm", ENCODING_IB)
1309 ENCODING("i32imm", ENCODING_Iv)
1310 ENCODING("i64i32imm", ENCODING_ID)
1311 ENCODING("i64i8imm", ENCODING_IB)
1312 ENCODING("i8imm", ENCODING_IB)
1313 // This is not a typo. Instructions like BLENDVPD put
1314 // register IDs in 8-bit immediates nowadays.
1315 ENCODING("FR32", ENCODING_IB)
1316 ENCODING("FR64", ENCODING_IB)
1317 ENCODING("VR128", ENCODING_IB)
1318 ENCODING("VR256", ENCODING_IB)
1319 ENCODING("FR32X", ENCODING_IB)
1320 ENCODING("FR64X", ENCODING_IB)
1321 ENCODING("VR128X", ENCODING_IB)
1322 ENCODING("VR256X", ENCODING_IB)
1323 ENCODING("VR512", ENCODING_IB)
1324 errs() << "Unhandled immediate encoding " << s << "\n";
1325 llvm_unreachable("Unhandled immediate encoding");
1328 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1329 (const std::string &s,
1330 bool hasOpSizePrefix) {
1331 ENCODING("RST", ENCODING_FP)
1332 ENCODING("GR16", ENCODING_RM)
1333 ENCODING("GR32", ENCODING_RM)
1334 ENCODING("GR32orGR64", ENCODING_RM)
1335 ENCODING("GR64", ENCODING_RM)
1336 ENCODING("GR8", ENCODING_RM)
1337 ENCODING("VR128", ENCODING_RM)
1338 ENCODING("VR128X", ENCODING_RM)
1339 ENCODING("FR64", ENCODING_RM)
1340 ENCODING("FR32", ENCODING_RM)
1341 ENCODING("FR64X", ENCODING_RM)
1342 ENCODING("FR32X", ENCODING_RM)
1343 ENCODING("VR64", ENCODING_RM)
1344 ENCODING("VR256", ENCODING_RM)
1345 ENCODING("VR256X", ENCODING_RM)
1346 ENCODING("VR512", ENCODING_RM)
1347 ENCODING("VK1", ENCODING_RM)
1348 ENCODING("VK8", ENCODING_RM)
1349 ENCODING("VK16", ENCODING_RM)
1350 errs() << "Unhandled R/M register encoding " << s << "\n";
1351 llvm_unreachable("Unhandled R/M register encoding");
1354 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1355 (const std::string &s,
1356 bool hasOpSizePrefix) {
1357 ENCODING("GR16", ENCODING_REG)
1358 ENCODING("GR32", ENCODING_REG)
1359 ENCODING("GR32orGR64", ENCODING_REG)
1360 ENCODING("GR64", ENCODING_REG)
1361 ENCODING("GR8", ENCODING_REG)
1362 ENCODING("VR128", ENCODING_REG)
1363 ENCODING("FR64", ENCODING_REG)
1364 ENCODING("FR32", ENCODING_REG)
1365 ENCODING("VR64", ENCODING_REG)
1366 ENCODING("SEGMENT_REG", ENCODING_REG)
1367 ENCODING("DEBUG_REG", ENCODING_REG)
1368 ENCODING("CONTROL_REG", ENCODING_REG)
1369 ENCODING("VR256", ENCODING_REG)
1370 ENCODING("VR256X", ENCODING_REG)
1371 ENCODING("VR128X", ENCODING_REG)
1372 ENCODING("FR64X", ENCODING_REG)
1373 ENCODING("FR32X", ENCODING_REG)
1374 ENCODING("VR512", ENCODING_REG)
1375 ENCODING("VK1", ENCODING_REG)
1376 ENCODING("VK8", ENCODING_REG)
1377 ENCODING("VK16", ENCODING_REG)
1378 ENCODING("VK1WM", ENCODING_REG)
1379 ENCODING("VK8WM", ENCODING_REG)
1380 ENCODING("VK16WM", ENCODING_REG)
1381 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1382 llvm_unreachable("Unhandled reg/opcode register encoding");
1385 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1386 (const std::string &s,
1387 bool hasOpSizePrefix) {
1388 ENCODING("GR32", ENCODING_VVVV)
1389 ENCODING("GR64", ENCODING_VVVV)
1390 ENCODING("FR32", ENCODING_VVVV)
1391 ENCODING("FR64", ENCODING_VVVV)
1392 ENCODING("VR128", ENCODING_VVVV)
1393 ENCODING("VR256", ENCODING_VVVV)
1394 ENCODING("FR32X", ENCODING_VVVV)
1395 ENCODING("FR64X", ENCODING_VVVV)
1396 ENCODING("VR128X", ENCODING_VVVV)
1397 ENCODING("VR256X", ENCODING_VVVV)
1398 ENCODING("VR512", ENCODING_VVVV)
1399 ENCODING("VK1", ENCODING_VVVV)
1400 ENCODING("VK8", ENCODING_VVVV)
1401 ENCODING("VK16", ENCODING_VVVV)
1402 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1403 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1406 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1407 (const std::string &s,
1408 bool hasOpSizePrefix) {
1409 ENCODING("VK1WM", ENCODING_WRITEMASK)
1410 ENCODING("VK8WM", ENCODING_WRITEMASK)
1411 ENCODING("VK16WM", ENCODING_WRITEMASK)
1412 errs() << "Unhandled mask register encoding " << s << "\n";
1413 llvm_unreachable("Unhandled mask register encoding");
1416 OperandEncoding RecognizableInstr::memoryEncodingFromString
1417 (const std::string &s,
1418 bool hasOpSizePrefix) {
1419 ENCODING("i16mem", ENCODING_RM)
1420 ENCODING("i32mem", ENCODING_RM)
1421 ENCODING("i64mem", ENCODING_RM)
1422 ENCODING("i8mem", ENCODING_RM)
1423 ENCODING("ssmem", ENCODING_RM)
1424 ENCODING("sdmem", ENCODING_RM)
1425 ENCODING("f128mem", ENCODING_RM)
1426 ENCODING("f256mem", ENCODING_RM)
1427 ENCODING("f512mem", ENCODING_RM)
1428 ENCODING("f64mem", ENCODING_RM)
1429 ENCODING("f32mem", ENCODING_RM)
1430 ENCODING("i128mem", ENCODING_RM)
1431 ENCODING("i256mem", ENCODING_RM)
1432 ENCODING("i512mem", ENCODING_RM)
1433 ENCODING("f80mem", ENCODING_RM)
1434 ENCODING("lea32mem", ENCODING_RM)
1435 ENCODING("lea64_32mem", ENCODING_RM)
1436 ENCODING("lea64mem", ENCODING_RM)
1437 ENCODING("opaque32mem", ENCODING_RM)
1438 ENCODING("opaque48mem", ENCODING_RM)
1439 ENCODING("opaque80mem", ENCODING_RM)
1440 ENCODING("opaque512mem", ENCODING_RM)
1441 ENCODING("vx32mem", ENCODING_RM)
1442 ENCODING("vy32mem", ENCODING_RM)
1443 ENCODING("vz32mem", ENCODING_RM)
1444 ENCODING("vx64mem", ENCODING_RM)
1445 ENCODING("vy64mem", ENCODING_RM)
1446 ENCODING("vy64xmem", ENCODING_RM)
1447 ENCODING("vz64mem", ENCODING_RM)
1448 errs() << "Unhandled memory encoding " << s << "\n";
1449 llvm_unreachable("Unhandled memory encoding");
1452 OperandEncoding RecognizableInstr::relocationEncodingFromString
1453 (const std::string &s,
1454 bool hasOpSizePrefix) {
1455 if(!hasOpSizePrefix) {
1456 // For instructions without an OpSize prefix, a declared 16-bit register or
1457 // immediate encoding is special.
1458 ENCODING("i16imm", ENCODING_IW)
1460 ENCODING("i16imm", ENCODING_Iv)
1461 ENCODING("i16i8imm", ENCODING_IB)
1462 ENCODING("i32imm", ENCODING_Iv)
1463 ENCODING("i32i8imm", ENCODING_IB)
1464 ENCODING("i64i32imm", ENCODING_ID)
1465 ENCODING("i64i8imm", ENCODING_IB)
1466 ENCODING("i8imm", ENCODING_IB)
1467 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1468 ENCODING("i16imm_pcrel", ENCODING_IW)
1469 ENCODING("i32imm_pcrel", ENCODING_ID)
1470 ENCODING("brtarget", ENCODING_Iv)
1471 ENCODING("brtarget8", ENCODING_IB)
1472 ENCODING("i64imm", ENCODING_IO)
1473 ENCODING("offset8", ENCODING_Ia)
1474 ENCODING("offset16", ENCODING_Ia)
1475 ENCODING("offset32", ENCODING_Ia)
1476 ENCODING("offset64", ENCODING_Ia)
1477 errs() << "Unhandled relocation encoding " << s << "\n";
1478 llvm_unreachable("Unhandled relocation encoding");
1481 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1482 (const std::string &s,
1483 bool hasOpSizePrefix) {
1484 ENCODING("GR32", ENCODING_Rv)
1485 ENCODING("GR64", ENCODING_RO)
1486 ENCODING("GR16", ENCODING_Rv)
1487 ENCODING("GR8", ENCODING_RB)
1488 ENCODING("GR16_NOAX", ENCODING_Rv)
1489 ENCODING("GR32_NOAX", ENCODING_Rv)
1490 ENCODING("GR64_NOAX", ENCODING_RO)
1491 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1492 llvm_unreachable("Unhandled opcode modifier encoding");