1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
80 // A clone of X86 since we can't depend on something that is generated.
96 MRMXr = 14, MRMXm = 15,
97 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
98 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
99 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
100 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
101 #define MAP(from, to) MRM_##from = to,
108 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6
112 PS = 1, PD = 2, XS = 3, XD = 4
116 VEX = 1, XOP = 2, EVEX = 3
120 OpSize16 = 1, OpSize32 = 2
124 AdSize16 = 1, AdSize32 = 2, AdSize64 = 3
128 using namespace X86Disassembler;
130 /// isRegFormat - Indicates whether a particular form requires the Mod field of
131 /// the ModR/M byte to be 0b11.
133 /// @param form - The form of the instruction.
134 /// @return - true if the form implies that Mod must be 0b11, false
136 static bool isRegFormat(uint8_t form) {
137 return (form == X86Local::MRMDestReg ||
138 form == X86Local::MRMSrcReg ||
139 form == X86Local::MRMXr ||
140 (form >= X86Local::MRM0r && form <= X86Local::MRM7r));
143 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
144 /// Useful for switch statements and the like.
146 /// @param init - A reference to the BitsInit to be decoded.
147 /// @return - The field, with the first bit in the BitsInit as the lowest
149 static uint8_t byteFromBitsInit(BitsInit &init) {
150 int width = init.getNumBits();
152 assert(width <= 8 && "Field is too large for uint8_t!");
159 for (index = 0; index < width; index++) {
160 if (static_cast<BitInit*>(init.getBit(index))->getValue())
169 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
170 /// name of the field.
172 /// @param rec - The record from which to extract the value.
173 /// @param name - The name of the field in the record.
174 /// @return - The field, as translated by byteFromBitsInit().
175 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
176 BitsInit* bits = rec->getValueAsBitsInit(name);
177 return byteFromBitsInit(*bits);
180 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
181 const CodeGenInstruction &insn,
186 Name = Rec->getName();
187 Spec = &tables.specForUID(UID);
189 if (!Rec->isSubClassOf("X86Inst")) {
190 ShouldBeEmitted = false;
194 OpPrefix = byteFromRec(Rec, "OpPrefixBits");
195 OpMap = byteFromRec(Rec, "OpMapBits");
196 Opcode = byteFromRec(Rec, "Opcode");
197 Form = byteFromRec(Rec, "FormBits");
198 Encoding = byteFromRec(Rec, "OpEncBits");
200 OpSize = byteFromRec(Rec, "OpSizeBits");
201 AdSize = byteFromRec(Rec, "AdSizeBits");
202 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
203 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V");
204 HasVEX_4VOp3 = Rec->getValueAsBit("hasVEX_4VOp3");
205 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
206 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
207 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
208 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
209 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
210 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
211 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
212 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
213 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
214 CD8_Scale = byteFromRec(Rec, "CD8_Scale");
216 Name = Rec->getName();
217 AsmString = Rec->getValueAsString("AsmString");
219 Operands = &insn.Operands.OperandList;
221 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
223 // Check for 64-bit inst which does not require REX
226 // FIXME: Is there some better way to check for In64BitMode?
227 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
228 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
229 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
230 Predicates[i]->getName().find("In32Bit") != Name.npos) {
234 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
240 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) {
241 ShouldBeEmitted = false;
245 // Special case since there is no attribute class for 64-bit and VEX
246 if (Name == "VMASKMOVDQU64") {
247 ShouldBeEmitted = false;
251 ShouldBeEmitted = true;
254 void RecognizableInstr::processInstr(DisassemblerTables &tables,
255 const CodeGenInstruction &insn,
258 // Ignore "asm parser only" instructions.
259 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
262 RecognizableInstr recogInstr(tables, insn, uid);
264 if (recogInstr.shouldBeEmitted()) {
265 recogInstr.emitInstructionSpecifier();
266 recogInstr.emitDecodePath(tables);
270 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
271 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
272 (HasEVEX_KZ ? n##_KZ : \
273 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
275 InstructionContext RecognizableInstr::insnContext() const {
276 InstructionContext insnContext;
278 if (Encoding == X86Local::EVEX) {
279 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
280 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
281 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
284 if (HasVEX_LPrefix && HasVEX_WPrefix) {
285 if (OpPrefix == X86Local::PD)
286 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
287 else if (OpPrefix == X86Local::XS)
288 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
289 else if (OpPrefix == X86Local::XD)
290 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
291 else if (OpPrefix == X86Local::PS)
292 insnContext = EVEX_KB(IC_EVEX_L_W);
294 errs() << "Instruction does not use a prefix: " << Name << "\n";
295 llvm_unreachable("Invalid prefix");
297 } else if (HasVEX_LPrefix) {
299 if (OpPrefix == X86Local::PD)
300 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
301 else if (OpPrefix == X86Local::XS)
302 insnContext = EVEX_KB(IC_EVEX_L_XS);
303 else if (OpPrefix == X86Local::XD)
304 insnContext = EVEX_KB(IC_EVEX_L_XD);
305 else if (OpPrefix == X86Local::PS)
306 insnContext = EVEX_KB(IC_EVEX_L);
308 errs() << "Instruction does not use a prefix: " << Name << "\n";
309 llvm_unreachable("Invalid prefix");
312 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
314 if (OpPrefix == X86Local::PD)
315 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
316 else if (OpPrefix == X86Local::XS)
317 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
318 else if (OpPrefix == X86Local::XD)
319 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
320 else if (OpPrefix == X86Local::PS)
321 insnContext = EVEX_KB(IC_EVEX_L2_W);
323 errs() << "Instruction does not use a prefix: " << Name << "\n";
324 llvm_unreachable("Invalid prefix");
326 } else if (HasEVEX_L2Prefix) {
328 if (OpPrefix == X86Local::PD)
329 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
330 else if (OpPrefix == X86Local::XD)
331 insnContext = EVEX_KB(IC_EVEX_L2_XD);
332 else if (OpPrefix == X86Local::XS)
333 insnContext = EVEX_KB(IC_EVEX_L2_XS);
334 else if (OpPrefix == X86Local::PS)
335 insnContext = EVEX_KB(IC_EVEX_L2);
337 errs() << "Instruction does not use a prefix: " << Name << "\n";
338 llvm_unreachable("Invalid prefix");
341 else if (HasVEX_WPrefix) {
343 if (OpPrefix == X86Local::PD)
344 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
345 else if (OpPrefix == X86Local::XS)
346 insnContext = EVEX_KB(IC_EVEX_W_XS);
347 else if (OpPrefix == X86Local::XD)
348 insnContext = EVEX_KB(IC_EVEX_W_XD);
349 else if (OpPrefix == X86Local::PS)
350 insnContext = EVEX_KB(IC_EVEX_W);
352 errs() << "Instruction does not use a prefix: " << Name << "\n";
353 llvm_unreachable("Invalid prefix");
357 else if (OpPrefix == X86Local::PD)
358 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
359 else if (OpPrefix == X86Local::XD)
360 insnContext = EVEX_KB(IC_EVEX_XD);
361 else if (OpPrefix == X86Local::XS)
362 insnContext = EVEX_KB(IC_EVEX_XS);
364 insnContext = EVEX_KB(IC_EVEX);
366 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) {
367 if (HasVEX_LPrefix && HasVEX_WPrefix) {
368 if (OpPrefix == X86Local::PD)
369 insnContext = IC_VEX_L_W_OPSIZE;
370 else if (OpPrefix == X86Local::XS)
371 insnContext = IC_VEX_L_W_XS;
372 else if (OpPrefix == X86Local::XD)
373 insnContext = IC_VEX_L_W_XD;
374 else if (OpPrefix == X86Local::PS)
375 insnContext = IC_VEX_L_W;
377 errs() << "Instruction does not use a prefix: " << Name << "\n";
378 llvm_unreachable("Invalid prefix");
380 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix)
381 insnContext = IC_VEX_L_OPSIZE;
382 else if (OpPrefix == X86Local::PD && HasVEX_WPrefix)
383 insnContext = IC_VEX_W_OPSIZE;
384 else if (OpPrefix == X86Local::PD)
385 insnContext = IC_VEX_OPSIZE;
386 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS)
387 insnContext = IC_VEX_L_XS;
388 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD)
389 insnContext = IC_VEX_L_XD;
390 else if (HasVEX_WPrefix && OpPrefix == X86Local::XS)
391 insnContext = IC_VEX_W_XS;
392 else if (HasVEX_WPrefix && OpPrefix == X86Local::XD)
393 insnContext = IC_VEX_W_XD;
394 else if (HasVEX_WPrefix && OpPrefix == X86Local::PS)
395 insnContext = IC_VEX_W;
396 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS)
397 insnContext = IC_VEX_L;
398 else if (OpPrefix == X86Local::XD)
399 insnContext = IC_VEX_XD;
400 else if (OpPrefix == X86Local::XS)
401 insnContext = IC_VEX_XS;
402 else if (OpPrefix == X86Local::PS)
403 insnContext = IC_VEX;
405 errs() << "Instruction does not use a prefix: " << Name << "\n";
406 llvm_unreachable("Invalid prefix");
408 } else if (Is64Bit || HasREX_WPrefix) {
409 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD))
410 insnContext = IC_64BIT_REXW_OPSIZE;
411 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
412 insnContext = IC_64BIT_XD_OPSIZE;
413 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
414 insnContext = IC_64BIT_XS_OPSIZE;
415 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
416 insnContext = IC_64BIT_OPSIZE;
417 else if (AdSize == X86Local::AdSize32)
418 insnContext = IC_64BIT_ADSIZE;
419 else if (HasREX_WPrefix && OpPrefix == X86Local::XS)
420 insnContext = IC_64BIT_REXW_XS;
421 else if (HasREX_WPrefix && OpPrefix == X86Local::XD)
422 insnContext = IC_64BIT_REXW_XD;
423 else if (OpPrefix == X86Local::XD)
424 insnContext = IC_64BIT_XD;
425 else if (OpPrefix == X86Local::XS)
426 insnContext = IC_64BIT_XS;
427 else if (HasREX_WPrefix)
428 insnContext = IC_64BIT_REXW;
430 insnContext = IC_64BIT;
432 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD)
433 insnContext = IC_XD_OPSIZE;
434 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS)
435 insnContext = IC_XS_OPSIZE;
436 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)
437 insnContext = IC_OPSIZE;
438 else if (AdSize == X86Local::AdSize16)
439 insnContext = IC_ADSIZE;
440 else if (OpPrefix == X86Local::XD)
442 else if (OpPrefix == X86Local::XS)
451 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) {
452 // The scaling factor for AVX512 compressed displacement encoding is an
453 // instruction attribute. Adjust the ModRM encoding type to include the
454 // scale for compressed displacement.
455 if (encoding != ENCODING_RM || CD8_Scale == 0)
457 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale));
458 assert(encoding <= ENCODING_RM_CD64 && "Invalid CDisp scaling");
461 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
462 unsigned &physicalOperandIndex,
463 unsigned &numPhysicalOperands,
464 const unsigned *operandMapping,
465 OperandEncoding (*encodingFromString)
469 if (physicalOperandIndex >= numPhysicalOperands)
472 assert(physicalOperandIndex < numPhysicalOperands);
475 while (operandMapping[operandIndex] != operandIndex) {
476 Spec->operands[operandIndex].encoding = ENCODING_DUP;
477 Spec->operands[operandIndex].type =
478 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
482 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
484 OperandEncoding encoding = encodingFromString(typeName, OpSize);
485 // Adjust the encoding type for an operand based on the instruction.
486 adjustOperandEncoding(encoding);
487 Spec->operands[operandIndex].encoding = encoding;
488 Spec->operands[operandIndex].type = typeFromString(typeName,
489 HasREX_WPrefix, OpSize);
492 ++physicalOperandIndex;
495 void RecognizableInstr::emitInstructionSpecifier() {
498 Spec->insnContext = insnContext();
500 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
502 unsigned numOperands = OperandList.size();
503 unsigned numPhysicalOperands = 0;
505 // operandMapping maps from operands in OperandList to their originals.
506 // If operandMapping[i] != i, then the entry is a duplicate.
507 unsigned operandMapping[X86_MAX_OPERANDS];
508 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
510 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
511 if (OperandList[operandIndex].Constraints.size()) {
512 const CGIOperandList::ConstraintInfo &Constraint =
513 OperandList[operandIndex].Constraints[0];
514 if (Constraint.isTied()) {
515 operandMapping[operandIndex] = operandIndex;
516 operandMapping[Constraint.getTiedOperand()] = operandIndex;
518 ++numPhysicalOperands;
519 operandMapping[operandIndex] = operandIndex;
522 ++numPhysicalOperands;
523 operandMapping[operandIndex] = operandIndex;
527 #define HANDLE_OPERAND(class) \
528 handleOperand(false, \
530 physicalOperandIndex, \
531 numPhysicalOperands, \
533 class##EncodingFromString);
535 #define HANDLE_OPTIONAL(class) \
536 handleOperand(true, \
538 physicalOperandIndex, \
539 numPhysicalOperands, \
541 class##EncodingFromString);
543 // operandIndex should always be < numOperands
544 unsigned operandIndex = 0;
545 // physicalOperandIndex should always be < numPhysicalOperands
546 unsigned physicalOperandIndex = 0;
548 // Given the set of prefix bits, how many additional operands does the
550 unsigned additionalOperands = 0;
551 if (HasVEX_4V || HasVEX_4VOp3)
552 ++additionalOperands;
554 ++additionalOperands;
557 default: llvm_unreachable("Unhandled form");
558 case X86Local::RawFrmSrc:
559 HANDLE_OPERAND(relocation);
561 case X86Local::RawFrmDst:
562 HANDLE_OPERAND(relocation);
564 case X86Local::RawFrmDstSrc:
565 HANDLE_OPERAND(relocation);
566 HANDLE_OPERAND(relocation);
568 case X86Local::RawFrm:
569 // Operand 1 (optional) is an address or immediate.
570 // Operand 2 (optional) is an immediate.
571 assert(numPhysicalOperands <= 2 &&
572 "Unexpected number of operands for RawFrm");
573 HANDLE_OPTIONAL(relocation)
574 HANDLE_OPTIONAL(immediate)
576 case X86Local::RawFrmMemOffs:
577 // Operand 1 is an address.
578 HANDLE_OPERAND(relocation);
580 case X86Local::AddRegFrm:
581 // Operand 1 is added to the opcode.
582 // Operand 2 (optional) is an address.
583 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
584 "Unexpected number of operands for AddRegFrm");
585 HANDLE_OPERAND(opcodeModifier)
586 HANDLE_OPTIONAL(relocation)
588 case X86Local::MRMDestReg:
589 // Operand 1 is a register operand in the R/M field.
590 // - In AVX512 there may be a mask operand here -
591 // Operand 2 is a register operand in the Reg/Opcode field.
592 // - In AVX, there is a register operand in the VEX.vvvv field here -
593 // Operand 3 (optional) is an immediate.
594 assert(numPhysicalOperands >= 2 + additionalOperands &&
595 numPhysicalOperands <= 3 + additionalOperands &&
596 "Unexpected number of operands for MRMDestRegFrm");
598 HANDLE_OPERAND(rmRegister)
600 HANDLE_OPERAND(writemaskRegister)
603 // FIXME: In AVX, the register below becomes the one encoded
604 // in ModRMVEX and the one above the one in the VEX.VVVV field
605 HANDLE_OPERAND(vvvvRegister)
607 HANDLE_OPERAND(roRegister)
608 HANDLE_OPTIONAL(immediate)
610 case X86Local::MRMDestMem:
611 // Operand 1 is a memory operand (possibly SIB-extended)
612 // Operand 2 is a register operand in the Reg/Opcode field.
613 // - In AVX, there is a register operand in the VEX.vvvv field here -
614 // Operand 3 (optional) is an immediate.
615 assert(numPhysicalOperands >= 2 + additionalOperands &&
616 numPhysicalOperands <= 3 + additionalOperands &&
617 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
619 HANDLE_OPERAND(memory)
622 HANDLE_OPERAND(writemaskRegister)
625 // FIXME: In AVX, the register below becomes the one encoded
626 // in ModRMVEX and the one above the one in the VEX.VVVV field
627 HANDLE_OPERAND(vvvvRegister)
629 HANDLE_OPERAND(roRegister)
630 HANDLE_OPTIONAL(immediate)
632 case X86Local::MRMSrcReg:
633 // Operand 1 is a register operand in the Reg/Opcode field.
634 // Operand 2 is a register operand in the R/M field.
635 // - In AVX, there is a register operand in the VEX.vvvv field here -
636 // Operand 3 (optional) is an immediate.
637 // Operand 4 (optional) is an immediate.
639 assert(numPhysicalOperands >= 2 + additionalOperands &&
640 numPhysicalOperands <= 4 + additionalOperands &&
641 "Unexpected number of operands for MRMSrcRegFrm");
643 HANDLE_OPERAND(roRegister)
646 HANDLE_OPERAND(writemaskRegister)
649 // FIXME: In AVX, the register below becomes the one encoded
650 // in ModRMVEX and the one above the one in the VEX.VVVV field
651 HANDLE_OPERAND(vvvvRegister)
654 HANDLE_OPERAND(immediate)
656 HANDLE_OPERAND(rmRegister)
659 HANDLE_OPERAND(vvvvRegister)
661 if (!HasMemOp4Prefix)
662 HANDLE_OPTIONAL(immediate)
663 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
664 HANDLE_OPTIONAL(immediate)
666 case X86Local::MRMSrcMem:
667 // Operand 1 is a register operand in the Reg/Opcode field.
668 // Operand 2 is a memory operand (possibly SIB-extended)
669 // - In AVX, there is a register operand in the VEX.vvvv field here -
670 // Operand 3 (optional) is an immediate.
672 assert(numPhysicalOperands >= 2 + additionalOperands &&
673 numPhysicalOperands <= 4 + additionalOperands &&
674 "Unexpected number of operands for MRMSrcMemFrm");
676 HANDLE_OPERAND(roRegister)
679 HANDLE_OPERAND(writemaskRegister)
682 // FIXME: In AVX, the register below becomes the one encoded
683 // in ModRMVEX and the one above the one in the VEX.VVVV field
684 HANDLE_OPERAND(vvvvRegister)
687 HANDLE_OPERAND(immediate)
689 HANDLE_OPERAND(memory)
692 HANDLE_OPERAND(vvvvRegister)
694 if (!HasMemOp4Prefix)
695 HANDLE_OPTIONAL(immediate)
696 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
698 case X86Local::MRMXr:
699 case X86Local::MRM0r:
700 case X86Local::MRM1r:
701 case X86Local::MRM2r:
702 case X86Local::MRM3r:
703 case X86Local::MRM4r:
704 case X86Local::MRM5r:
705 case X86Local::MRM6r:
706 case X86Local::MRM7r:
707 // Operand 1 is a register operand in the R/M field.
708 // Operand 2 (optional) is an immediate or relocation.
709 // Operand 3 (optional) is an immediate.
710 assert(numPhysicalOperands >= 0 + additionalOperands &&
711 numPhysicalOperands <= 3 + additionalOperands &&
712 "Unexpected number of operands for MRMnr");
715 HANDLE_OPERAND(vvvvRegister)
718 HANDLE_OPERAND(writemaskRegister)
719 HANDLE_OPTIONAL(rmRegister)
720 HANDLE_OPTIONAL(relocation)
721 HANDLE_OPTIONAL(immediate)
723 case X86Local::MRMXm:
724 case X86Local::MRM0m:
725 case X86Local::MRM1m:
726 case X86Local::MRM2m:
727 case X86Local::MRM3m:
728 case X86Local::MRM4m:
729 case X86Local::MRM5m:
730 case X86Local::MRM6m:
731 case X86Local::MRM7m:
732 // Operand 1 is a memory operand (possibly SIB-extended)
733 // Operand 2 (optional) is an immediate or relocation.
734 assert(numPhysicalOperands >= 1 + additionalOperands &&
735 numPhysicalOperands <= 2 + additionalOperands &&
736 "Unexpected number of operands for MRMnm");
739 HANDLE_OPERAND(vvvvRegister)
741 HANDLE_OPERAND(writemaskRegister)
742 HANDLE_OPERAND(memory)
743 HANDLE_OPTIONAL(relocation)
745 case X86Local::RawFrmImm8:
746 // operand 1 is a 16-bit immediate
747 // operand 2 is an 8-bit immediate
748 assert(numPhysicalOperands == 2 &&
749 "Unexpected number of operands for X86Local::RawFrmImm8");
750 HANDLE_OPERAND(immediate)
751 HANDLE_OPERAND(immediate)
753 case X86Local::RawFrmImm16:
754 // operand 1 is a 16-bit immediate
755 // operand 2 is a 16-bit immediate
756 HANDLE_OPERAND(immediate)
757 HANDLE_OPERAND(immediate)
759 case X86Local::MRM_F8:
760 if (Opcode == 0xc6) {
761 assert(numPhysicalOperands == 1 &&
762 "Unexpected number of operands for X86Local::MRM_F8");
763 HANDLE_OPERAND(immediate)
764 } else if (Opcode == 0xc7) {
765 assert(numPhysicalOperands == 1 &&
766 "Unexpected number of operands for X86Local::MRM_F8");
767 HANDLE_OPERAND(relocation)
770 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2:
771 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8:
772 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB:
773 case X86Local::MRM_CF: case X86Local::MRM_D0: case X86Local::MRM_D1:
774 case X86Local::MRM_D4: case X86Local::MRM_D5: case X86Local::MRM_D6:
775 case X86Local::MRM_D7: case X86Local::MRM_D8: case X86Local::MRM_D9:
776 case X86Local::MRM_DA: case X86Local::MRM_DB: case X86Local::MRM_DC:
777 case X86Local::MRM_DD: case X86Local::MRM_DE: case X86Local::MRM_DF:
778 case X86Local::MRM_E0: case X86Local::MRM_E1: case X86Local::MRM_E2:
779 case X86Local::MRM_E3: case X86Local::MRM_E4: case X86Local::MRM_E5:
780 case X86Local::MRM_E8: case X86Local::MRM_E9: case X86Local::MRM_EA:
781 case X86Local::MRM_EB: case X86Local::MRM_EC: case X86Local::MRM_ED:
782 case X86Local::MRM_EE: case X86Local::MRM_F0: case X86Local::MRM_F1:
783 case X86Local::MRM_F2: case X86Local::MRM_F3: case X86Local::MRM_F4:
784 case X86Local::MRM_F5: case X86Local::MRM_F6: case X86Local::MRM_F7:
785 case X86Local::MRM_F9: case X86Local::MRM_FA: case X86Local::MRM_FB:
786 case X86Local::MRM_FC: case X86Local::MRM_FD: case X86Local::MRM_FE:
787 case X86Local::MRM_FF:
792 #undef HANDLE_OPERAND
793 #undef HANDLE_OPTIONAL
796 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
797 // Special cases where the LLVM tables are not complete
799 #define MAP(from, to) \
800 case X86Local::MRM_##from: \
801 filter = new ExactFilter(0x##from); \
804 OpcodeType opcodeType = (OpcodeType)-1;
806 ModRMFilter* filter = nullptr;
807 uint8_t opcodeToSet = 0;
810 default: llvm_unreachable("Invalid map!");
819 default: llvm_unreachable("Unexpected map!");
820 case X86Local::OB: opcodeType = ONEBYTE; break;
821 case X86Local::TB: opcodeType = TWOBYTE; break;
822 case X86Local::T8: opcodeType = THREEBYTE_38; break;
823 case X86Local::TA: opcodeType = THREEBYTE_3A; break;
824 case X86Local::XOP8: opcodeType = XOP8_MAP; break;
825 case X86Local::XOP9: opcodeType = XOP9_MAP; break;
826 case X86Local::XOPA: opcodeType = XOPA_MAP; break;
831 filter = new DumbFilter();
833 case X86Local::MRMDestReg: case X86Local::MRMDestMem:
834 case X86Local::MRMSrcReg: case X86Local::MRMSrcMem:
835 case X86Local::MRMXr: case X86Local::MRMXm:
836 filter = new ModFilter(isRegFormat(Form));
838 case X86Local::MRM0r: case X86Local::MRM1r:
839 case X86Local::MRM2r: case X86Local::MRM3r:
840 case X86Local::MRM4r: case X86Local::MRM5r:
841 case X86Local::MRM6r: case X86Local::MRM7r:
842 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
844 case X86Local::MRM0m: case X86Local::MRM1m:
845 case X86Local::MRM2m: case X86Local::MRM3m:
846 case X86Local::MRM4m: case X86Local::MRM5m:
847 case X86Local::MRM6m: case X86Local::MRM7m:
848 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
853 opcodeToSet = Opcode;
857 assert(opcodeType != (OpcodeType)-1 &&
858 "Opcode type not set");
859 assert(filter && "Filter not set");
861 if (Form == X86Local::AddRegFrm) {
862 assert(((opcodeToSet & 7) == 0) &&
863 "ADDREG_FRM opcode not aligned");
865 uint8_t currentOpcode;
867 for (currentOpcode = opcodeToSet;
868 currentOpcode < opcodeToSet + 8;
870 tables.setTableFields(opcodeType,
874 UID, Is32Bit, IgnoresVEX_L);
876 tables.setTableFields(opcodeType,
880 UID, Is32Bit, IgnoresVEX_L);
888 #define TYPE(str, type) if (s == str) return type;
889 OperandType RecognizableInstr::typeFromString(const std::string &s,
893 // For instructions with a REX_W prefix, a declared 32-bit register encoding
895 TYPE("GR32", TYPE_R32)
897 if(OpSize == X86Local::OpSize16) {
898 // For OpSize16 instructions, a declared 16-bit register or
899 // immediate encoding is special.
900 TYPE("GR16", TYPE_Rv)
901 TYPE("i16imm", TYPE_IMMv)
902 } else if(OpSize == X86Local::OpSize32) {
903 // For OpSize32 instructions, a declared 32-bit register or
904 // immediate encoding is special.
905 TYPE("GR32", TYPE_Rv)
907 TYPE("i16mem", TYPE_Mv)
908 TYPE("i16imm", TYPE_IMM16)
909 TYPE("i16i8imm", TYPE_IMMv)
910 TYPE("GR16", TYPE_R16)
911 TYPE("i32mem", TYPE_Mv)
912 TYPE("i32imm", TYPE_IMMv)
913 TYPE("i32i8imm", TYPE_IMM32)
914 TYPE("GR32", TYPE_R32)
915 TYPE("GR32orGR64", TYPE_R32)
916 TYPE("i64mem", TYPE_Mv)
917 TYPE("i64i32imm", TYPE_IMM64)
918 TYPE("i64i8imm", TYPE_IMM64)
919 TYPE("GR64", TYPE_R64)
920 TYPE("i8mem", TYPE_M8)
921 TYPE("i8imm", TYPE_IMM8)
923 TYPE("VR128", TYPE_XMM128)
924 TYPE("VR128X", TYPE_XMM128)
925 TYPE("f128mem", TYPE_M128)
926 TYPE("f256mem", TYPE_M256)
927 TYPE("f512mem", TYPE_M512)
928 TYPE("FR64", TYPE_XMM64)
929 TYPE("FR64X", TYPE_XMM64)
930 TYPE("f64mem", TYPE_M64FP)
931 TYPE("sdmem", TYPE_M64FP)
932 TYPE("FR32", TYPE_XMM32)
933 TYPE("FR32X", TYPE_XMM32)
934 TYPE("f32mem", TYPE_M32FP)
935 TYPE("ssmem", TYPE_M32FP)
937 TYPE("i128mem", TYPE_M128)
938 TYPE("i256mem", TYPE_M256)
939 TYPE("i512mem", TYPE_M512)
940 TYPE("i64i32imm_pcrel", TYPE_REL64)
941 TYPE("i16imm_pcrel", TYPE_REL16)
942 TYPE("i32imm_pcrel", TYPE_REL32)
943 TYPE("SSECC", TYPE_IMM3)
944 TYPE("AVXCC", TYPE_IMM5)
945 TYPE("AVX512RC", TYPE_IMM32)
946 TYPE("brtarget", TYPE_RELv)
947 TYPE("uncondbrtarget", TYPE_RELv)
948 TYPE("brtarget8", TYPE_REL8)
949 TYPE("f80mem", TYPE_M80FP)
950 TYPE("lea32mem", TYPE_LEA)
951 TYPE("lea64_32mem", TYPE_LEA)
952 TYPE("lea64mem", TYPE_LEA)
953 TYPE("VR64", TYPE_MM64)
954 TYPE("i64imm", TYPE_IMMv)
955 TYPE("opaque32mem", TYPE_M1616)
956 TYPE("opaque48mem", TYPE_M1632)
957 TYPE("opaque80mem", TYPE_M1664)
958 TYPE("opaque512mem", TYPE_M512)
959 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
960 TYPE("DEBUG_REG", TYPE_DEBUGREG)
961 TYPE("CONTROL_REG", TYPE_CONTROLREG)
962 TYPE("srcidx8", TYPE_SRCIDX8)
963 TYPE("srcidx16", TYPE_SRCIDX16)
964 TYPE("srcidx32", TYPE_SRCIDX32)
965 TYPE("srcidx64", TYPE_SRCIDX64)
966 TYPE("dstidx8", TYPE_DSTIDX8)
967 TYPE("dstidx16", TYPE_DSTIDX16)
968 TYPE("dstidx32", TYPE_DSTIDX32)
969 TYPE("dstidx64", TYPE_DSTIDX64)
970 TYPE("offset8", TYPE_MOFFS8)
971 TYPE("offset16", TYPE_MOFFS16)
972 TYPE("offset32", TYPE_MOFFS32)
973 TYPE("offset64", TYPE_MOFFS64)
974 TYPE("VR256", TYPE_XMM256)
975 TYPE("VR256X", TYPE_XMM256)
976 TYPE("VR512", TYPE_XMM512)
977 TYPE("VK1", TYPE_VK1)
978 TYPE("VK1WM", TYPE_VK1)
979 TYPE("VK2", TYPE_VK2)
980 TYPE("VK2WM", TYPE_VK2)
981 TYPE("VK4", TYPE_VK4)
982 TYPE("VK4WM", TYPE_VK4)
983 TYPE("VK8", TYPE_VK8)
984 TYPE("VK8WM", TYPE_VK8)
985 TYPE("VK16", TYPE_VK16)
986 TYPE("VK16WM", TYPE_VK16)
987 TYPE("VK32", TYPE_VK32)
988 TYPE("VK32WM", TYPE_VK32)
989 TYPE("VK64", TYPE_VK64)
990 TYPE("VK64WM", TYPE_VK64)
991 TYPE("GR16_NOAX", TYPE_Rv)
992 TYPE("GR32_NOAX", TYPE_Rv)
993 TYPE("GR64_NOAX", TYPE_R64)
994 TYPE("vx32mem", TYPE_M32)
995 TYPE("vy32mem", TYPE_M32)
996 TYPE("vz32mem", TYPE_M32)
997 TYPE("vx64mem", TYPE_M64)
998 TYPE("vy64mem", TYPE_M64)
999 TYPE("vy64xmem", TYPE_M64)
1000 TYPE("vz64mem", TYPE_M64)
1001 errs() << "Unhandled type string " << s << "\n";
1002 llvm_unreachable("Unhandled type string");
1006 #define ENCODING(str, encoding) if (s == str) return encoding;
1008 RecognizableInstr::immediateEncodingFromString(const std::string &s,
1010 if(OpSize != X86Local::OpSize16) {
1011 // For instructions without an OpSize prefix, a declared 16-bit register or
1012 // immediate encoding is special.
1013 ENCODING("i16imm", ENCODING_IW)
1015 ENCODING("i32i8imm", ENCODING_IB)
1016 ENCODING("SSECC", ENCODING_IB)
1017 ENCODING("AVXCC", ENCODING_IB)
1018 ENCODING("AVX512RC", ENCODING_IB)
1019 ENCODING("i16imm", ENCODING_Iv)
1020 ENCODING("i16i8imm", ENCODING_IB)
1021 ENCODING("i32imm", ENCODING_Iv)
1022 ENCODING("i64i32imm", ENCODING_ID)
1023 ENCODING("i64i8imm", ENCODING_IB)
1024 ENCODING("i8imm", ENCODING_IB)
1025 // This is not a typo. Instructions like BLENDVPD put
1026 // register IDs in 8-bit immediates nowadays.
1027 ENCODING("FR32", ENCODING_IB)
1028 ENCODING("FR64", ENCODING_IB)
1029 ENCODING("VR128", ENCODING_IB)
1030 ENCODING("VR256", ENCODING_IB)
1031 ENCODING("FR32X", ENCODING_IB)
1032 ENCODING("FR64X", ENCODING_IB)
1033 ENCODING("VR128X", ENCODING_IB)
1034 ENCODING("VR256X", ENCODING_IB)
1035 ENCODING("VR512", ENCODING_IB)
1036 errs() << "Unhandled immediate encoding " << s << "\n";
1037 llvm_unreachable("Unhandled immediate encoding");
1041 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s,
1043 ENCODING("RST", ENCODING_FP)
1044 ENCODING("GR16", ENCODING_RM)
1045 ENCODING("GR32", ENCODING_RM)
1046 ENCODING("GR32orGR64", ENCODING_RM)
1047 ENCODING("GR64", ENCODING_RM)
1048 ENCODING("GR8", ENCODING_RM)
1049 ENCODING("VR128", ENCODING_RM)
1050 ENCODING("VR128X", ENCODING_RM)
1051 ENCODING("FR64", ENCODING_RM)
1052 ENCODING("FR32", ENCODING_RM)
1053 ENCODING("FR64X", ENCODING_RM)
1054 ENCODING("FR32X", ENCODING_RM)
1055 ENCODING("VR64", ENCODING_RM)
1056 ENCODING("VR256", ENCODING_RM)
1057 ENCODING("VR256X", ENCODING_RM)
1058 ENCODING("VR512", ENCODING_RM)
1059 ENCODING("VK1", ENCODING_RM)
1060 ENCODING("VK8", ENCODING_RM)
1061 ENCODING("VK16", ENCODING_RM)
1062 ENCODING("VK32", ENCODING_RM)
1063 ENCODING("VK64", ENCODING_RM)
1064 errs() << "Unhandled R/M register encoding " << s << "\n";
1065 llvm_unreachable("Unhandled R/M register encoding");
1069 RecognizableInstr::roRegisterEncodingFromString(const std::string &s,
1071 ENCODING("GR16", ENCODING_REG)
1072 ENCODING("GR32", ENCODING_REG)
1073 ENCODING("GR32orGR64", ENCODING_REG)
1074 ENCODING("GR64", ENCODING_REG)
1075 ENCODING("GR8", ENCODING_REG)
1076 ENCODING("VR128", ENCODING_REG)
1077 ENCODING("FR64", ENCODING_REG)
1078 ENCODING("FR32", ENCODING_REG)
1079 ENCODING("VR64", ENCODING_REG)
1080 ENCODING("SEGMENT_REG", ENCODING_REG)
1081 ENCODING("DEBUG_REG", ENCODING_REG)
1082 ENCODING("CONTROL_REG", ENCODING_REG)
1083 ENCODING("VR256", ENCODING_REG)
1084 ENCODING("VR256X", ENCODING_REG)
1085 ENCODING("VR128X", ENCODING_REG)
1086 ENCODING("FR64X", ENCODING_REG)
1087 ENCODING("FR32X", ENCODING_REG)
1088 ENCODING("VR512", ENCODING_REG)
1089 ENCODING("VK1", ENCODING_REG)
1090 ENCODING("VK2", ENCODING_REG)
1091 ENCODING("VK4", ENCODING_REG)
1092 ENCODING("VK8", ENCODING_REG)
1093 ENCODING("VK16", ENCODING_REG)
1094 ENCODING("VK32", ENCODING_REG)
1095 ENCODING("VK64", ENCODING_REG)
1096 ENCODING("VK1WM", ENCODING_REG)
1097 ENCODING("VK8WM", ENCODING_REG)
1098 ENCODING("VK16WM", ENCODING_REG)
1099 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1100 llvm_unreachable("Unhandled reg/opcode register encoding");
1104 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s,
1106 ENCODING("GR32", ENCODING_VVVV)
1107 ENCODING("GR64", ENCODING_VVVV)
1108 ENCODING("FR32", ENCODING_VVVV)
1109 ENCODING("FR64", ENCODING_VVVV)
1110 ENCODING("VR128", ENCODING_VVVV)
1111 ENCODING("VR256", ENCODING_VVVV)
1112 ENCODING("FR32X", ENCODING_VVVV)
1113 ENCODING("FR64X", ENCODING_VVVV)
1114 ENCODING("VR128X", ENCODING_VVVV)
1115 ENCODING("VR256X", ENCODING_VVVV)
1116 ENCODING("VR512", ENCODING_VVVV)
1117 ENCODING("VK1", ENCODING_VVVV)
1118 ENCODING("VK2", ENCODING_VVVV)
1119 ENCODING("VK4", ENCODING_VVVV)
1120 ENCODING("VK8", ENCODING_VVVV)
1121 ENCODING("VK16", ENCODING_VVVV)
1122 ENCODING("VK32", ENCODING_VVVV)
1123 ENCODING("VK64", ENCODING_VVVV)
1124 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1125 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1129 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s,
1131 ENCODING("VK1WM", ENCODING_WRITEMASK)
1132 ENCODING("VK2WM", ENCODING_WRITEMASK)
1133 ENCODING("VK4WM", ENCODING_WRITEMASK)
1134 ENCODING("VK8WM", ENCODING_WRITEMASK)
1135 ENCODING("VK16WM", ENCODING_WRITEMASK)
1136 ENCODING("VK32WM", ENCODING_WRITEMASK)
1137 ENCODING("VK64WM", ENCODING_WRITEMASK)
1138 errs() << "Unhandled mask register encoding " << s << "\n";
1139 llvm_unreachable("Unhandled mask register encoding");
1143 RecognizableInstr::memoryEncodingFromString(const std::string &s,
1145 ENCODING("i16mem", ENCODING_RM)
1146 ENCODING("i32mem", ENCODING_RM)
1147 ENCODING("i64mem", ENCODING_RM)
1148 ENCODING("i8mem", ENCODING_RM)
1149 ENCODING("ssmem", ENCODING_RM)
1150 ENCODING("sdmem", ENCODING_RM)
1151 ENCODING("f128mem", ENCODING_RM)
1152 ENCODING("f256mem", ENCODING_RM)
1153 ENCODING("f512mem", ENCODING_RM)
1154 ENCODING("f64mem", ENCODING_RM)
1155 ENCODING("f32mem", ENCODING_RM)
1156 ENCODING("i128mem", ENCODING_RM)
1157 ENCODING("i256mem", ENCODING_RM)
1158 ENCODING("i512mem", ENCODING_RM)
1159 ENCODING("f80mem", ENCODING_RM)
1160 ENCODING("lea32mem", ENCODING_RM)
1161 ENCODING("lea64_32mem", ENCODING_RM)
1162 ENCODING("lea64mem", ENCODING_RM)
1163 ENCODING("opaque32mem", ENCODING_RM)
1164 ENCODING("opaque48mem", ENCODING_RM)
1165 ENCODING("opaque80mem", ENCODING_RM)
1166 ENCODING("opaque512mem", ENCODING_RM)
1167 ENCODING("vx32mem", ENCODING_RM)
1168 ENCODING("vy32mem", ENCODING_RM)
1169 ENCODING("vz32mem", ENCODING_RM)
1170 ENCODING("vx64mem", ENCODING_RM)
1171 ENCODING("vy64mem", ENCODING_RM)
1172 ENCODING("vy64xmem", ENCODING_RM)
1173 ENCODING("vz64mem", ENCODING_RM)
1174 errs() << "Unhandled memory encoding " << s << "\n";
1175 llvm_unreachable("Unhandled memory encoding");
1179 RecognizableInstr::relocationEncodingFromString(const std::string &s,
1181 if(OpSize != X86Local::OpSize16) {
1182 // For instructions without an OpSize prefix, a declared 16-bit register or
1183 // immediate encoding is special.
1184 ENCODING("i16imm", ENCODING_IW)
1186 ENCODING("i16imm", ENCODING_Iv)
1187 ENCODING("i16i8imm", ENCODING_IB)
1188 ENCODING("i32imm", ENCODING_Iv)
1189 ENCODING("i32i8imm", ENCODING_IB)
1190 ENCODING("i64i32imm", ENCODING_ID)
1191 ENCODING("i64i8imm", ENCODING_IB)
1192 ENCODING("i8imm", ENCODING_IB)
1193 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1194 ENCODING("i16imm_pcrel", ENCODING_IW)
1195 ENCODING("i32imm_pcrel", ENCODING_ID)
1196 ENCODING("brtarget", ENCODING_Iv)
1197 ENCODING("brtarget8", ENCODING_IB)
1198 ENCODING("i64imm", ENCODING_IO)
1199 ENCODING("offset8", ENCODING_Ia)
1200 ENCODING("offset16", ENCODING_Ia)
1201 ENCODING("offset32", ENCODING_Ia)
1202 ENCODING("offset64", ENCODING_Ia)
1203 ENCODING("srcidx8", ENCODING_SI)
1204 ENCODING("srcidx16", ENCODING_SI)
1205 ENCODING("srcidx32", ENCODING_SI)
1206 ENCODING("srcidx64", ENCODING_SI)
1207 ENCODING("dstidx8", ENCODING_DI)
1208 ENCODING("dstidx16", ENCODING_DI)
1209 ENCODING("dstidx32", ENCODING_DI)
1210 ENCODING("dstidx64", ENCODING_DI)
1211 errs() << "Unhandled relocation encoding " << s << "\n";
1212 llvm_unreachable("Unhandled relocation encoding");
1216 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s,
1218 ENCODING("GR32", ENCODING_Rv)
1219 ENCODING("GR64", ENCODING_RO)
1220 ENCODING("GR16", ENCODING_Rv)
1221 ENCODING("GR8", ENCODING_RB)
1222 ENCODING("GR16_NOAX", ENCODING_Rv)
1223 ENCODING("GR32_NOAX", ENCODING_Rv)
1224 ENCODING("GR64_NOAX", ENCODING_RO)
1225 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1226 llvm_unreachable("Unhandled opcode modifier encoding");