1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
41 // A clone of X86 since we can't depend on something that is generated.
51 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
56 #define MAP(from, to) MRM_##from = to,
67 D8 = 3, D9 = 4, DA = 5, DB = 6,
68 DC = 7, DD = 8, DE = 9, DF = 10,
71 A6 = 15, A7 = 16, TF = 17
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
92 #define ONE_BYTE_EXTENSION_TABLES \
100 EXTENSION_TABLE(c6) \
101 EXTENSION_TABLE(c7) \
102 EXTENSION_TABLE(d0) \
103 EXTENSION_TABLE(d1) \
104 EXTENSION_TABLE(d2) \
105 EXTENSION_TABLE(d3) \
106 EXTENSION_TABLE(f6) \
107 EXTENSION_TABLE(f7) \
108 EXTENSION_TABLE(fe) \
111 #define TWO_BYTE_EXTENSION_TABLES \
112 EXTENSION_TABLE(00) \
113 EXTENSION_TABLE(01) \
114 EXTENSION_TABLE(18) \
115 EXTENSION_TABLE(71) \
116 EXTENSION_TABLE(72) \
117 EXTENSION_TABLE(73) \
118 EXTENSION_TABLE(ae) \
119 EXTENSION_TABLE(ba) \
122 #define THREE_BYTE_38_EXTENSION_TABLES \
125 using namespace X86Disassembler;
127 /// needsModRMForDecode - Indicates whether a particular instruction requires a
128 /// ModR/M byte for the instruction to be properly decoded. For example, a
129 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
132 /// @param form - The form of the instruction.
133 /// @return - true if the form implies that a ModR/M byte is required, false
135 static bool needsModRMForDecode(uint8_t form) {
136 if (form == X86Local::MRMDestReg ||
137 form == X86Local::MRMDestMem ||
138 form == X86Local::MRMSrcReg ||
139 form == X86Local::MRMSrcMem ||
140 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
141 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
147 /// isRegFormat - Indicates whether a particular form requires the Mod field of
148 /// the ModR/M byte to be 0b11.
150 /// @param form - The form of the instruction.
151 /// @return - true if the form implies that Mod must be 0b11, false
153 static bool isRegFormat(uint8_t form) {
154 if (form == X86Local::MRMDestReg ||
155 form == X86Local::MRMSrcReg ||
156 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
162 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
163 /// Useful for switch statements and the like.
165 /// @param init - A reference to the BitsInit to be decoded.
166 /// @return - The field, with the first bit in the BitsInit as the lowest
168 static uint8_t byteFromBitsInit(BitsInit &init) {
169 int width = init.getNumBits();
171 assert(width <= 8 && "Field is too large for uint8_t!");
178 for (index = 0; index < width; index++) {
179 if (static_cast<BitInit*>(init.getBit(index))->getValue())
188 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
189 /// name of the field.
191 /// @param rec - The record from which to extract the value.
192 /// @param name - The name of the field in the record.
193 /// @return - The field, as translated by byteFromBitsInit().
194 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
195 BitsInit* bits = rec->getValueAsBitsInit(name);
196 return byteFromBitsInit(*bits);
199 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
200 const CodeGenInstruction &insn,
205 Name = Rec->getName();
206 Spec = &tables.specForUID(UID);
208 if (!Rec->isSubClassOf("X86Inst")) {
209 ShouldBeEmitted = false;
213 Prefix = byteFromRec(Rec, "Prefix");
214 Opcode = byteFromRec(Rec, "Opcode");
215 Form = byteFromRec(Rec, "FormBits");
216 SegOvr = byteFromRec(Rec, "SegOvrBits");
218 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
219 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
220 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
221 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
222 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
223 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
224 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
225 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
227 Name = Rec->getName();
228 AsmString = Rec->getValueAsString("AsmString");
230 Operands = &insn.Operands.OperandList;
232 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
233 (Name.find("CRC32") != Name.npos);
234 HasFROperands = hasFROperands();
235 HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
237 // Check for 64-bit inst which does not require REX
240 // FIXME: Is there some better way to check for In64BitMode?
241 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
242 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
243 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
247 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
252 // FIXME: These instructions aren't marked as 64-bit in any way
253 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
254 Rec->getName() == "MASKMOVDQU64" ||
255 Rec->getName() == "POPFS64" ||
256 Rec->getName() == "POPGS64" ||
257 Rec->getName() == "PUSHFS64" ||
258 Rec->getName() == "PUSHGS64" ||
259 Rec->getName() == "REX64_PREFIX" ||
260 Rec->getName().find("MOV64") != Name.npos ||
261 Rec->getName().find("PUSH64") != Name.npos ||
262 Rec->getName().find("POP64") != Name.npos;
264 // FIXME: BEXTR uses VEX.vvvv to encode its third operand
265 IsBEXTR = Rec->getName().find("BEXTR") != Name.npos;
267 ShouldBeEmitted = true;
270 void RecognizableInstr::processInstr(DisassemblerTables &tables,
271 const CodeGenInstruction &insn,
274 // Ignore "asm parser only" instructions.
275 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
278 RecognizableInstr recogInstr(tables, insn, uid);
280 recogInstr.emitInstructionSpecifier(tables);
282 if (recogInstr.shouldBeEmitted())
283 recogInstr.emitDecodePath(tables);
286 InstructionContext RecognizableInstr::insnContext() const {
287 InstructionContext insnContext;
289 if (HasVEX_4VPrefix || HasVEXPrefix) {
290 if (HasVEX_LPrefix && HasVEX_WPrefix)
291 llvm_unreachable("Don't support VEX.L and VEX.W together");
292 else if (HasOpSizePrefix && HasVEX_LPrefix)
293 insnContext = IC_VEX_L_OPSIZE;
294 else if (HasOpSizePrefix && HasVEX_WPrefix)
295 insnContext = IC_VEX_W_OPSIZE;
296 else if (HasOpSizePrefix)
297 insnContext = IC_VEX_OPSIZE;
298 else if (HasVEX_LPrefix && Prefix == X86Local::XS)
299 insnContext = IC_VEX_L_XS;
300 else if (HasVEX_LPrefix && Prefix == X86Local::XD)
301 insnContext = IC_VEX_L_XD;
302 else if (HasVEX_WPrefix && Prefix == X86Local::XS)
303 insnContext = IC_VEX_W_XS;
304 else if (HasVEX_WPrefix && Prefix == X86Local::XD)
305 insnContext = IC_VEX_W_XD;
306 else if (HasVEX_WPrefix)
307 insnContext = IC_VEX_W;
308 else if (HasVEX_LPrefix)
309 insnContext = IC_VEX_L;
310 else if (Prefix == X86Local::XD)
311 insnContext = IC_VEX_XD;
312 else if (Prefix == X86Local::XS)
313 insnContext = IC_VEX_XS;
315 insnContext = IC_VEX;
316 } else if (Is64Bit || HasREX_WPrefix) {
317 if (HasREX_WPrefix && HasOpSizePrefix)
318 insnContext = IC_64BIT_REXW_OPSIZE;
319 else if (HasOpSizePrefix &&
320 (Prefix == X86Local::XD || Prefix == X86Local::TF))
321 insnContext = IC_64BIT_XD_OPSIZE;
322 else if (HasOpSizePrefix && Prefix == X86Local::XS)
323 insnContext = IC_64BIT_XS_OPSIZE;
324 else if (HasOpSizePrefix)
325 insnContext = IC_64BIT_OPSIZE;
326 else if (HasREX_WPrefix && Prefix == X86Local::XS)
327 insnContext = IC_64BIT_REXW_XS;
328 else if (HasREX_WPrefix &&
329 (Prefix == X86Local::XD || Prefix == X86Local::TF))
330 insnContext = IC_64BIT_REXW_XD;
331 else if (Prefix == X86Local::XD || Prefix == X86Local::TF)
332 insnContext = IC_64BIT_XD;
333 else if (Prefix == X86Local::XS)
334 insnContext = IC_64BIT_XS;
335 else if (HasREX_WPrefix)
336 insnContext = IC_64BIT_REXW;
338 insnContext = IC_64BIT;
340 if (HasOpSizePrefix &&
341 (Prefix == X86Local::XD || Prefix == X86Local::TF))
342 insnContext = IC_XD_OPSIZE;
343 else if (HasOpSizePrefix && Prefix == X86Local::XS)
344 insnContext = IC_XS_OPSIZE;
345 else if (HasOpSizePrefix)
346 insnContext = IC_OPSIZE;
347 else if (Prefix == X86Local::XD || Prefix == X86Local::TF)
349 else if (Prefix == X86Local::XS || Prefix == X86Local::REP)
358 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
363 // Filter out intrinsics
365 if (!Rec->isSubClassOf("X86Inst"))
366 return FILTER_STRONG;
368 if (Form == X86Local::Pseudo ||
369 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
370 return FILTER_STRONG;
372 if (Form == X86Local::MRMInitReg)
373 return FILTER_STRONG;
376 // Filter out artificial instructions
378 if (Name.find("TAILJMP") != Name.npos ||
379 Name.find("_Int") != Name.npos ||
380 Name.find("_int") != Name.npos ||
381 Name.find("Int_") != Name.npos ||
382 Name.find("_NOREX") != Name.npos ||
383 Name.find("_TC") != Name.npos ||
384 Name.find("EH_RETURN") != Name.npos ||
385 Name.find("V_SET") != Name.npos ||
386 Name.find("LOCK_") != Name.npos ||
387 Name.find("WIN") != Name.npos ||
388 Name.find("_AVX") != Name.npos ||
389 Name.find("2SDL") != Name.npos)
390 return FILTER_STRONG;
392 // Filter out instructions with segment override prefixes.
393 // They're too messy to handle now and we'll special case them if needed.
396 return FILTER_STRONG;
398 // Filter out instructions that can't be printed.
400 if (AsmString.size() == 0)
401 return FILTER_STRONG;
403 // Filter out instructions with subreg operands.
405 if (AsmString.find("subreg") != AsmString.npos)
406 return FILTER_STRONG;
413 // Filter out instructions with a LOCK prefix;
414 // prefer forms that do not have the prefix
418 // Filter out alternate forms of AVX instructions
419 if (Name.find("_alt") != Name.npos ||
420 Name.find("XrYr") != Name.npos ||
421 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
422 Name.find("_64mr") != Name.npos ||
423 Name.find("Xrr") != Name.npos ||
424 Name.find("rr64") != Name.npos)
427 if (Name == "VMASKMOVDQU64" ||
428 Name == "VEXTRACTPSrr64" ||
429 Name == "VMOVQd64rr" ||
430 Name == "VMOVQs64rr")
435 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
437 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
440 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
442 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
444 if (Name.find("Fs") != Name.npos)
446 if (Name == "MOVLPDrr" ||
447 Name == "MOVLPSrr" ||
453 Name == "MOVSX16rm8" ||
454 Name == "MOVSX16rr8" ||
455 Name == "MOVZX16rm8" ||
456 Name == "MOVZX16rr8" ||
457 Name == "PUSH32i16" ||
458 Name == "PUSH64i16" ||
459 Name == "MOVPQI2QImr" ||
460 Name == "VMOVPQI2QImr" ||
465 Name == "MMX_MOVD64rrv164" ||
466 Name == "CRC32m16" ||
467 Name == "MOV64ri64i32" ||
471 if (HasFROperands && Name.find("MOV") != Name.npos &&
472 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
473 (Name.find("to") != Name.npos)))
476 return FILTER_NORMAL;
479 bool RecognizableInstr::hasFROperands() const {
480 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
481 unsigned numOperands = OperandList.size();
483 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
484 const std::string &recName = OperandList[operandIndex].Rec->getName();
486 if (recName.find("FR") != recName.npos)
492 bool RecognizableInstr::has256BitOperands() const {
493 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
494 unsigned numOperands = OperandList.size();
496 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
497 const std::string &recName = OperandList[operandIndex].Rec->getName();
499 if (!recName.compare("VR256") || !recName.compare("f256mem")) {
506 void RecognizableInstr::handleOperand(
508 unsigned &operandIndex,
509 unsigned &physicalOperandIndex,
510 unsigned &numPhysicalOperands,
511 unsigned *operandMapping,
512 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
514 if (physicalOperandIndex >= numPhysicalOperands)
517 assert(physicalOperandIndex < numPhysicalOperands);
520 while (operandMapping[operandIndex] != operandIndex) {
521 Spec->operands[operandIndex].encoding = ENCODING_DUP;
522 Spec->operands[operandIndex].type =
523 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
527 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
529 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
531 Spec->operands[operandIndex].type = typeFromString(typeName,
537 ++physicalOperandIndex;
540 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
543 if (!Rec->isSubClassOf("X86Inst"))
548 Spec->filtered = true;
551 ShouldBeEmitted = false;
557 Spec->insnContext = insnContext();
559 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
561 unsigned operandIndex;
562 unsigned numOperands = OperandList.size();
563 unsigned numPhysicalOperands = 0;
565 // operandMapping maps from operands in OperandList to their originals.
566 // If operandMapping[i] != i, then the entry is a duplicate.
567 unsigned operandMapping[X86_MAX_OPERANDS];
569 bool hasFROperands = false;
571 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
573 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
574 if (OperandList[operandIndex].Constraints.size()) {
575 const CGIOperandList::ConstraintInfo &Constraint =
576 OperandList[operandIndex].Constraints[0];
577 if (Constraint.isTied()) {
578 operandMapping[operandIndex] = Constraint.getTiedOperand();
580 ++numPhysicalOperands;
581 operandMapping[operandIndex] = operandIndex;
584 ++numPhysicalOperands;
585 operandMapping[operandIndex] = operandIndex;
588 const std::string &recName = OperandList[operandIndex].Rec->getName();
590 if (recName.find("FR") != recName.npos)
591 hasFROperands = true;
594 if (hasFROperands && Name.find("MOV") != Name.npos &&
595 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
596 (Name.find("to") != Name.npos)))
597 ShouldBeEmitted = false;
599 if (!ShouldBeEmitted)
602 #define HANDLE_OPERAND(class) \
603 handleOperand(false, \
605 physicalOperandIndex, \
606 numPhysicalOperands, \
608 class##EncodingFromString);
610 #define HANDLE_OPTIONAL(class) \
611 handleOperand(true, \
613 physicalOperandIndex, \
614 numPhysicalOperands, \
616 class##EncodingFromString);
618 // operandIndex should always be < numOperands
620 // physicalOperandIndex should always be < numPhysicalOperands
621 unsigned physicalOperandIndex = 0;
624 case X86Local::RawFrm:
625 // Operand 1 (optional) is an address or immediate.
626 // Operand 2 (optional) is an immediate.
627 assert(numPhysicalOperands <= 2 &&
628 "Unexpected number of operands for RawFrm");
629 HANDLE_OPTIONAL(relocation)
630 HANDLE_OPTIONAL(immediate)
632 case X86Local::AddRegFrm:
633 // Operand 1 is added to the opcode.
634 // Operand 2 (optional) is an address.
635 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
636 "Unexpected number of operands for AddRegFrm");
637 HANDLE_OPERAND(opcodeModifier)
638 HANDLE_OPTIONAL(relocation)
640 case X86Local::MRMDestReg:
641 // Operand 1 is a register operand in the R/M field.
642 // Operand 2 is a register operand in the Reg/Opcode field.
643 // - In AVX, there is a register operand in the VEX.vvvv field here -
644 // Operand 3 (optional) is an immediate.
646 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
647 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
649 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
650 "Unexpected number of operands for MRMDestRegFrm");
652 HANDLE_OPERAND(rmRegister)
655 // FIXME: In AVX, the register below becomes the one encoded
656 // in ModRMVEX and the one above the one in the VEX.VVVV field
657 HANDLE_OPERAND(vvvvRegister)
659 HANDLE_OPERAND(roRegister)
660 HANDLE_OPTIONAL(immediate)
662 case X86Local::MRMDestMem:
663 // Operand 1 is a memory operand (possibly SIB-extended)
664 // Operand 2 is a register operand in the Reg/Opcode field.
665 // - In AVX, there is a register operand in the VEX.vvvv field here -
666 // Operand 3 (optional) is an immediate.
668 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
669 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
671 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
672 "Unexpected number of operands for MRMDestMemFrm");
673 HANDLE_OPERAND(memory)
676 // FIXME: In AVX, the register below becomes the one encoded
677 // in ModRMVEX and the one above the one in the VEX.VVVV field
678 HANDLE_OPERAND(vvvvRegister)
680 HANDLE_OPERAND(roRegister)
681 HANDLE_OPTIONAL(immediate)
683 case X86Local::MRMSrcReg:
684 // Operand 1 is a register operand in the Reg/Opcode field.
685 // Operand 2 is a register operand in the R/M field.
686 // - In AVX, there is a register operand in the VEX.vvvv field here -
687 // Operand 3 (optional) is an immediate.
690 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
691 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
693 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
694 "Unexpected number of operands for MRMSrcRegFrm");
696 HANDLE_OPERAND(roRegister)
698 if (HasVEX_4VPrefix && !IsBEXTR)
699 // FIXME: In AVX, the register below becomes the one encoded
700 // in ModRMVEX and the one above the one in the VEX.VVVV field
701 HANDLE_OPERAND(vvvvRegister)
703 HANDLE_OPERAND(rmRegister)
705 // FIXME: BEXTR uses VEX.vvvv for Operand 3
707 HANDLE_OPERAND(vvvvRegister)
709 HANDLE_OPTIONAL(immediate)
711 case X86Local::MRMSrcMem:
712 // Operand 1 is a register operand in the Reg/Opcode field.
713 // Operand 2 is a memory operand (possibly SIB-extended)
714 // - In AVX, there is a register operand in the VEX.vvvv field here -
715 // Operand 3 (optional) is an immediate.
718 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
719 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
721 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
722 "Unexpected number of operands for MRMSrcMemFrm");
724 HANDLE_OPERAND(roRegister)
726 if (HasVEX_4VPrefix && !IsBEXTR)
727 // FIXME: In AVX, the register below becomes the one encoded
728 // in ModRMVEX and the one above the one in the VEX.VVVV field
729 HANDLE_OPERAND(vvvvRegister)
731 HANDLE_OPERAND(memory)
733 // FIXME: BEXTR uses VEX.vvvv for Operand 3
735 HANDLE_OPERAND(vvvvRegister)
737 HANDLE_OPTIONAL(immediate)
739 case X86Local::MRM0r:
740 case X86Local::MRM1r:
741 case X86Local::MRM2r:
742 case X86Local::MRM3r:
743 case X86Local::MRM4r:
744 case X86Local::MRM5r:
745 case X86Local::MRM6r:
746 case X86Local::MRM7r:
747 // Operand 1 is a register operand in the R/M field.
748 // Operand 2 (optional) is an immediate or relocation.
750 assert(numPhysicalOperands <= 3 &&
751 "Unexpected number of operands for MRMnRFrm with VEX_4V");
753 assert(numPhysicalOperands <= 2 &&
754 "Unexpected number of operands for MRMnRFrm");
756 HANDLE_OPERAND(vvvvRegister)
757 HANDLE_OPTIONAL(rmRegister)
758 HANDLE_OPTIONAL(relocation)
760 case X86Local::MRM0m:
761 case X86Local::MRM1m:
762 case X86Local::MRM2m:
763 case X86Local::MRM3m:
764 case X86Local::MRM4m:
765 case X86Local::MRM5m:
766 case X86Local::MRM6m:
767 case X86Local::MRM7m:
768 // Operand 1 is a memory operand (possibly SIB-extended)
769 // Operand 2 (optional) is an immediate or relocation.
771 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
772 "Unexpected number of operands for MRMnMFrm");
774 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
775 "Unexpected number of operands for MRMnMFrm");
777 HANDLE_OPERAND(vvvvRegister)
778 HANDLE_OPERAND(memory)
779 HANDLE_OPTIONAL(relocation)
781 case X86Local::RawFrmImm8:
782 // operand 1 is a 16-bit immediate
783 // operand 2 is an 8-bit immediate
784 assert(numPhysicalOperands == 2 &&
785 "Unexpected number of operands for X86Local::RawFrmImm8");
786 HANDLE_OPERAND(immediate)
787 HANDLE_OPERAND(immediate)
789 case X86Local::RawFrmImm16:
790 // operand 1 is a 16-bit immediate
791 // operand 2 is a 16-bit immediate
792 HANDLE_OPERAND(immediate)
793 HANDLE_OPERAND(immediate)
795 case X86Local::MRMInitReg:
800 #undef HANDLE_OPERAND
801 #undef HANDLE_OPTIONAL
804 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
805 // Special cases where the LLVM tables are not complete
807 #define MAP(from, to) \
808 case X86Local::MRM_##from: \
809 filter = new ExactFilter(0x##from); \
812 OpcodeType opcodeType = (OpcodeType)-1;
814 ModRMFilter* filter = NULL;
815 uint8_t opcodeToSet = 0;
818 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
822 opcodeType = TWOBYTE;
826 if (needsModRMForDecode(Form))
827 filter = new ModFilter(isRegFormat(Form));
829 filter = new DumbFilter();
831 #define EXTENSION_TABLE(n) case 0x##n:
832 TWO_BYTE_EXTENSION_TABLES
833 #undef EXTENSION_TABLE
836 llvm_unreachable("Unhandled two-byte extended opcode");
837 case X86Local::MRM0r:
838 case X86Local::MRM1r:
839 case X86Local::MRM2r:
840 case X86Local::MRM3r:
841 case X86Local::MRM4r:
842 case X86Local::MRM5r:
843 case X86Local::MRM6r:
844 case X86Local::MRM7r:
845 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
847 case X86Local::MRM0m:
848 case X86Local::MRM1m:
849 case X86Local::MRM2m:
850 case X86Local::MRM3m:
851 case X86Local::MRM4m:
852 case X86Local::MRM5m:
853 case X86Local::MRM6m:
854 case X86Local::MRM7m:
855 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
861 opcodeToSet = Opcode;
865 opcodeType = THREEBYTE_38;
868 if (needsModRMForDecode(Form))
869 filter = new ModFilter(isRegFormat(Form));
871 filter = new DumbFilter();
873 #define EXTENSION_TABLE(n) case 0x##n:
874 THREE_BYTE_38_EXTENSION_TABLES
875 #undef EXTENSION_TABLE
878 llvm_unreachable("Unhandled two-byte extended opcode");
879 case X86Local::MRM0r:
880 case X86Local::MRM1r:
881 case X86Local::MRM2r:
882 case X86Local::MRM3r:
883 case X86Local::MRM4r:
884 case X86Local::MRM5r:
885 case X86Local::MRM6r:
886 case X86Local::MRM7r:
887 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
889 case X86Local::MRM0m:
890 case X86Local::MRM1m:
891 case X86Local::MRM2m:
892 case X86Local::MRM3m:
893 case X86Local::MRM4m:
894 case X86Local::MRM5m:
895 case X86Local::MRM6m:
896 case X86Local::MRM7m:
897 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
903 opcodeToSet = Opcode;
906 opcodeType = THREEBYTE_3A;
907 if (needsModRMForDecode(Form))
908 filter = new ModFilter(isRegFormat(Form));
910 filter = new DumbFilter();
911 opcodeToSet = Opcode;
914 opcodeType = THREEBYTE_A6;
915 if (needsModRMForDecode(Form))
916 filter = new ModFilter(isRegFormat(Form));
918 filter = new DumbFilter();
919 opcodeToSet = Opcode;
922 opcodeType = THREEBYTE_A7;
923 if (needsModRMForDecode(Form))
924 filter = new ModFilter(isRegFormat(Form));
926 filter = new DumbFilter();
927 opcodeToSet = Opcode;
937 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
938 opcodeType = ONEBYTE;
939 if (Form == X86Local::AddRegFrm) {
940 Spec->modifierType = MODIFIER_MODRM;
941 Spec->modifierBase = Opcode;
942 filter = new AddRegEscapeFilter(Opcode);
944 filter = new EscapeFilter(true, Opcode);
946 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
950 opcodeType = ONEBYTE;
952 #define EXTENSION_TABLE(n) case 0x##n:
953 ONE_BYTE_EXTENSION_TABLES
954 #undef EXTENSION_TABLE
957 llvm_unreachable("Fell through the cracks of a single-byte "
959 case X86Local::MRM0r:
960 case X86Local::MRM1r:
961 case X86Local::MRM2r:
962 case X86Local::MRM3r:
963 case X86Local::MRM4r:
964 case X86Local::MRM5r:
965 case X86Local::MRM6r:
966 case X86Local::MRM7r:
967 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
969 case X86Local::MRM0m:
970 case X86Local::MRM1m:
971 case X86Local::MRM2m:
972 case X86Local::MRM3m:
973 case X86Local::MRM4m:
974 case X86Local::MRM5m:
975 case X86Local::MRM6m:
976 case X86Local::MRM7m:
977 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
990 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
993 if (needsModRMForDecode(Form))
994 filter = new ModFilter(isRegFormat(Form));
996 filter = new DumbFilter();
999 opcodeToSet = Opcode;
1000 } // switch (Prefix)
1002 assert(opcodeType != (OpcodeType)-1 &&
1003 "Opcode type not set");
1004 assert(filter && "Filter not set");
1006 if (Form == X86Local::AddRegFrm) {
1007 if(Spec->modifierType != MODIFIER_MODRM) {
1008 assert(opcodeToSet < 0xf9 &&
1009 "Not enough room for all ADDREG_FRM operands");
1011 uint8_t currentOpcode;
1013 for (currentOpcode = opcodeToSet;
1014 currentOpcode < opcodeToSet + 8;
1016 tables.setTableFields(opcodeType,
1020 UID, Is32Bit, IgnoresVEX_L);
1022 Spec->modifierType = MODIFIER_OPCODE;
1023 Spec->modifierBase = opcodeToSet;
1025 // modifierBase was set where MODIFIER_MODRM was set
1026 tables.setTableFields(opcodeType,
1030 UID, Is32Bit, IgnoresVEX_L);
1033 tables.setTableFields(opcodeType,
1037 UID, Is32Bit, IgnoresVEX_L);
1039 Spec->modifierType = MODIFIER_NONE;
1040 Spec->modifierBase = opcodeToSet;
1048 #define TYPE(str, type) if (s == str) return type;
1049 OperandType RecognizableInstr::typeFromString(const std::string &s,
1051 bool hasREX_WPrefix,
1052 bool hasOpSizePrefix) {
1054 // For SSE instructions, we ignore the OpSize prefix and force operand
1056 TYPE("GR16", TYPE_R16)
1057 TYPE("GR32", TYPE_R32)
1058 TYPE("GR64", TYPE_R64)
1060 if(hasREX_WPrefix) {
1061 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1063 TYPE("GR32", TYPE_R32)
1065 if(!hasOpSizePrefix) {
1066 // For instructions without an OpSize prefix, a declared 16-bit register or
1067 // immediate encoding is special.
1068 TYPE("GR16", TYPE_R16)
1069 TYPE("i16imm", TYPE_IMM16)
1071 TYPE("i16mem", TYPE_Mv)
1072 TYPE("i16imm", TYPE_IMMv)
1073 TYPE("i16i8imm", TYPE_IMMv)
1074 TYPE("GR16", TYPE_Rv)
1075 TYPE("i32mem", TYPE_Mv)
1076 TYPE("i32imm", TYPE_IMMv)
1077 TYPE("i32i8imm", TYPE_IMM32)
1078 TYPE("u32u8imm", TYPE_IMM32)
1079 TYPE("GR32", TYPE_Rv)
1080 TYPE("i64mem", TYPE_Mv)
1081 TYPE("i64i32imm", TYPE_IMM64)
1082 TYPE("i64i8imm", TYPE_IMM64)
1083 TYPE("GR64", TYPE_R64)
1084 TYPE("i8mem", TYPE_M8)
1085 TYPE("i8imm", TYPE_IMM8)
1086 TYPE("GR8", TYPE_R8)
1087 TYPE("VR128", TYPE_XMM128)
1088 TYPE("f128mem", TYPE_M128)
1089 TYPE("f256mem", TYPE_M256)
1090 TYPE("FR64", TYPE_XMM64)
1091 TYPE("f64mem", TYPE_M64FP)
1092 TYPE("sdmem", TYPE_M64FP)
1093 TYPE("FR32", TYPE_XMM32)
1094 TYPE("f32mem", TYPE_M32FP)
1095 TYPE("ssmem", TYPE_M32FP)
1096 TYPE("RST", TYPE_ST)
1097 TYPE("i128mem", TYPE_M128)
1098 TYPE("i256mem", TYPE_M256)
1099 TYPE("i64i32imm_pcrel", TYPE_REL64)
1100 TYPE("i16imm_pcrel", TYPE_REL16)
1101 TYPE("i32imm_pcrel", TYPE_REL32)
1102 TYPE("SSECC", TYPE_IMM3)
1103 TYPE("brtarget", TYPE_RELv)
1104 TYPE("uncondbrtarget", TYPE_RELv)
1105 TYPE("brtarget8", TYPE_REL8)
1106 TYPE("f80mem", TYPE_M80FP)
1107 TYPE("lea32mem", TYPE_LEA)
1108 TYPE("lea64_32mem", TYPE_LEA)
1109 TYPE("lea64mem", TYPE_LEA)
1110 TYPE("VR64", TYPE_MM64)
1111 TYPE("i64imm", TYPE_IMMv)
1112 TYPE("opaque32mem", TYPE_M1616)
1113 TYPE("opaque48mem", TYPE_M1632)
1114 TYPE("opaque80mem", TYPE_M1664)
1115 TYPE("opaque512mem", TYPE_M512)
1116 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1117 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1118 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1119 TYPE("offset8", TYPE_MOFFS8)
1120 TYPE("offset16", TYPE_MOFFS16)
1121 TYPE("offset32", TYPE_MOFFS32)
1122 TYPE("offset64", TYPE_MOFFS64)
1123 TYPE("VR256", TYPE_XMM256)
1124 TYPE("GR16_NOAX", TYPE_Rv)
1125 TYPE("GR32_NOAX", TYPE_Rv)
1126 TYPE("GR64_NOAX", TYPE_R64)
1127 errs() << "Unhandled type string " << s << "\n";
1128 llvm_unreachable("Unhandled type string");
1132 #define ENCODING(str, encoding) if (s == str) return encoding;
1133 OperandEncoding RecognizableInstr::immediateEncodingFromString
1134 (const std::string &s,
1135 bool hasOpSizePrefix) {
1136 if(!hasOpSizePrefix) {
1137 // For instructions without an OpSize prefix, a declared 16-bit register or
1138 // immediate encoding is special.
1139 ENCODING("i16imm", ENCODING_IW)
1141 ENCODING("i32i8imm", ENCODING_IB)
1142 ENCODING("u32u8imm", ENCODING_IB)
1143 ENCODING("SSECC", ENCODING_IB)
1144 ENCODING("i16imm", ENCODING_Iv)
1145 ENCODING("i16i8imm", ENCODING_IB)
1146 ENCODING("i32imm", ENCODING_Iv)
1147 ENCODING("i64i32imm", ENCODING_ID)
1148 ENCODING("i64i8imm", ENCODING_IB)
1149 ENCODING("i8imm", ENCODING_IB)
1150 // This is not a typo. Instructions like BLENDVPD put
1151 // register IDs in 8-bit immediates nowadays.
1152 ENCODING("VR256", ENCODING_IB)
1153 ENCODING("VR128", ENCODING_IB)
1154 errs() << "Unhandled immediate encoding " << s << "\n";
1155 llvm_unreachable("Unhandled immediate encoding");
1158 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1159 (const std::string &s,
1160 bool hasOpSizePrefix) {
1161 ENCODING("GR16", ENCODING_RM)
1162 ENCODING("GR32", ENCODING_RM)
1163 ENCODING("GR64", ENCODING_RM)
1164 ENCODING("GR8", ENCODING_RM)
1165 ENCODING("VR128", ENCODING_RM)
1166 ENCODING("FR64", ENCODING_RM)
1167 ENCODING("FR32", ENCODING_RM)
1168 ENCODING("VR64", ENCODING_RM)
1169 ENCODING("VR256", ENCODING_RM)
1170 errs() << "Unhandled R/M register encoding " << s << "\n";
1171 llvm_unreachable("Unhandled R/M register encoding");
1174 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1175 (const std::string &s,
1176 bool hasOpSizePrefix) {
1177 ENCODING("GR16", ENCODING_REG)
1178 ENCODING("GR32", ENCODING_REG)
1179 ENCODING("GR64", ENCODING_REG)
1180 ENCODING("GR8", ENCODING_REG)
1181 ENCODING("VR128", ENCODING_REG)
1182 ENCODING("FR64", ENCODING_REG)
1183 ENCODING("FR32", ENCODING_REG)
1184 ENCODING("VR64", ENCODING_REG)
1185 ENCODING("SEGMENT_REG", ENCODING_REG)
1186 ENCODING("DEBUG_REG", ENCODING_REG)
1187 ENCODING("CONTROL_REG", ENCODING_REG)
1188 ENCODING("VR256", ENCODING_REG)
1189 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1190 llvm_unreachable("Unhandled reg/opcode register encoding");
1193 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1194 (const std::string &s,
1195 bool hasOpSizePrefix) {
1196 ENCODING("GR32", ENCODING_VVVV)
1197 ENCODING("GR64", ENCODING_VVVV)
1198 ENCODING("FR32", ENCODING_VVVV)
1199 ENCODING("FR64", ENCODING_VVVV)
1200 ENCODING("VR128", ENCODING_VVVV)
1201 ENCODING("VR256", ENCODING_VVVV)
1202 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1203 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1206 OperandEncoding RecognizableInstr::memoryEncodingFromString
1207 (const std::string &s,
1208 bool hasOpSizePrefix) {
1209 ENCODING("i16mem", ENCODING_RM)
1210 ENCODING("i32mem", ENCODING_RM)
1211 ENCODING("i64mem", ENCODING_RM)
1212 ENCODING("i8mem", ENCODING_RM)
1213 ENCODING("ssmem", ENCODING_RM)
1214 ENCODING("sdmem", ENCODING_RM)
1215 ENCODING("f128mem", ENCODING_RM)
1216 ENCODING("f256mem", ENCODING_RM)
1217 ENCODING("f64mem", ENCODING_RM)
1218 ENCODING("f32mem", ENCODING_RM)
1219 ENCODING("i128mem", ENCODING_RM)
1220 ENCODING("i256mem", ENCODING_RM)
1221 ENCODING("f80mem", ENCODING_RM)
1222 ENCODING("lea32mem", ENCODING_RM)
1223 ENCODING("lea64_32mem", ENCODING_RM)
1224 ENCODING("lea64mem", ENCODING_RM)
1225 ENCODING("opaque32mem", ENCODING_RM)
1226 ENCODING("opaque48mem", ENCODING_RM)
1227 ENCODING("opaque80mem", ENCODING_RM)
1228 ENCODING("opaque512mem", ENCODING_RM)
1229 errs() << "Unhandled memory encoding " << s << "\n";
1230 llvm_unreachable("Unhandled memory encoding");
1233 OperandEncoding RecognizableInstr::relocationEncodingFromString
1234 (const std::string &s,
1235 bool hasOpSizePrefix) {
1236 if(!hasOpSizePrefix) {
1237 // For instructions without an OpSize prefix, a declared 16-bit register or
1238 // immediate encoding is special.
1239 ENCODING("i16imm", ENCODING_IW)
1241 ENCODING("i16imm", ENCODING_Iv)
1242 ENCODING("i16i8imm", ENCODING_IB)
1243 ENCODING("i32imm", ENCODING_Iv)
1244 ENCODING("i32i8imm", ENCODING_IB)
1245 ENCODING("i64i32imm", ENCODING_ID)
1246 ENCODING("i64i8imm", ENCODING_IB)
1247 ENCODING("i8imm", ENCODING_IB)
1248 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1249 ENCODING("i16imm_pcrel", ENCODING_IW)
1250 ENCODING("i32imm_pcrel", ENCODING_ID)
1251 ENCODING("brtarget", ENCODING_Iv)
1252 ENCODING("brtarget8", ENCODING_IB)
1253 ENCODING("i64imm", ENCODING_IO)
1254 ENCODING("offset8", ENCODING_Ia)
1255 ENCODING("offset16", ENCODING_Ia)
1256 ENCODING("offset32", ENCODING_Ia)
1257 ENCODING("offset64", ENCODING_Ia)
1258 errs() << "Unhandled relocation encoding " << s << "\n";
1259 llvm_unreachable("Unhandled relocation encoding");
1262 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1263 (const std::string &s,
1264 bool hasOpSizePrefix) {
1265 ENCODING("RST", ENCODING_I)
1266 ENCODING("GR32", ENCODING_Rv)
1267 ENCODING("GR64", ENCODING_RO)
1268 ENCODING("GR16", ENCODING_Rv)
1269 ENCODING("GR8", ENCODING_RB)
1270 ENCODING("GR16_NOAX", ENCODING_Rv)
1271 ENCODING("GR32_NOAX", ENCODING_Rv)
1272 ENCODING("GR64_NOAX", ENCODING_RO)
1273 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1274 llvm_unreachable("Unhandled opcode modifier encoding");