1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
86 // If rows are added to the opcode extension tables, then corresponding entries
87 // must be added here.
89 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
90 // that byte to ONE_BYTE_EXTENSION_TABLES.
92 // If the row corresponds to two bytes where the first is 0f, add an entry for
93 // the second byte to TWO_BYTE_EXTENSION_TABLES.
95 // If the row corresponds to some other set of bytes, you will need to modify
96 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
97 // to the X86 TD files, except in two cases: if the first two bytes of such a
98 // new combination are 0f 38 or 0f 3a, you just have to add maps called
99 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
100 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
101 // in RecognizableInstr::emitDecodePath().
103 #define ONE_BYTE_EXTENSION_TABLES \
104 EXTENSION_TABLE(80) \
105 EXTENSION_TABLE(81) \
106 EXTENSION_TABLE(82) \
107 EXTENSION_TABLE(83) \
108 EXTENSION_TABLE(8f) \
109 EXTENSION_TABLE(c0) \
110 EXTENSION_TABLE(c1) \
111 EXTENSION_TABLE(c6) \
112 EXTENSION_TABLE(c7) \
113 EXTENSION_TABLE(d0) \
114 EXTENSION_TABLE(d1) \
115 EXTENSION_TABLE(d2) \
116 EXTENSION_TABLE(d3) \
117 EXTENSION_TABLE(f6) \
118 EXTENSION_TABLE(f7) \
119 EXTENSION_TABLE(fe) \
122 #define TWO_BYTE_EXTENSION_TABLES \
123 EXTENSION_TABLE(00) \
124 EXTENSION_TABLE(01) \
125 EXTENSION_TABLE(0d) \
126 EXTENSION_TABLE(18) \
127 EXTENSION_TABLE(71) \
128 EXTENSION_TABLE(72) \
129 EXTENSION_TABLE(73) \
130 EXTENSION_TABLE(ae) \
131 EXTENSION_TABLE(ba) \
134 #define THREE_BYTE_38_EXTENSION_TABLES \
137 using namespace X86Disassembler;
139 /// needsModRMForDecode - Indicates whether a particular instruction requires a
140 /// ModR/M byte for the instruction to be properly decoded. For example, a
141 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
144 /// @param form - The form of the instruction.
145 /// @return - true if the form implies that a ModR/M byte is required, false
147 static bool needsModRMForDecode(uint8_t form) {
148 if (form == X86Local::MRMDestReg ||
149 form == X86Local::MRMDestMem ||
150 form == X86Local::MRMSrcReg ||
151 form == X86Local::MRMSrcMem ||
152 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
153 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
159 /// isRegFormat - Indicates whether a particular form requires the Mod field of
160 /// the ModR/M byte to be 0b11.
162 /// @param form - The form of the instruction.
163 /// @return - true if the form implies that Mod must be 0b11, false
165 static bool isRegFormat(uint8_t form) {
166 if (form == X86Local::MRMDestReg ||
167 form == X86Local::MRMSrcReg ||
168 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
174 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
175 /// Useful for switch statements and the like.
177 /// @param init - A reference to the BitsInit to be decoded.
178 /// @return - The field, with the first bit in the BitsInit as the lowest
180 static uint8_t byteFromBitsInit(BitsInit &init) {
181 int width = init.getNumBits();
183 assert(width <= 8 && "Field is too large for uint8_t!");
190 for (index = 0; index < width; index++) {
191 if (static_cast<BitInit*>(init.getBit(index))->getValue())
200 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
201 /// name of the field.
203 /// @param rec - The record from which to extract the value.
204 /// @param name - The name of the field in the record.
205 /// @return - The field, as translated by byteFromBitsInit().
206 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
207 BitsInit* bits = rec->getValueAsBitsInit(name);
208 return byteFromBitsInit(*bits);
211 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
212 const CodeGenInstruction &insn,
217 Name = Rec->getName();
218 Spec = &tables.specForUID(UID);
220 if (!Rec->isSubClassOf("X86Inst")) {
221 ShouldBeEmitted = false;
225 Prefix = byteFromRec(Rec, "Prefix");
226 Opcode = byteFromRec(Rec, "Opcode");
227 Form = byteFromRec(Rec, "FormBits");
228 SegOvr = byteFromRec(Rec, "SegOvrBits");
230 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
231 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
232 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
233 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
234 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
235 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
236 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
237 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
238 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
239 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
240 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
242 Name = Rec->getName();
243 AsmString = Rec->getValueAsString("AsmString");
245 Operands = &insn.Operands.OperandList;
247 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
248 (Name.find("CRC32") != Name.npos);
249 HasFROperands = hasFROperands();
250 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
252 // Check for 64-bit inst which does not require REX
255 // FIXME: Is there some better way to check for In64BitMode?
256 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
257 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
258 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
262 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
267 // FIXME: These instructions aren't marked as 64-bit in any way
268 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
269 Rec->getName() == "MASKMOVDQU64" ||
270 Rec->getName() == "POPFS64" ||
271 Rec->getName() == "POPGS64" ||
272 Rec->getName() == "PUSHFS64" ||
273 Rec->getName() == "PUSHGS64" ||
274 Rec->getName() == "REX64_PREFIX" ||
275 Rec->getName().find("MOV64") != Name.npos ||
276 Rec->getName().find("PUSH64") != Name.npos ||
277 Rec->getName().find("POP64") != Name.npos;
279 ShouldBeEmitted = true;
282 void RecognizableInstr::processInstr(DisassemblerTables &tables,
283 const CodeGenInstruction &insn,
286 // Ignore "asm parser only" instructions.
287 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
290 RecognizableInstr recogInstr(tables, insn, uid);
292 recogInstr.emitInstructionSpecifier(tables);
294 if (recogInstr.shouldBeEmitted())
295 recogInstr.emitDecodePath(tables);
298 InstructionContext RecognizableInstr::insnContext() const {
299 InstructionContext insnContext;
301 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
302 if (HasVEX_LPrefix && HasVEX_WPrefix) {
304 insnContext = IC_VEX_L_W_OPSIZE;
306 llvm_unreachable("Don't support VEX.L and VEX.W together");
307 } else if (HasOpSizePrefix && HasVEX_LPrefix)
308 insnContext = IC_VEX_L_OPSIZE;
309 else if (HasOpSizePrefix && HasVEX_WPrefix)
310 insnContext = IC_VEX_W_OPSIZE;
311 else if (HasOpSizePrefix)
312 insnContext = IC_VEX_OPSIZE;
313 else if (HasVEX_LPrefix &&
314 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
315 insnContext = IC_VEX_L_XS;
316 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
317 Prefix == X86Local::T8XD ||
318 Prefix == X86Local::TAXD))
319 insnContext = IC_VEX_L_XD;
320 else if (HasVEX_WPrefix &&
321 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
322 insnContext = IC_VEX_W_XS;
323 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
324 Prefix == X86Local::T8XD ||
325 Prefix == X86Local::TAXD))
326 insnContext = IC_VEX_W_XD;
327 else if (HasVEX_WPrefix)
328 insnContext = IC_VEX_W;
329 else if (HasVEX_LPrefix)
330 insnContext = IC_VEX_L;
331 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
332 Prefix == X86Local::TAXD)
333 insnContext = IC_VEX_XD;
334 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
335 insnContext = IC_VEX_XS;
337 insnContext = IC_VEX;
338 } else if (Is64Bit || HasREX_WPrefix) {
339 if (HasREX_WPrefix && HasOpSizePrefix)
340 insnContext = IC_64BIT_REXW_OPSIZE;
341 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
342 Prefix == X86Local::T8XD ||
343 Prefix == X86Local::TAXD))
344 insnContext = IC_64BIT_XD_OPSIZE;
345 else if (HasOpSizePrefix &&
346 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
347 insnContext = IC_64BIT_XS_OPSIZE;
348 else if (HasOpSizePrefix)
349 insnContext = IC_64BIT_OPSIZE;
350 else if (HasAdSizePrefix)
351 insnContext = IC_64BIT_ADSIZE;
352 else if (HasREX_WPrefix &&
353 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
354 insnContext = IC_64BIT_REXW_XS;
355 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
356 Prefix == X86Local::T8XD ||
357 Prefix == X86Local::TAXD))
358 insnContext = IC_64BIT_REXW_XD;
359 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
360 Prefix == X86Local::TAXD)
361 insnContext = IC_64BIT_XD;
362 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
363 insnContext = IC_64BIT_XS;
364 else if (HasREX_WPrefix)
365 insnContext = IC_64BIT_REXW;
367 insnContext = IC_64BIT;
369 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
370 Prefix == X86Local::T8XD ||
371 Prefix == X86Local::TAXD))
372 insnContext = IC_XD_OPSIZE;
373 else if (HasOpSizePrefix &&
374 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
375 insnContext = IC_XS_OPSIZE;
376 else if (HasOpSizePrefix)
377 insnContext = IC_OPSIZE;
378 else if (HasAdSizePrefix)
379 insnContext = IC_ADSIZE;
380 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
381 Prefix == X86Local::TAXD)
383 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
384 Prefix == X86Local::REP)
393 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
398 // Filter out intrinsics
400 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
402 if (Form == X86Local::Pseudo ||
403 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
404 return FILTER_STRONG;
407 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
408 // printed as a separate "instruction".
410 if (Name.find("_Int") != Name.npos ||
411 Name.find("Int_") != Name.npos)
412 return FILTER_STRONG;
414 // Filter out instructions with segment override prefixes.
415 // They're too messy to handle now and we'll special case them if needed.
418 return FILTER_STRONG;
426 // Filter out instructions with a LOCK prefix;
427 // prefer forms that do not have the prefix
431 // Filter out alternate forms of AVX instructions
432 if (Name.find("_alt") != Name.npos ||
433 Name.find("XrYr") != Name.npos ||
434 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
435 Name.find("_64mr") != Name.npos ||
436 Name.find("Xrr") != Name.npos ||
437 Name.find("rr64") != Name.npos)
442 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
444 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
447 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
449 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
451 if (Name.find("Fs") != Name.npos)
453 if (Name == "PUSH64i16" ||
454 Name == "MOVPQI2QImr" ||
455 Name == "VMOVPQI2QImr" ||
456 Name == "MMX_MOVD64rrv164" ||
457 Name == "MOV64ri64i32" ||
458 Name == "VMASKMOVDQU64" ||
459 Name == "VEXTRACTPSrr64" ||
460 Name == "VMOVQd64rr" ||
461 Name == "VMOVQs64rr")
464 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
465 // For now, just prefer the REP versions.
466 if (Name == "XACQUIRE_PREFIX" ||
467 Name == "XRELEASE_PREFIX")
470 if (HasFROperands && Name.find("MOV") != Name.npos &&
471 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
472 (Name.find("to") != Name.npos)))
473 return FILTER_STRONG;
475 return FILTER_NORMAL;
478 bool RecognizableInstr::hasFROperands() const {
479 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
480 unsigned numOperands = OperandList.size();
482 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
483 const std::string &recName = OperandList[operandIndex].Rec->getName();
485 if (recName.find("FR") != recName.npos)
491 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
492 unsigned &physicalOperandIndex,
493 unsigned &numPhysicalOperands,
494 const unsigned *operandMapping,
495 OperandEncoding (*encodingFromString)
497 bool hasOpSizePrefix)) {
499 if (physicalOperandIndex >= numPhysicalOperands)
502 assert(physicalOperandIndex < numPhysicalOperands);
505 while (operandMapping[operandIndex] != operandIndex) {
506 Spec->operands[operandIndex].encoding = ENCODING_DUP;
507 Spec->operands[operandIndex].type =
508 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
512 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
514 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
516 Spec->operands[operandIndex].type = typeFromString(typeName,
522 ++physicalOperandIndex;
525 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
528 if (!ShouldBeEmitted)
533 Spec->filtered = true;
536 ShouldBeEmitted = false;
542 Spec->insnContext = insnContext();
544 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
546 unsigned numOperands = OperandList.size();
547 unsigned numPhysicalOperands = 0;
549 // operandMapping maps from operands in OperandList to their originals.
550 // If operandMapping[i] != i, then the entry is a duplicate.
551 unsigned operandMapping[X86_MAX_OPERANDS];
552 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
554 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
555 if (OperandList[operandIndex].Constraints.size()) {
556 const CGIOperandList::ConstraintInfo &Constraint =
557 OperandList[operandIndex].Constraints[0];
558 if (Constraint.isTied()) {
559 operandMapping[operandIndex] = operandIndex;
560 operandMapping[Constraint.getTiedOperand()] = operandIndex;
562 ++numPhysicalOperands;
563 operandMapping[operandIndex] = operandIndex;
566 ++numPhysicalOperands;
567 operandMapping[operandIndex] = operandIndex;
571 #define HANDLE_OPERAND(class) \
572 handleOperand(false, \
574 physicalOperandIndex, \
575 numPhysicalOperands, \
577 class##EncodingFromString);
579 #define HANDLE_OPTIONAL(class) \
580 handleOperand(true, \
582 physicalOperandIndex, \
583 numPhysicalOperands, \
585 class##EncodingFromString);
587 // operandIndex should always be < numOperands
588 unsigned operandIndex = 0;
589 // physicalOperandIndex should always be < numPhysicalOperands
590 unsigned physicalOperandIndex = 0;
593 case X86Local::RawFrm:
594 // Operand 1 (optional) is an address or immediate.
595 // Operand 2 (optional) is an immediate.
596 assert(numPhysicalOperands <= 2 &&
597 "Unexpected number of operands for RawFrm");
598 HANDLE_OPTIONAL(relocation)
599 HANDLE_OPTIONAL(immediate)
601 case X86Local::AddRegFrm:
602 // Operand 1 is added to the opcode.
603 // Operand 2 (optional) is an address.
604 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
605 "Unexpected number of operands for AddRegFrm");
606 HANDLE_OPERAND(opcodeModifier)
607 HANDLE_OPTIONAL(relocation)
609 case X86Local::MRMDestReg:
610 // Operand 1 is a register operand in the R/M field.
611 // Operand 2 is a register operand in the Reg/Opcode field.
612 // - In AVX, there is a register operand in the VEX.vvvv field here -
613 // Operand 3 (optional) is an immediate.
615 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
616 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
618 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
619 "Unexpected number of operands for MRMDestRegFrm");
621 HANDLE_OPERAND(rmRegister)
624 // FIXME: In AVX, the register below becomes the one encoded
625 // in ModRMVEX and the one above the one in the VEX.VVVV field
626 HANDLE_OPERAND(vvvvRegister)
628 HANDLE_OPERAND(roRegister)
629 HANDLE_OPTIONAL(immediate)
631 case X86Local::MRMDestMem:
632 // Operand 1 is a memory operand (possibly SIB-extended)
633 // Operand 2 is a register operand in the Reg/Opcode field.
634 // - In AVX, there is a register operand in the VEX.vvvv field here -
635 // Operand 3 (optional) is an immediate.
637 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
638 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
640 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
641 "Unexpected number of operands for MRMDestMemFrm");
642 HANDLE_OPERAND(memory)
645 // FIXME: In AVX, the register below becomes the one encoded
646 // in ModRMVEX and the one above the one in the VEX.VVVV field
647 HANDLE_OPERAND(vvvvRegister)
649 HANDLE_OPERAND(roRegister)
650 HANDLE_OPTIONAL(immediate)
652 case X86Local::MRMSrcReg:
653 // Operand 1 is a register operand in the Reg/Opcode field.
654 // Operand 2 is a register operand in the R/M field.
655 // - In AVX, there is a register operand in the VEX.vvvv field here -
656 // Operand 3 (optional) is an immediate.
657 // Operand 4 (optional) is an immediate.
659 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
660 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
661 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
663 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
664 "Unexpected number of operands for MRMSrcRegFrm");
666 HANDLE_OPERAND(roRegister)
669 // FIXME: In AVX, the register below becomes the one encoded
670 // in ModRMVEX and the one above the one in the VEX.VVVV field
671 HANDLE_OPERAND(vvvvRegister)
674 HANDLE_OPERAND(immediate)
676 HANDLE_OPERAND(rmRegister)
678 if (HasVEX_4VOp3Prefix)
679 HANDLE_OPERAND(vvvvRegister)
681 if (!HasMemOp4Prefix)
682 HANDLE_OPTIONAL(immediate)
683 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
684 HANDLE_OPTIONAL(immediate)
686 case X86Local::MRMSrcMem:
687 // Operand 1 is a register operand in the Reg/Opcode field.
688 // Operand 2 is a memory operand (possibly SIB-extended)
689 // - In AVX, there is a register operand in the VEX.vvvv field here -
690 // Operand 3 (optional) is an immediate.
692 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
693 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
694 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
696 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
697 "Unexpected number of operands for MRMSrcMemFrm");
699 HANDLE_OPERAND(roRegister)
702 // FIXME: In AVX, the register below becomes the one encoded
703 // in ModRMVEX and the one above the one in the VEX.VVVV field
704 HANDLE_OPERAND(vvvvRegister)
707 HANDLE_OPERAND(immediate)
709 HANDLE_OPERAND(memory)
711 if (HasVEX_4VOp3Prefix)
712 HANDLE_OPERAND(vvvvRegister)
714 if (!HasMemOp4Prefix)
715 HANDLE_OPTIONAL(immediate)
716 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
718 case X86Local::MRM0r:
719 case X86Local::MRM1r:
720 case X86Local::MRM2r:
721 case X86Local::MRM3r:
722 case X86Local::MRM4r:
723 case X86Local::MRM5r:
724 case X86Local::MRM6r:
725 case X86Local::MRM7r:
726 // Operand 1 is a register operand in the R/M field.
727 // Operand 2 (optional) is an immediate or relocation.
728 // Operand 3 (optional) is an immediate.
730 assert(numPhysicalOperands <= 3 &&
731 "Unexpected number of operands for MRMnRFrm with VEX_4V");
733 assert(numPhysicalOperands <= 3 &&
734 "Unexpected number of operands for MRMnRFrm");
736 HANDLE_OPERAND(vvvvRegister)
737 HANDLE_OPTIONAL(rmRegister)
738 HANDLE_OPTIONAL(relocation)
739 HANDLE_OPTIONAL(immediate)
741 case X86Local::MRM0m:
742 case X86Local::MRM1m:
743 case X86Local::MRM2m:
744 case X86Local::MRM3m:
745 case X86Local::MRM4m:
746 case X86Local::MRM5m:
747 case X86Local::MRM6m:
748 case X86Local::MRM7m:
749 // Operand 1 is a memory operand (possibly SIB-extended)
750 // Operand 2 (optional) is an immediate or relocation.
752 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
753 "Unexpected number of operands for MRMnMFrm");
755 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
756 "Unexpected number of operands for MRMnMFrm");
758 HANDLE_OPERAND(vvvvRegister)
759 HANDLE_OPERAND(memory)
760 HANDLE_OPTIONAL(relocation)
762 case X86Local::RawFrmImm8:
763 // operand 1 is a 16-bit immediate
764 // operand 2 is an 8-bit immediate
765 assert(numPhysicalOperands == 2 &&
766 "Unexpected number of operands for X86Local::RawFrmImm8");
767 HANDLE_OPERAND(immediate)
768 HANDLE_OPERAND(immediate)
770 case X86Local::RawFrmImm16:
771 // operand 1 is a 16-bit immediate
772 // operand 2 is a 16-bit immediate
773 HANDLE_OPERAND(immediate)
774 HANDLE_OPERAND(immediate)
776 case X86Local::MRM_F8:
777 if (Opcode == 0xc6) {
778 assert(numPhysicalOperands == 1 &&
779 "Unexpected number of operands for X86Local::MRM_F8");
780 HANDLE_OPERAND(immediate)
781 } else if (Opcode == 0xc7) {
782 assert(numPhysicalOperands == 1 &&
783 "Unexpected number of operands for X86Local::MRM_F8");
784 HANDLE_OPERAND(relocation)
787 case X86Local::MRMInitReg:
792 #undef HANDLE_OPERAND
793 #undef HANDLE_OPTIONAL
796 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
797 // Special cases where the LLVM tables are not complete
799 #define MAP(from, to) \
800 case X86Local::MRM_##from: \
801 filter = new ExactFilter(0x##from); \
804 OpcodeType opcodeType = (OpcodeType)-1;
806 ModRMFilter* filter = NULL;
807 uint8_t opcodeToSet = 0;
810 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
814 opcodeType = TWOBYTE;
818 if (needsModRMForDecode(Form))
819 filter = new ModFilter(isRegFormat(Form));
821 filter = new DumbFilter();
823 #define EXTENSION_TABLE(n) case 0x##n:
824 TWO_BYTE_EXTENSION_TABLES
825 #undef EXTENSION_TABLE
828 llvm_unreachable("Unhandled two-byte extended opcode");
829 case X86Local::MRM0r:
830 case X86Local::MRM1r:
831 case X86Local::MRM2r:
832 case X86Local::MRM3r:
833 case X86Local::MRM4r:
834 case X86Local::MRM5r:
835 case X86Local::MRM6r:
836 case X86Local::MRM7r:
837 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
839 case X86Local::MRM0m:
840 case X86Local::MRM1m:
841 case X86Local::MRM2m:
842 case X86Local::MRM3m:
843 case X86Local::MRM4m:
844 case X86Local::MRM5m:
845 case X86Local::MRM6m:
846 case X86Local::MRM7m:
847 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
853 opcodeToSet = Opcode;
858 opcodeType = THREEBYTE_38;
861 if (needsModRMForDecode(Form))
862 filter = new ModFilter(isRegFormat(Form));
864 filter = new DumbFilter();
866 #define EXTENSION_TABLE(n) case 0x##n:
867 THREE_BYTE_38_EXTENSION_TABLES
868 #undef EXTENSION_TABLE
871 llvm_unreachable("Unhandled two-byte extended opcode");
872 case X86Local::MRM0r:
873 case X86Local::MRM1r:
874 case X86Local::MRM2r:
875 case X86Local::MRM3r:
876 case X86Local::MRM4r:
877 case X86Local::MRM5r:
878 case X86Local::MRM6r:
879 case X86Local::MRM7r:
880 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
882 case X86Local::MRM0m:
883 case X86Local::MRM1m:
884 case X86Local::MRM2m:
885 case X86Local::MRM3m:
886 case X86Local::MRM4m:
887 case X86Local::MRM5m:
888 case X86Local::MRM6m:
889 case X86Local::MRM7m:
890 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
896 opcodeToSet = Opcode;
900 opcodeType = THREEBYTE_3A;
901 if (needsModRMForDecode(Form))
902 filter = new ModFilter(isRegFormat(Form));
904 filter = new DumbFilter();
905 opcodeToSet = Opcode;
908 opcodeType = THREEBYTE_A6;
909 if (needsModRMForDecode(Form))
910 filter = new ModFilter(isRegFormat(Form));
912 filter = new DumbFilter();
913 opcodeToSet = Opcode;
916 opcodeType = THREEBYTE_A7;
917 if (needsModRMForDecode(Form))
918 filter = new ModFilter(isRegFormat(Form));
920 filter = new DumbFilter();
921 opcodeToSet = Opcode;
931 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
932 opcodeType = ONEBYTE;
933 if (Form == X86Local::AddRegFrm) {
934 Spec->modifierType = MODIFIER_MODRM;
935 Spec->modifierBase = Opcode;
936 filter = new AddRegEscapeFilter(Opcode);
938 filter = new EscapeFilter(true, Opcode);
940 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
944 opcodeType = ONEBYTE;
946 #define EXTENSION_TABLE(n) case 0x##n:
947 ONE_BYTE_EXTENSION_TABLES
948 #undef EXTENSION_TABLE
951 llvm_unreachable("Fell through the cracks of a single-byte "
953 case X86Local::MRM0r:
954 case X86Local::MRM1r:
955 case X86Local::MRM2r:
956 case X86Local::MRM3r:
957 case X86Local::MRM4r:
958 case X86Local::MRM5r:
959 case X86Local::MRM6r:
960 case X86Local::MRM7r:
961 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
963 case X86Local::MRM0m:
964 case X86Local::MRM1m:
965 case X86Local::MRM2m:
966 case X86Local::MRM3m:
967 case X86Local::MRM4m:
968 case X86Local::MRM5m:
969 case X86Local::MRM6m:
970 case X86Local::MRM7m:
971 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
984 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
987 if (needsModRMForDecode(Form))
988 filter = new ModFilter(isRegFormat(Form));
990 filter = new DumbFilter();
993 opcodeToSet = Opcode;
996 assert(opcodeType != (OpcodeType)-1 &&
997 "Opcode type not set");
998 assert(filter && "Filter not set");
1000 if (Form == X86Local::AddRegFrm) {
1001 if(Spec->modifierType != MODIFIER_MODRM) {
1002 assert(opcodeToSet < 0xf9 &&
1003 "Not enough room for all ADDREG_FRM operands");
1005 uint8_t currentOpcode;
1007 for (currentOpcode = opcodeToSet;
1008 currentOpcode < opcodeToSet + 8;
1010 tables.setTableFields(opcodeType,
1014 UID, Is32Bit, IgnoresVEX_L);
1016 Spec->modifierType = MODIFIER_OPCODE;
1017 Spec->modifierBase = opcodeToSet;
1019 // modifierBase was set where MODIFIER_MODRM was set
1020 tables.setTableFields(opcodeType,
1024 UID, Is32Bit, IgnoresVEX_L);
1027 tables.setTableFields(opcodeType,
1031 UID, Is32Bit, IgnoresVEX_L);
1033 Spec->modifierType = MODIFIER_NONE;
1034 Spec->modifierBase = opcodeToSet;
1042 #define TYPE(str, type) if (s == str) return type;
1043 OperandType RecognizableInstr::typeFromString(const std::string &s,
1045 bool hasREX_WPrefix,
1046 bool hasOpSizePrefix) {
1048 // For SSE instructions, we ignore the OpSize prefix and force operand
1050 TYPE("GR16", TYPE_R16)
1051 TYPE("GR32", TYPE_R32)
1052 TYPE("GR64", TYPE_R64)
1054 if(hasREX_WPrefix) {
1055 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1057 TYPE("GR32", TYPE_R32)
1059 if(!hasOpSizePrefix) {
1060 // For instructions without an OpSize prefix, a declared 16-bit register or
1061 // immediate encoding is special.
1062 TYPE("GR16", TYPE_R16)
1063 TYPE("i16imm", TYPE_IMM16)
1065 TYPE("i16mem", TYPE_Mv)
1066 TYPE("i16imm", TYPE_IMMv)
1067 TYPE("i16i8imm", TYPE_IMMv)
1068 TYPE("GR16", TYPE_Rv)
1069 TYPE("i32mem", TYPE_Mv)
1070 TYPE("i32imm", TYPE_IMMv)
1071 TYPE("i32i8imm", TYPE_IMM32)
1072 TYPE("u32u8imm", TYPE_IMM32)
1073 TYPE("GR32", TYPE_Rv)
1074 TYPE("i64mem", TYPE_Mv)
1075 TYPE("i64i32imm", TYPE_IMM64)
1076 TYPE("i64i8imm", TYPE_IMM64)
1077 TYPE("GR64", TYPE_R64)
1078 TYPE("i8mem", TYPE_M8)
1079 TYPE("i8imm", TYPE_IMM8)
1080 TYPE("GR8", TYPE_R8)
1081 TYPE("VR128", TYPE_XMM128)
1082 TYPE("f128mem", TYPE_M128)
1083 TYPE("f256mem", TYPE_M256)
1084 TYPE("FR64", TYPE_XMM64)
1085 TYPE("f64mem", TYPE_M64FP)
1086 TYPE("sdmem", TYPE_M64FP)
1087 TYPE("FR32", TYPE_XMM32)
1088 TYPE("f32mem", TYPE_M32FP)
1089 TYPE("ssmem", TYPE_M32FP)
1090 TYPE("RST", TYPE_ST)
1091 TYPE("i128mem", TYPE_M128)
1092 TYPE("i256mem", TYPE_M256)
1093 TYPE("i64i32imm_pcrel", TYPE_REL64)
1094 TYPE("i16imm_pcrel", TYPE_REL16)
1095 TYPE("i32imm_pcrel", TYPE_REL32)
1096 TYPE("SSECC", TYPE_IMM3)
1097 TYPE("AVXCC", TYPE_IMM5)
1098 TYPE("brtarget", TYPE_RELv)
1099 TYPE("uncondbrtarget", TYPE_RELv)
1100 TYPE("brtarget8", TYPE_REL8)
1101 TYPE("f80mem", TYPE_M80FP)
1102 TYPE("lea32mem", TYPE_LEA)
1103 TYPE("lea64_32mem", TYPE_LEA)
1104 TYPE("lea64mem", TYPE_LEA)
1105 TYPE("VR64", TYPE_MM64)
1106 TYPE("i64imm", TYPE_IMMv)
1107 TYPE("opaque32mem", TYPE_M1616)
1108 TYPE("opaque48mem", TYPE_M1632)
1109 TYPE("opaque80mem", TYPE_M1664)
1110 TYPE("opaque512mem", TYPE_M512)
1111 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1112 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1113 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1114 TYPE("offset8", TYPE_MOFFS8)
1115 TYPE("offset16", TYPE_MOFFS16)
1116 TYPE("offset32", TYPE_MOFFS32)
1117 TYPE("offset64", TYPE_MOFFS64)
1118 TYPE("VR256", TYPE_XMM256)
1119 TYPE("GR16_NOAX", TYPE_Rv)
1120 TYPE("GR32_NOAX", TYPE_Rv)
1121 TYPE("GR64_NOAX", TYPE_R64)
1122 TYPE("vx32mem", TYPE_M32)
1123 TYPE("vy32mem", TYPE_M32)
1124 TYPE("vx64mem", TYPE_M64)
1125 TYPE("vy64mem", TYPE_M64)
1126 errs() << "Unhandled type string " << s << "\n";
1127 llvm_unreachable("Unhandled type string");
1131 #define ENCODING(str, encoding) if (s == str) return encoding;
1132 OperandEncoding RecognizableInstr::immediateEncodingFromString
1133 (const std::string &s,
1134 bool hasOpSizePrefix) {
1135 if(!hasOpSizePrefix) {
1136 // For instructions without an OpSize prefix, a declared 16-bit register or
1137 // immediate encoding is special.
1138 ENCODING("i16imm", ENCODING_IW)
1140 ENCODING("i32i8imm", ENCODING_IB)
1141 ENCODING("u32u8imm", ENCODING_IB)
1142 ENCODING("SSECC", ENCODING_IB)
1143 ENCODING("AVXCC", ENCODING_IB)
1144 ENCODING("i16imm", ENCODING_Iv)
1145 ENCODING("i16i8imm", ENCODING_IB)
1146 ENCODING("i32imm", ENCODING_Iv)
1147 ENCODING("i64i32imm", ENCODING_ID)
1148 ENCODING("i64i8imm", ENCODING_IB)
1149 ENCODING("i8imm", ENCODING_IB)
1150 // This is not a typo. Instructions like BLENDVPD put
1151 // register IDs in 8-bit immediates nowadays.
1152 ENCODING("VR256", ENCODING_IB)
1153 ENCODING("VR128", ENCODING_IB)
1154 ENCODING("FR32", ENCODING_IB)
1155 ENCODING("FR64", ENCODING_IB)
1156 errs() << "Unhandled immediate encoding " << s << "\n";
1157 llvm_unreachable("Unhandled immediate encoding");
1160 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1161 (const std::string &s,
1162 bool hasOpSizePrefix) {
1163 ENCODING("GR16", ENCODING_RM)
1164 ENCODING("GR32", ENCODING_RM)
1165 ENCODING("GR64", ENCODING_RM)
1166 ENCODING("GR8", ENCODING_RM)
1167 ENCODING("VR128", ENCODING_RM)
1168 ENCODING("FR64", ENCODING_RM)
1169 ENCODING("FR32", ENCODING_RM)
1170 ENCODING("VR64", ENCODING_RM)
1171 ENCODING("VR256", ENCODING_RM)
1172 errs() << "Unhandled R/M register encoding " << s << "\n";
1173 llvm_unreachable("Unhandled R/M register encoding");
1176 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1177 (const std::string &s,
1178 bool hasOpSizePrefix) {
1179 ENCODING("GR16", ENCODING_REG)
1180 ENCODING("GR32", ENCODING_REG)
1181 ENCODING("GR64", ENCODING_REG)
1182 ENCODING("GR8", ENCODING_REG)
1183 ENCODING("VR128", ENCODING_REG)
1184 ENCODING("FR64", ENCODING_REG)
1185 ENCODING("FR32", ENCODING_REG)
1186 ENCODING("VR64", ENCODING_REG)
1187 ENCODING("SEGMENT_REG", ENCODING_REG)
1188 ENCODING("DEBUG_REG", ENCODING_REG)
1189 ENCODING("CONTROL_REG", ENCODING_REG)
1190 ENCODING("VR256", ENCODING_REG)
1191 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1192 llvm_unreachable("Unhandled reg/opcode register encoding");
1195 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1196 (const std::string &s,
1197 bool hasOpSizePrefix) {
1198 ENCODING("GR32", ENCODING_VVVV)
1199 ENCODING("GR64", ENCODING_VVVV)
1200 ENCODING("FR32", ENCODING_VVVV)
1201 ENCODING("FR64", ENCODING_VVVV)
1202 ENCODING("VR128", ENCODING_VVVV)
1203 ENCODING("VR256", ENCODING_VVVV)
1204 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1205 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1208 OperandEncoding RecognizableInstr::memoryEncodingFromString
1209 (const std::string &s,
1210 bool hasOpSizePrefix) {
1211 ENCODING("i16mem", ENCODING_RM)
1212 ENCODING("i32mem", ENCODING_RM)
1213 ENCODING("i64mem", ENCODING_RM)
1214 ENCODING("i8mem", ENCODING_RM)
1215 ENCODING("ssmem", ENCODING_RM)
1216 ENCODING("sdmem", ENCODING_RM)
1217 ENCODING("f128mem", ENCODING_RM)
1218 ENCODING("f256mem", ENCODING_RM)
1219 ENCODING("f64mem", ENCODING_RM)
1220 ENCODING("f32mem", ENCODING_RM)
1221 ENCODING("i128mem", ENCODING_RM)
1222 ENCODING("i256mem", ENCODING_RM)
1223 ENCODING("f80mem", ENCODING_RM)
1224 ENCODING("lea32mem", ENCODING_RM)
1225 ENCODING("lea64_32mem", ENCODING_RM)
1226 ENCODING("lea64mem", ENCODING_RM)
1227 ENCODING("opaque32mem", ENCODING_RM)
1228 ENCODING("opaque48mem", ENCODING_RM)
1229 ENCODING("opaque80mem", ENCODING_RM)
1230 ENCODING("opaque512mem", ENCODING_RM)
1231 ENCODING("vx32mem", ENCODING_RM)
1232 ENCODING("vy32mem", ENCODING_RM)
1233 ENCODING("vx64mem", ENCODING_RM)
1234 ENCODING("vy64mem", ENCODING_RM)
1235 errs() << "Unhandled memory encoding " << s << "\n";
1236 llvm_unreachable("Unhandled memory encoding");
1239 OperandEncoding RecognizableInstr::relocationEncodingFromString
1240 (const std::string &s,
1241 bool hasOpSizePrefix) {
1242 if(!hasOpSizePrefix) {
1243 // For instructions without an OpSize prefix, a declared 16-bit register or
1244 // immediate encoding is special.
1245 ENCODING("i16imm", ENCODING_IW)
1247 ENCODING("i16imm", ENCODING_Iv)
1248 ENCODING("i16i8imm", ENCODING_IB)
1249 ENCODING("i32imm", ENCODING_Iv)
1250 ENCODING("i32i8imm", ENCODING_IB)
1251 ENCODING("i64i32imm", ENCODING_ID)
1252 ENCODING("i64i8imm", ENCODING_IB)
1253 ENCODING("i8imm", ENCODING_IB)
1254 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1255 ENCODING("i16imm_pcrel", ENCODING_IW)
1256 ENCODING("i32imm_pcrel", ENCODING_ID)
1257 ENCODING("brtarget", ENCODING_Iv)
1258 ENCODING("brtarget8", ENCODING_IB)
1259 ENCODING("i64imm", ENCODING_IO)
1260 ENCODING("offset8", ENCODING_Ia)
1261 ENCODING("offset16", ENCODING_Ia)
1262 ENCODING("offset32", ENCODING_Ia)
1263 ENCODING("offset64", ENCODING_Ia)
1264 errs() << "Unhandled relocation encoding " << s << "\n";
1265 llvm_unreachable("Unhandled relocation encoding");
1268 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1269 (const std::string &s,
1270 bool hasOpSizePrefix) {
1271 ENCODING("RST", ENCODING_I)
1272 ENCODING("GR32", ENCODING_Rv)
1273 ENCODING("GR64", ENCODING_RO)
1274 ENCODING("GR16", ENCODING_Rv)
1275 ENCODING("GR8", ENCODING_RB)
1276 ENCODING("GR16_NOAX", ENCODING_Rv)
1277 ENCODING("GR32_NOAX", ENCODING_Rv)
1278 ENCODING("GR64_NOAX", ENCODING_RO)
1279 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1280 llvm_unreachable("Unhandled opcode modifier encoding");