1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
135 #define THREE_BYTE_38_EXTENSION_TABLES \
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
233 SegOvr = byteFromRec(Rec, "SegOvrBits");
235 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
236 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
237 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
238 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
239 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
240 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
242 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
243 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
244 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
245 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
247 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
248 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
249 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
251 Name = Rec->getName();
252 AsmString = Rec->getValueAsString("AsmString");
254 Operands = &insn.Operands.OperandList;
256 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
257 (Name.find("CRC32") != Name.npos);
258 HasFROperands = hasFROperands();
259 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
261 // Check for 64-bit inst which does not require REX
264 // FIXME: Is there some better way to check for In64BitMode?
265 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
266 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
267 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
271 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
276 // FIXME: These instructions aren't marked as 64-bit in any way
277 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
278 Rec->getName() == "MASKMOVDQU64" ||
279 Rec->getName() == "POPFS64" ||
280 Rec->getName() == "POPGS64" ||
281 Rec->getName() == "PUSHFS64" ||
282 Rec->getName() == "PUSHGS64" ||
283 Rec->getName() == "REX64_PREFIX" ||
284 Rec->getName().find("MOV64") != Name.npos ||
285 Rec->getName().find("PUSH64") != Name.npos ||
286 Rec->getName().find("POP64") != Name.npos;
288 ShouldBeEmitted = true;
291 void RecognizableInstr::processInstr(DisassemblerTables &tables,
292 const CodeGenInstruction &insn,
295 // Ignore "asm parser only" instructions.
296 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
299 RecognizableInstr recogInstr(tables, insn, uid);
301 recogInstr.emitInstructionSpecifier(tables);
303 if (recogInstr.shouldBeEmitted())
304 recogInstr.emitDecodePath(tables);
307 #define EVEX_KB(n) (HasEVEX_K && HasEVEX_B? n##_K_B : \
308 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))
310 InstructionContext RecognizableInstr::insnContext() const {
311 InstructionContext insnContext;
314 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
315 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
316 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
319 if (HasVEX_LPrefix && HasVEX_WPrefix) {
321 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
322 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
323 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
324 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
325 Prefix == X86Local::TAXD)
326 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
328 insnContext = EVEX_KB(IC_EVEX_L_W);
329 } else if (HasVEX_LPrefix) {
332 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
333 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
334 insnContext = EVEX_KB(IC_EVEX_L_XS);
335 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
336 Prefix == X86Local::TAXD)
337 insnContext = EVEX_KB(IC_EVEX_L_XD);
339 insnContext = EVEX_KB(IC_EVEX_L);
341 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
344 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
345 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
346 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
347 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
348 Prefix == X86Local::TAXD)
349 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
351 insnContext = EVEX_KB(IC_EVEX_L2_W);
352 } else if (HasEVEX_L2Prefix) {
355 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
356 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
357 Prefix == X86Local::TAXD)
358 insnContext = EVEX_KB(IC_EVEX_L2_XD);
359 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
360 insnContext = EVEX_KB(IC_EVEX_L2_XS);
362 insnContext = EVEX_KB(IC_EVEX_L2);
364 else if (HasVEX_WPrefix) {
367 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
368 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
369 insnContext = EVEX_KB(IC_EVEX_W_XS);
370 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
371 Prefix == X86Local::TAXD)
372 insnContext = EVEX_KB(IC_EVEX_W_XD);
374 insnContext = EVEX_KB(IC_EVEX_W);
377 else if (HasOpSizePrefix)
378 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
379 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
380 Prefix == X86Local::TAXD)
381 insnContext = EVEX_KB(IC_EVEX_XD);
382 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
383 insnContext = EVEX_KB(IC_EVEX_XS);
385 insnContext = EVEX_KB(IC_EVEX);
387 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
388 if (HasVEX_LPrefix && HasVEX_WPrefix) {
390 insnContext = IC_VEX_L_W_OPSIZE;
391 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
392 insnContext = IC_VEX_L_W_XS;
393 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
394 Prefix == X86Local::TAXD)
395 insnContext = IC_VEX_L_W_XD;
397 insnContext = IC_VEX_L_W;
398 } else if (HasOpSizePrefix && HasVEX_LPrefix)
399 insnContext = IC_VEX_L_OPSIZE;
400 else if (HasOpSizePrefix && HasVEX_WPrefix)
401 insnContext = IC_VEX_W_OPSIZE;
402 else if (HasOpSizePrefix)
403 insnContext = IC_VEX_OPSIZE;
404 else if (HasVEX_LPrefix &&
405 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
406 insnContext = IC_VEX_L_XS;
407 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
408 Prefix == X86Local::T8XD ||
409 Prefix == X86Local::TAXD))
410 insnContext = IC_VEX_L_XD;
411 else if (HasVEX_WPrefix &&
412 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
413 insnContext = IC_VEX_W_XS;
414 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
415 Prefix == X86Local::T8XD ||
416 Prefix == X86Local::TAXD))
417 insnContext = IC_VEX_W_XD;
418 else if (HasVEX_WPrefix)
419 insnContext = IC_VEX_W;
420 else if (HasVEX_LPrefix)
421 insnContext = IC_VEX_L;
422 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
423 Prefix == X86Local::TAXD)
424 insnContext = IC_VEX_XD;
425 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
426 insnContext = IC_VEX_XS;
428 insnContext = IC_VEX;
429 } else if (Is64Bit || HasREX_WPrefix) {
430 if (HasREX_WPrefix && HasOpSizePrefix)
431 insnContext = IC_64BIT_REXW_OPSIZE;
432 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
433 Prefix == X86Local::T8XD ||
434 Prefix == X86Local::TAXD))
435 insnContext = IC_64BIT_XD_OPSIZE;
436 else if (HasOpSizePrefix &&
437 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
438 insnContext = IC_64BIT_XS_OPSIZE;
439 else if (HasOpSizePrefix)
440 insnContext = IC_64BIT_OPSIZE;
441 else if (HasAdSizePrefix)
442 insnContext = IC_64BIT_ADSIZE;
443 else if (HasREX_WPrefix &&
444 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
445 insnContext = IC_64BIT_REXW_XS;
446 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
447 Prefix == X86Local::T8XD ||
448 Prefix == X86Local::TAXD))
449 insnContext = IC_64BIT_REXW_XD;
450 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
451 Prefix == X86Local::TAXD)
452 insnContext = IC_64BIT_XD;
453 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
454 insnContext = IC_64BIT_XS;
455 else if (HasREX_WPrefix)
456 insnContext = IC_64BIT_REXW;
458 insnContext = IC_64BIT;
460 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
461 Prefix == X86Local::T8XD ||
462 Prefix == X86Local::TAXD))
463 insnContext = IC_XD_OPSIZE;
464 else if (HasOpSizePrefix &&
465 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
466 insnContext = IC_XS_OPSIZE;
467 else if (HasOpSizePrefix)
468 insnContext = IC_OPSIZE;
469 else if (HasAdSizePrefix)
470 insnContext = IC_ADSIZE;
471 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
472 Prefix == X86Local::TAXD)
474 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
475 Prefix == X86Local::REP)
484 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
489 // Filter out intrinsics
491 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
493 if (Form == X86Local::Pseudo ||
494 (IsCodeGenOnly && Name.find("_REV") == Name.npos &&
495 Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos))
496 return FILTER_STRONG;
499 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
500 // printed as a separate "instruction".
502 if (Name.find("_Int") != Name.npos ||
503 Name.find("Int_") != Name.npos)
504 return FILTER_STRONG;
506 // Filter out instructions with segment override prefixes.
507 // They're too messy to handle now and we'll special case them if needed.
510 return FILTER_STRONG;
518 // Filter out instructions with a LOCK prefix;
519 // prefer forms that do not have the prefix
523 // Filter out alternate forms of AVX instructions
524 if (Name.find("_alt") != Name.npos ||
525 Name.find("XrYr") != Name.npos ||
526 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
527 Name.find("_64mr") != Name.npos ||
528 Name.find("Xrr") != Name.npos ||
529 Name.find("rr64") != Name.npos)
534 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
536 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
539 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
541 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos &&
542 Name != "MOVZPQILo2PQIrr")
544 if (Name.find("Fs") != Name.npos)
546 if (Name == "PUSH64i16" ||
547 Name == "MOVPQI2QImr" ||
548 Name == "VMOVPQI2QImr" ||
549 Name == "MMX_MOVD64rrv164" ||
550 Name == "MOV64ri64i32" ||
551 Name == "VMASKMOVDQU64" ||
552 Name == "VEXTRACTPSrr64")
555 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
556 // For now, just prefer the REP versions.
557 if (Name == "XACQUIRE_PREFIX" ||
558 Name == "XRELEASE_PREFIX")
561 if (HasFROperands && Name.find("MOV") != Name.npos &&
562 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
563 (Name.find("to") != Name.npos)))
564 return FILTER_STRONG;
566 return FILTER_NORMAL;
569 bool RecognizableInstr::hasFROperands() const {
570 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
571 unsigned numOperands = OperandList.size();
573 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
574 const std::string &recName = OperandList[operandIndex].Rec->getName();
576 if (recName.find("FR") != recName.npos)
582 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
583 unsigned &physicalOperandIndex,
584 unsigned &numPhysicalOperands,
585 const unsigned *operandMapping,
586 OperandEncoding (*encodingFromString)
588 bool hasOpSizePrefix)) {
590 if (physicalOperandIndex >= numPhysicalOperands)
593 assert(physicalOperandIndex < numPhysicalOperands);
596 while (operandMapping[operandIndex] != operandIndex) {
597 Spec->operands[operandIndex].encoding = ENCODING_DUP;
598 Spec->operands[operandIndex].type =
599 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
603 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
605 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
607 Spec->operands[operandIndex].type = typeFromString(typeName,
613 ++physicalOperandIndex;
616 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
619 if (!ShouldBeEmitted)
624 Spec->filtered = true;
627 ShouldBeEmitted = false;
633 Spec->insnContext = insnContext();
635 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
637 unsigned numOperands = OperandList.size();
638 unsigned numPhysicalOperands = 0;
640 // operandMapping maps from operands in OperandList to their originals.
641 // If operandMapping[i] != i, then the entry is a duplicate.
642 unsigned operandMapping[X86_MAX_OPERANDS];
643 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
645 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
646 if (OperandList[operandIndex].Constraints.size()) {
647 const CGIOperandList::ConstraintInfo &Constraint =
648 OperandList[operandIndex].Constraints[0];
649 if (Constraint.isTied()) {
650 operandMapping[operandIndex] = operandIndex;
651 operandMapping[Constraint.getTiedOperand()] = operandIndex;
653 ++numPhysicalOperands;
654 operandMapping[operandIndex] = operandIndex;
657 ++numPhysicalOperands;
658 operandMapping[operandIndex] = operandIndex;
662 #define HANDLE_OPERAND(class) \
663 handleOperand(false, \
665 physicalOperandIndex, \
666 numPhysicalOperands, \
668 class##EncodingFromString);
670 #define HANDLE_OPTIONAL(class) \
671 handleOperand(true, \
673 physicalOperandIndex, \
674 numPhysicalOperands, \
676 class##EncodingFromString);
678 // operandIndex should always be < numOperands
679 unsigned operandIndex = 0;
680 // physicalOperandIndex should always be < numPhysicalOperands
681 unsigned physicalOperandIndex = 0;
684 case X86Local::RawFrm:
685 // Operand 1 (optional) is an address or immediate.
686 // Operand 2 (optional) is an immediate.
687 assert(numPhysicalOperands <= 2 &&
688 "Unexpected number of operands for RawFrm");
689 HANDLE_OPTIONAL(relocation)
690 HANDLE_OPTIONAL(immediate)
692 case X86Local::AddRegFrm:
693 // Operand 1 is added to the opcode.
694 // Operand 2 (optional) is an address.
695 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
696 "Unexpected number of operands for AddRegFrm");
697 HANDLE_OPERAND(opcodeModifier)
698 HANDLE_OPTIONAL(relocation)
700 case X86Local::MRMDestReg:
701 // Operand 1 is a register operand in the R/M field.
702 // Operand 2 is a register operand in the Reg/Opcode field.
703 // - In AVX, there is a register operand in the VEX.vvvv field here -
704 // Operand 3 (optional) is an immediate.
706 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
707 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
709 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
710 "Unexpected number of operands for MRMDestRegFrm");
712 HANDLE_OPERAND(rmRegister)
715 // FIXME: In AVX, the register below becomes the one encoded
716 // in ModRMVEX and the one above the one in the VEX.VVVV field
717 HANDLE_OPERAND(vvvvRegister)
719 HANDLE_OPERAND(roRegister)
720 HANDLE_OPTIONAL(immediate)
722 case X86Local::MRMDestMem:
723 // Operand 1 is a memory operand (possibly SIB-extended)
724 // Operand 2 is a register operand in the Reg/Opcode field.
725 // - In AVX, there is a register operand in the VEX.vvvv field here -
726 // Operand 3 (optional) is an immediate.
728 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
729 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
731 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
732 "Unexpected number of operands for MRMDestMemFrm");
733 HANDLE_OPERAND(memory)
736 HANDLE_OPERAND(writemaskRegister)
739 // FIXME: In AVX, the register below becomes the one encoded
740 // in ModRMVEX and the one above the one in the VEX.VVVV field
741 HANDLE_OPERAND(vvvvRegister)
743 HANDLE_OPERAND(roRegister)
744 HANDLE_OPTIONAL(immediate)
746 case X86Local::MRMSrcReg:
747 // Operand 1 is a register operand in the Reg/Opcode field.
748 // Operand 2 is a register operand in the R/M field.
749 // - In AVX, there is a register operand in the VEX.vvvv field here -
750 // Operand 3 (optional) is an immediate.
751 // Operand 4 (optional) is an immediate.
753 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
754 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
755 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
757 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
758 "Unexpected number of operands for MRMSrcRegFrm");
760 HANDLE_OPERAND(roRegister)
763 HANDLE_OPERAND(writemaskRegister)
766 // FIXME: In AVX, the register below becomes the one encoded
767 // in ModRMVEX and the one above the one in the VEX.VVVV field
768 HANDLE_OPERAND(vvvvRegister)
771 HANDLE_OPERAND(immediate)
773 HANDLE_OPERAND(rmRegister)
775 if (HasVEX_4VOp3Prefix)
776 HANDLE_OPERAND(vvvvRegister)
778 if (!HasMemOp4Prefix)
779 HANDLE_OPTIONAL(immediate)
780 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
781 HANDLE_OPTIONAL(immediate)
783 case X86Local::MRMSrcMem:
784 // Operand 1 is a register operand in the Reg/Opcode field.
785 // Operand 2 is a memory operand (possibly SIB-extended)
786 // - In AVX, there is a register operand in the VEX.vvvv field here -
787 // Operand 3 (optional) is an immediate.
789 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
790 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
791 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
793 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
794 "Unexpected number of operands for MRMSrcMemFrm");
796 HANDLE_OPERAND(roRegister)
799 HANDLE_OPERAND(writemaskRegister)
802 // FIXME: In AVX, the register below becomes the one encoded
803 // in ModRMVEX and the one above the one in the VEX.VVVV field
804 HANDLE_OPERAND(vvvvRegister)
807 HANDLE_OPERAND(immediate)
809 HANDLE_OPERAND(memory)
811 if (HasVEX_4VOp3Prefix)
812 HANDLE_OPERAND(vvvvRegister)
814 if (!HasMemOp4Prefix)
815 HANDLE_OPTIONAL(immediate)
816 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
818 case X86Local::MRM0r:
819 case X86Local::MRM1r:
820 case X86Local::MRM2r:
821 case X86Local::MRM3r:
822 case X86Local::MRM4r:
823 case X86Local::MRM5r:
824 case X86Local::MRM6r:
825 case X86Local::MRM7r:
827 // Operand 1 is a register operand in the R/M field.
828 // Operand 2 (optional) is an immediate or relocation.
829 // Operand 3 (optional) is an immediate.
830 unsigned kOp = (HasEVEX_K) ? 1:0;
831 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
832 if (numPhysicalOperands > 3 + kOp + Op4v)
833 llvm_unreachable("Unexpected number of operands for MRMnr");
836 HANDLE_OPERAND(vvvvRegister)
839 HANDLE_OPERAND(writemaskRegister)
840 HANDLE_OPTIONAL(rmRegister)
841 HANDLE_OPTIONAL(relocation)
842 HANDLE_OPTIONAL(immediate)
844 case X86Local::MRM0m:
845 case X86Local::MRM1m:
846 case X86Local::MRM2m:
847 case X86Local::MRM3m:
848 case X86Local::MRM4m:
849 case X86Local::MRM5m:
850 case X86Local::MRM6m:
851 case X86Local::MRM7m:
853 // Operand 1 is a memory operand (possibly SIB-extended)
854 // Operand 2 (optional) is an immediate or relocation.
855 unsigned kOp = (HasEVEX_K) ? 1:0;
856 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
857 if (numPhysicalOperands < 1 + kOp + Op4v ||
858 numPhysicalOperands > 2 + kOp + Op4v)
859 llvm_unreachable("Unexpected number of operands for MRMnm");
862 HANDLE_OPERAND(vvvvRegister)
864 HANDLE_OPERAND(writemaskRegister)
865 HANDLE_OPERAND(memory)
866 HANDLE_OPTIONAL(relocation)
868 case X86Local::RawFrmImm8:
869 // operand 1 is a 16-bit immediate
870 // operand 2 is an 8-bit immediate
871 assert(numPhysicalOperands == 2 &&
872 "Unexpected number of operands for X86Local::RawFrmImm8");
873 HANDLE_OPERAND(immediate)
874 HANDLE_OPERAND(immediate)
876 case X86Local::RawFrmImm16:
877 // operand 1 is a 16-bit immediate
878 // operand 2 is a 16-bit immediate
879 HANDLE_OPERAND(immediate)
880 HANDLE_OPERAND(immediate)
882 case X86Local::MRM_F8:
883 if (Opcode == 0xc6) {
884 assert(numPhysicalOperands == 1 &&
885 "Unexpected number of operands for X86Local::MRM_F8");
886 HANDLE_OPERAND(immediate)
887 } else if (Opcode == 0xc7) {
888 assert(numPhysicalOperands == 1 &&
889 "Unexpected number of operands for X86Local::MRM_F8");
890 HANDLE_OPERAND(relocation)
893 case X86Local::MRMInitReg:
898 #undef HANDLE_OPERAND
899 #undef HANDLE_OPTIONAL
902 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
903 // Special cases where the LLVM tables are not complete
905 #define MAP(from, to) \
906 case X86Local::MRM_##from: \
907 filter = new ExactFilter(0x##from); \
910 OpcodeType opcodeType = (OpcodeType)-1;
912 ModRMFilter* filter = NULL;
913 uint8_t opcodeToSet = 0;
916 default: llvm_unreachable("Invalid prefix!");
917 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
921 opcodeType = TWOBYTE;
925 if (needsModRMForDecode(Form))
926 filter = new ModFilter(isRegFormat(Form));
928 filter = new DumbFilter();
930 #define EXTENSION_TABLE(n) case 0x##n:
931 TWO_BYTE_EXTENSION_TABLES
932 #undef EXTENSION_TABLE
935 llvm_unreachable("Unhandled two-byte extended opcode");
936 case X86Local::MRM0r:
937 case X86Local::MRM1r:
938 case X86Local::MRM2r:
939 case X86Local::MRM3r:
940 case X86Local::MRM4r:
941 case X86Local::MRM5r:
942 case X86Local::MRM6r:
943 case X86Local::MRM7r:
944 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
946 case X86Local::MRM0m:
947 case X86Local::MRM1m:
948 case X86Local::MRM2m:
949 case X86Local::MRM3m:
950 case X86Local::MRM4m:
951 case X86Local::MRM5m:
952 case X86Local::MRM6m:
953 case X86Local::MRM7m:
954 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
960 opcodeToSet = Opcode;
965 opcodeType = THREEBYTE_38;
968 if (needsModRMForDecode(Form))
969 filter = new ModFilter(isRegFormat(Form));
971 filter = new DumbFilter();
973 #define EXTENSION_TABLE(n) case 0x##n:
974 THREE_BYTE_38_EXTENSION_TABLES
975 #undef EXTENSION_TABLE
978 llvm_unreachable("Unhandled two-byte extended opcode");
979 case X86Local::MRM0r:
980 case X86Local::MRM1r:
981 case X86Local::MRM2r:
982 case X86Local::MRM3r:
983 case X86Local::MRM4r:
984 case X86Local::MRM5r:
985 case X86Local::MRM6r:
986 case X86Local::MRM7r:
987 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
989 case X86Local::MRM0m:
990 case X86Local::MRM1m:
991 case X86Local::MRM2m:
992 case X86Local::MRM3m:
993 case X86Local::MRM4m:
994 case X86Local::MRM5m:
995 case X86Local::MRM6m:
996 case X86Local::MRM7m:
997 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1002 } // switch (Opcode)
1003 opcodeToSet = Opcode;
1005 case X86Local::P_TA:
1006 case X86Local::TAXD:
1007 opcodeType = THREEBYTE_3A;
1008 if (needsModRMForDecode(Form))
1009 filter = new ModFilter(isRegFormat(Form));
1011 filter = new DumbFilter();
1012 opcodeToSet = Opcode;
1015 opcodeType = THREEBYTE_A6;
1016 if (needsModRMForDecode(Form))
1017 filter = new ModFilter(isRegFormat(Form));
1019 filter = new DumbFilter();
1020 opcodeToSet = Opcode;
1023 opcodeType = THREEBYTE_A7;
1024 if (needsModRMForDecode(Form))
1025 filter = new ModFilter(isRegFormat(Form));
1027 filter = new DumbFilter();
1028 opcodeToSet = Opcode;
1030 case X86Local::XOP8:
1031 opcodeType = XOP8_MAP;
1032 if (needsModRMForDecode(Form))
1033 filter = new ModFilter(isRegFormat(Form));
1035 filter = new DumbFilter();
1036 opcodeToSet = Opcode;
1038 case X86Local::XOP9:
1039 opcodeType = XOP9_MAP;
1042 if (needsModRMForDecode(Form))
1043 filter = new ModFilter(isRegFormat(Form));
1045 filter = new DumbFilter();
1047 #define EXTENSION_TABLE(n) case 0x##n:
1048 XOP9_MAP_EXTENSION_TABLES
1049 #undef EXTENSION_TABLE
1052 llvm_unreachable("Unhandled XOP9 extended opcode");
1053 case X86Local::MRM0r:
1054 case X86Local::MRM1r:
1055 case X86Local::MRM2r:
1056 case X86Local::MRM3r:
1057 case X86Local::MRM4r:
1058 case X86Local::MRM5r:
1059 case X86Local::MRM6r:
1060 case X86Local::MRM7r:
1061 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1063 case X86Local::MRM0m:
1064 case X86Local::MRM1m:
1065 case X86Local::MRM2m:
1066 case X86Local::MRM3m:
1067 case X86Local::MRM4m:
1068 case X86Local::MRM5m:
1069 case X86Local::MRM6m:
1070 case X86Local::MRM7m:
1071 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1076 } // switch (Opcode)
1077 opcodeToSet = Opcode;
1079 case X86Local::XOPA:
1080 opcodeType = XOPA_MAP;
1081 if (needsModRMForDecode(Form))
1082 filter = new ModFilter(isRegFormat(Form));
1084 filter = new DumbFilter();
1085 opcodeToSet = Opcode;
1095 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1096 opcodeType = ONEBYTE;
1097 if (Form == X86Local::AddRegFrm) {
1098 Spec->modifierType = MODIFIER_MODRM;
1099 Spec->modifierBase = Opcode;
1100 filter = new AddRegEscapeFilter(Opcode);
1102 filter = new EscapeFilter(true, Opcode);
1104 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1108 opcodeType = ONEBYTE;
1110 #define EXTENSION_TABLE(n) case 0x##n:
1111 ONE_BYTE_EXTENSION_TABLES
1112 #undef EXTENSION_TABLE
1115 llvm_unreachable("Fell through the cracks of a single-byte "
1117 case X86Local::MRM0r:
1118 case X86Local::MRM1r:
1119 case X86Local::MRM2r:
1120 case X86Local::MRM3r:
1121 case X86Local::MRM4r:
1122 case X86Local::MRM5r:
1123 case X86Local::MRM6r:
1124 case X86Local::MRM7r:
1125 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1127 case X86Local::MRM0m:
1128 case X86Local::MRM1m:
1129 case X86Local::MRM2m:
1130 case X86Local::MRM3m:
1131 case X86Local::MRM4m:
1132 case X86Local::MRM5m:
1133 case X86Local::MRM6m:
1134 case X86Local::MRM7m:
1135 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1148 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1151 if (needsModRMForDecode(Form))
1152 filter = new ModFilter(isRegFormat(Form));
1154 filter = new DumbFilter();
1156 } // switch (Opcode)
1157 opcodeToSet = Opcode;
1158 } // switch (Prefix)
1160 assert(opcodeType != (OpcodeType)-1 &&
1161 "Opcode type not set");
1162 assert(filter && "Filter not set");
1164 if (Form == X86Local::AddRegFrm) {
1165 if(Spec->modifierType != MODIFIER_MODRM) {
1166 assert(opcodeToSet < 0xf9 &&
1167 "Not enough room for all ADDREG_FRM operands");
1169 uint8_t currentOpcode;
1171 for (currentOpcode = opcodeToSet;
1172 currentOpcode < opcodeToSet + 8;
1174 tables.setTableFields(opcodeType,
1178 UID, Is32Bit, IgnoresVEX_L);
1180 Spec->modifierType = MODIFIER_OPCODE;
1181 Spec->modifierBase = opcodeToSet;
1183 // modifierBase was set where MODIFIER_MODRM was set
1184 tables.setTableFields(opcodeType,
1188 UID, Is32Bit, IgnoresVEX_L);
1191 tables.setTableFields(opcodeType,
1195 UID, Is32Bit, IgnoresVEX_L);
1197 Spec->modifierType = MODIFIER_NONE;
1198 Spec->modifierBase = opcodeToSet;
1206 #define TYPE(str, type) if (s == str) return type;
1207 OperandType RecognizableInstr::typeFromString(const std::string &s,
1209 bool hasREX_WPrefix,
1210 bool hasOpSizePrefix) {
1212 // For SSE instructions, we ignore the OpSize prefix and force operand
1214 TYPE("GR16", TYPE_R16)
1215 TYPE("GR32", TYPE_R32)
1216 TYPE("GR64", TYPE_R64)
1218 if(hasREX_WPrefix) {
1219 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1221 TYPE("GR32", TYPE_R32)
1223 if(!hasOpSizePrefix) {
1224 // For instructions without an OpSize prefix, a declared 16-bit register or
1225 // immediate encoding is special.
1226 TYPE("GR16", TYPE_R16)
1227 TYPE("i16imm", TYPE_IMM16)
1229 TYPE("i16mem", TYPE_Mv)
1230 TYPE("i16imm", TYPE_IMMv)
1231 TYPE("i16i8imm", TYPE_IMMv)
1232 TYPE("GR16", TYPE_Rv)
1233 TYPE("i32mem", TYPE_Mv)
1234 TYPE("i32imm", TYPE_IMMv)
1235 TYPE("i32i8imm", TYPE_IMM32)
1236 TYPE("u32u8imm", TYPE_IMM32)
1237 TYPE("GR32", TYPE_Rv)
1238 TYPE("i64mem", TYPE_Mv)
1239 TYPE("i64i32imm", TYPE_IMM64)
1240 TYPE("i64i8imm", TYPE_IMM64)
1241 TYPE("GR64", TYPE_R64)
1242 TYPE("i8mem", TYPE_M8)
1243 TYPE("i8imm", TYPE_IMM8)
1244 TYPE("GR8", TYPE_R8)
1245 TYPE("VR128", TYPE_XMM128)
1246 TYPE("VR128X", TYPE_XMM128)
1247 TYPE("f128mem", TYPE_M128)
1248 TYPE("f256mem", TYPE_M256)
1249 TYPE("f512mem", TYPE_M512)
1250 TYPE("FR64", TYPE_XMM64)
1251 TYPE("FR64X", TYPE_XMM64)
1252 TYPE("f64mem", TYPE_M64FP)
1253 TYPE("sdmem", TYPE_M64FP)
1254 TYPE("FR32", TYPE_XMM32)
1255 TYPE("FR32X", TYPE_XMM32)
1256 TYPE("f32mem", TYPE_M32FP)
1257 TYPE("ssmem", TYPE_M32FP)
1258 TYPE("RST", TYPE_ST)
1259 TYPE("i128mem", TYPE_M128)
1260 TYPE("i256mem", TYPE_M256)
1261 TYPE("i512mem", TYPE_M512)
1262 TYPE("i64i32imm_pcrel", TYPE_REL64)
1263 TYPE("i16imm_pcrel", TYPE_REL16)
1264 TYPE("i32imm_pcrel", TYPE_REL32)
1265 TYPE("SSECC", TYPE_IMM3)
1266 TYPE("AVXCC", TYPE_IMM5)
1267 TYPE("brtarget", TYPE_RELv)
1268 TYPE("uncondbrtarget", TYPE_RELv)
1269 TYPE("brtarget8", TYPE_REL8)
1270 TYPE("f80mem", TYPE_M80FP)
1271 TYPE("lea32mem", TYPE_LEA)
1272 TYPE("lea64_32mem", TYPE_LEA)
1273 TYPE("lea64mem", TYPE_LEA)
1274 TYPE("VR64", TYPE_MM64)
1275 TYPE("i64imm", TYPE_IMMv)
1276 TYPE("opaque32mem", TYPE_M1616)
1277 TYPE("opaque48mem", TYPE_M1632)
1278 TYPE("opaque80mem", TYPE_M1664)
1279 TYPE("opaque512mem", TYPE_M512)
1280 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1281 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1282 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1283 TYPE("offset8", TYPE_MOFFS8)
1284 TYPE("offset16", TYPE_MOFFS16)
1285 TYPE("offset32", TYPE_MOFFS32)
1286 TYPE("offset64", TYPE_MOFFS64)
1287 TYPE("VR256", TYPE_XMM256)
1288 TYPE("VR256X", TYPE_XMM256)
1289 TYPE("VR512", TYPE_XMM512)
1290 TYPE("VK8", TYPE_VK8)
1291 TYPE("VK8WM", TYPE_VK8)
1292 TYPE("VK16", TYPE_VK16)
1293 TYPE("VK16WM", TYPE_VK16)
1294 TYPE("GR16_NOAX", TYPE_Rv)
1295 TYPE("GR32_NOAX", TYPE_Rv)
1296 TYPE("GR64_NOAX", TYPE_R64)
1297 TYPE("vx32mem", TYPE_M32)
1298 TYPE("vy32mem", TYPE_M32)
1299 TYPE("vz32mem", TYPE_M32)
1300 TYPE("vx64mem", TYPE_M64)
1301 TYPE("vy64mem", TYPE_M64)
1302 TYPE("vy64xmem", TYPE_M64)
1303 TYPE("vz64mem", TYPE_M64)
1304 errs() << "Unhandled type string " << s << "\n";
1305 llvm_unreachable("Unhandled type string");
1309 #define ENCODING(str, encoding) if (s == str) return encoding;
1310 OperandEncoding RecognizableInstr::immediateEncodingFromString
1311 (const std::string &s,
1312 bool hasOpSizePrefix) {
1313 if(!hasOpSizePrefix) {
1314 // For instructions without an OpSize prefix, a declared 16-bit register or
1315 // immediate encoding is special.
1316 ENCODING("i16imm", ENCODING_IW)
1318 ENCODING("i32i8imm", ENCODING_IB)
1319 ENCODING("u32u8imm", ENCODING_IB)
1320 ENCODING("SSECC", ENCODING_IB)
1321 ENCODING("AVXCC", ENCODING_IB)
1322 ENCODING("i16imm", ENCODING_Iv)
1323 ENCODING("i16i8imm", ENCODING_IB)
1324 ENCODING("i32imm", ENCODING_Iv)
1325 ENCODING("i64i32imm", ENCODING_ID)
1326 ENCODING("i64i8imm", ENCODING_IB)
1327 ENCODING("i8imm", ENCODING_IB)
1328 // This is not a typo. Instructions like BLENDVPD put
1329 // register IDs in 8-bit immediates nowadays.
1330 ENCODING("FR32", ENCODING_IB)
1331 ENCODING("FR64", ENCODING_IB)
1332 ENCODING("VR128", ENCODING_IB)
1333 ENCODING("VR256", ENCODING_IB)
1334 ENCODING("FR32X", ENCODING_IB)
1335 ENCODING("FR64X", ENCODING_IB)
1336 ENCODING("VR128X", ENCODING_IB)
1337 ENCODING("VR256X", ENCODING_IB)
1338 ENCODING("VR512", ENCODING_IB)
1339 errs() << "Unhandled immediate encoding " << s << "\n";
1340 llvm_unreachable("Unhandled immediate encoding");
1343 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1344 (const std::string &s,
1345 bool hasOpSizePrefix) {
1346 ENCODING("GR16", ENCODING_RM)
1347 ENCODING("GR32", ENCODING_RM)
1348 ENCODING("GR64", ENCODING_RM)
1349 ENCODING("GR8", ENCODING_RM)
1350 ENCODING("VR128", ENCODING_RM)
1351 ENCODING("VR128X", ENCODING_RM)
1352 ENCODING("FR64", ENCODING_RM)
1353 ENCODING("FR32", ENCODING_RM)
1354 ENCODING("FR64X", ENCODING_RM)
1355 ENCODING("FR32X", ENCODING_RM)
1356 ENCODING("VR64", ENCODING_RM)
1357 ENCODING("VR256", ENCODING_RM)
1358 ENCODING("VR256X", ENCODING_RM)
1359 ENCODING("VR512", ENCODING_RM)
1360 ENCODING("VK8", ENCODING_RM)
1361 ENCODING("VK16", ENCODING_RM)
1362 errs() << "Unhandled R/M register encoding " << s << "\n";
1363 llvm_unreachable("Unhandled R/M register encoding");
1366 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1367 (const std::string &s,
1368 bool hasOpSizePrefix) {
1369 ENCODING("GR16", ENCODING_REG)
1370 ENCODING("GR32", ENCODING_REG)
1371 ENCODING("GR64", ENCODING_REG)
1372 ENCODING("GR8", ENCODING_REG)
1373 ENCODING("VR128", ENCODING_REG)
1374 ENCODING("FR64", ENCODING_REG)
1375 ENCODING("FR32", ENCODING_REG)
1376 ENCODING("VR64", ENCODING_REG)
1377 ENCODING("SEGMENT_REG", ENCODING_REG)
1378 ENCODING("DEBUG_REG", ENCODING_REG)
1379 ENCODING("CONTROL_REG", ENCODING_REG)
1380 ENCODING("VR256", ENCODING_REG)
1381 ENCODING("VR256X", ENCODING_REG)
1382 ENCODING("VR128X", ENCODING_REG)
1383 ENCODING("FR64X", ENCODING_REG)
1384 ENCODING("FR32X", ENCODING_REG)
1385 ENCODING("VR512", ENCODING_REG)
1386 ENCODING("VK8", ENCODING_REG)
1387 ENCODING("VK16", ENCODING_REG)
1388 ENCODING("VK8WM", ENCODING_REG)
1389 ENCODING("VK16WM", ENCODING_REG)
1390 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1391 llvm_unreachable("Unhandled reg/opcode register encoding");
1394 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1395 (const std::string &s,
1396 bool hasOpSizePrefix) {
1397 ENCODING("GR32", ENCODING_VVVV)
1398 ENCODING("GR64", ENCODING_VVVV)
1399 ENCODING("FR32", ENCODING_VVVV)
1400 ENCODING("FR64", ENCODING_VVVV)
1401 ENCODING("VR128", ENCODING_VVVV)
1402 ENCODING("VR256", ENCODING_VVVV)
1403 ENCODING("FR32X", ENCODING_VVVV)
1404 ENCODING("FR64X", ENCODING_VVVV)
1405 ENCODING("VR128X", ENCODING_VVVV)
1406 ENCODING("VR256X", ENCODING_VVVV)
1407 ENCODING("VR512", ENCODING_VVVV)
1408 ENCODING("VK8", ENCODING_VVVV)
1409 ENCODING("VK16", ENCODING_VVVV)
1410 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1411 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1414 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1415 (const std::string &s,
1416 bool hasOpSizePrefix) {
1417 ENCODING("VK8WM", ENCODING_WRITEMASK)
1418 ENCODING("VK16WM", ENCODING_WRITEMASK)
1419 errs() << "Unhandled mask register encoding " << s << "\n";
1420 llvm_unreachable("Unhandled mask register encoding");
1423 OperandEncoding RecognizableInstr::memoryEncodingFromString
1424 (const std::string &s,
1425 bool hasOpSizePrefix) {
1426 ENCODING("i16mem", ENCODING_RM)
1427 ENCODING("i32mem", ENCODING_RM)
1428 ENCODING("i64mem", ENCODING_RM)
1429 ENCODING("i8mem", ENCODING_RM)
1430 ENCODING("ssmem", ENCODING_RM)
1431 ENCODING("sdmem", ENCODING_RM)
1432 ENCODING("f128mem", ENCODING_RM)
1433 ENCODING("f256mem", ENCODING_RM)
1434 ENCODING("f512mem", ENCODING_RM)
1435 ENCODING("f64mem", ENCODING_RM)
1436 ENCODING("f32mem", ENCODING_RM)
1437 ENCODING("i128mem", ENCODING_RM)
1438 ENCODING("i256mem", ENCODING_RM)
1439 ENCODING("i512mem", ENCODING_RM)
1440 ENCODING("f80mem", ENCODING_RM)
1441 ENCODING("lea32mem", ENCODING_RM)
1442 ENCODING("lea64_32mem", ENCODING_RM)
1443 ENCODING("lea64mem", ENCODING_RM)
1444 ENCODING("opaque32mem", ENCODING_RM)
1445 ENCODING("opaque48mem", ENCODING_RM)
1446 ENCODING("opaque80mem", ENCODING_RM)
1447 ENCODING("opaque512mem", ENCODING_RM)
1448 ENCODING("vx32mem", ENCODING_RM)
1449 ENCODING("vy32mem", ENCODING_RM)
1450 ENCODING("vz32mem", ENCODING_RM)
1451 ENCODING("vx64mem", ENCODING_RM)
1452 ENCODING("vy64mem", ENCODING_RM)
1453 ENCODING("vy64xmem", ENCODING_RM)
1454 ENCODING("vz64mem", ENCODING_RM)
1455 errs() << "Unhandled memory encoding " << s << "\n";
1456 llvm_unreachable("Unhandled memory encoding");
1459 OperandEncoding RecognizableInstr::relocationEncodingFromString
1460 (const std::string &s,
1461 bool hasOpSizePrefix) {
1462 if(!hasOpSizePrefix) {
1463 // For instructions without an OpSize prefix, a declared 16-bit register or
1464 // immediate encoding is special.
1465 ENCODING("i16imm", ENCODING_IW)
1467 ENCODING("i16imm", ENCODING_Iv)
1468 ENCODING("i16i8imm", ENCODING_IB)
1469 ENCODING("i32imm", ENCODING_Iv)
1470 ENCODING("i32i8imm", ENCODING_IB)
1471 ENCODING("i64i32imm", ENCODING_ID)
1472 ENCODING("i64i8imm", ENCODING_IB)
1473 ENCODING("i8imm", ENCODING_IB)
1474 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1475 ENCODING("i16imm_pcrel", ENCODING_IW)
1476 ENCODING("i32imm_pcrel", ENCODING_ID)
1477 ENCODING("brtarget", ENCODING_Iv)
1478 ENCODING("brtarget8", ENCODING_IB)
1479 ENCODING("i64imm", ENCODING_IO)
1480 ENCODING("offset8", ENCODING_Ia)
1481 ENCODING("offset16", ENCODING_Ia)
1482 ENCODING("offset32", ENCODING_Ia)
1483 ENCODING("offset64", ENCODING_Ia)
1484 errs() << "Unhandled relocation encoding " << s << "\n";
1485 llvm_unreachable("Unhandled relocation encoding");
1488 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1489 (const std::string &s,
1490 bool hasOpSizePrefix) {
1491 ENCODING("RST", ENCODING_I)
1492 ENCODING("GR32", ENCODING_Rv)
1493 ENCODING("GR64", ENCODING_RO)
1494 ENCODING("GR16", ENCODING_Rv)
1495 ENCODING("GR8", ENCODING_RB)
1496 ENCODING("GR16_NOAX", ENCODING_Rv)
1497 ENCODING("GR32_NOAX", ENCODING_Rv)
1498 ENCODING("GR64_NOAX", ENCODING_RO)
1499 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1500 llvm_unreachable("Unhandled opcode modifier encoding");