1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
135 #define THREE_BYTE_38_EXTENSION_TABLES \
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
233 SegOvr = byteFromRec(Rec, "SegOvrBits");
235 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
236 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
237 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
238 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
239 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
240 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
242 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
243 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
244 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
245 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
247 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
248 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
249 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
250 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
251 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
253 Name = Rec->getName();
254 AsmString = Rec->getValueAsString("AsmString");
256 Operands = &insn.Operands.OperandList;
258 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
259 (Name.find("CRC32") != Name.npos);
260 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
262 // Check for 64-bit inst which does not require REX
265 // FIXME: Is there some better way to check for In64BitMode?
266 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
267 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
268 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
269 Predicates[i]->getName().find("In32Bit") != Name.npos) {
273 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
279 ShouldBeEmitted = true;
282 void RecognizableInstr::processInstr(DisassemblerTables &tables,
283 const CodeGenInstruction &insn,
286 // Ignore "asm parser only" instructions.
287 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
290 RecognizableInstr recogInstr(tables, insn, uid);
292 recogInstr.emitInstructionSpecifier();
294 if (recogInstr.shouldBeEmitted())
295 recogInstr.emitDecodePath(tables);
298 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
299 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
300 (HasEVEX_KZ ? n##_KZ : \
301 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
303 InstructionContext RecognizableInstr::insnContext() const {
304 InstructionContext insnContext;
307 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
308 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
309 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
312 if (HasVEX_LPrefix && HasVEX_WPrefix) {
314 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
315 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
316 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
317 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
318 Prefix == X86Local::TAXD)
319 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
321 insnContext = EVEX_KB(IC_EVEX_L_W);
322 } else if (HasVEX_LPrefix) {
325 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
326 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
327 insnContext = EVEX_KB(IC_EVEX_L_XS);
328 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
329 Prefix == X86Local::TAXD)
330 insnContext = EVEX_KB(IC_EVEX_L_XD);
332 insnContext = EVEX_KB(IC_EVEX_L);
334 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
337 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
338 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
339 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
340 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
341 Prefix == X86Local::TAXD)
342 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
344 insnContext = EVEX_KB(IC_EVEX_L2_W);
345 } else if (HasEVEX_L2Prefix) {
348 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
349 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
350 Prefix == X86Local::TAXD)
351 insnContext = EVEX_KB(IC_EVEX_L2_XD);
352 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
353 insnContext = EVEX_KB(IC_EVEX_L2_XS);
355 insnContext = EVEX_KB(IC_EVEX_L2);
357 else if (HasVEX_WPrefix) {
360 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
361 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
362 insnContext = EVEX_KB(IC_EVEX_W_XS);
363 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
364 Prefix == X86Local::TAXD)
365 insnContext = EVEX_KB(IC_EVEX_W_XD);
367 insnContext = EVEX_KB(IC_EVEX_W);
370 else if (HasOpSizePrefix)
371 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
372 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
373 Prefix == X86Local::TAXD)
374 insnContext = EVEX_KB(IC_EVEX_XD);
375 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
376 insnContext = EVEX_KB(IC_EVEX_XS);
378 insnContext = EVEX_KB(IC_EVEX);
380 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
381 if (HasVEX_LPrefix && HasVEX_WPrefix) {
383 insnContext = IC_VEX_L_W_OPSIZE;
384 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
385 insnContext = IC_VEX_L_W_XS;
386 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
387 Prefix == X86Local::TAXD)
388 insnContext = IC_VEX_L_W_XD;
390 insnContext = IC_VEX_L_W;
391 } else if (HasOpSizePrefix && HasVEX_LPrefix)
392 insnContext = IC_VEX_L_OPSIZE;
393 else if (HasOpSizePrefix && HasVEX_WPrefix)
394 insnContext = IC_VEX_W_OPSIZE;
395 else if (HasOpSizePrefix)
396 insnContext = IC_VEX_OPSIZE;
397 else if (HasVEX_LPrefix &&
398 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
399 insnContext = IC_VEX_L_XS;
400 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
401 Prefix == X86Local::T8XD ||
402 Prefix == X86Local::TAXD))
403 insnContext = IC_VEX_L_XD;
404 else if (HasVEX_WPrefix &&
405 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
406 insnContext = IC_VEX_W_XS;
407 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
408 Prefix == X86Local::T8XD ||
409 Prefix == X86Local::TAXD))
410 insnContext = IC_VEX_W_XD;
411 else if (HasVEX_WPrefix)
412 insnContext = IC_VEX_W;
413 else if (HasVEX_LPrefix)
414 insnContext = IC_VEX_L;
415 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
416 Prefix == X86Local::TAXD)
417 insnContext = IC_VEX_XD;
418 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
419 insnContext = IC_VEX_XS;
421 insnContext = IC_VEX;
422 } else if (Is64Bit || HasREX_WPrefix) {
423 if (HasREX_WPrefix && HasOpSizePrefix)
424 insnContext = IC_64BIT_REXW_OPSIZE;
425 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
426 Prefix == X86Local::T8XD ||
427 Prefix == X86Local::TAXD))
428 insnContext = IC_64BIT_XD_OPSIZE;
429 else if (HasOpSizePrefix &&
430 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
431 insnContext = IC_64BIT_XS_OPSIZE;
432 else if (HasOpSizePrefix)
433 insnContext = IC_64BIT_OPSIZE;
434 else if (HasAdSizePrefix)
435 insnContext = IC_64BIT_ADSIZE;
436 else if (HasREX_WPrefix &&
437 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
438 insnContext = IC_64BIT_REXW_XS;
439 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
440 Prefix == X86Local::T8XD ||
441 Prefix == X86Local::TAXD))
442 insnContext = IC_64BIT_REXW_XD;
443 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
444 Prefix == X86Local::TAXD)
445 insnContext = IC_64BIT_XD;
446 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
447 insnContext = IC_64BIT_XS;
448 else if (HasREX_WPrefix)
449 insnContext = IC_64BIT_REXW;
451 insnContext = IC_64BIT;
453 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
454 Prefix == X86Local::T8XD ||
455 Prefix == X86Local::TAXD))
456 insnContext = IC_XD_OPSIZE;
457 else if (HasOpSizePrefix &&
458 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
459 insnContext = IC_XS_OPSIZE;
460 else if (HasOpSizePrefix)
461 insnContext = IC_OPSIZE;
462 else if (HasAdSizePrefix)
463 insnContext = IC_ADSIZE;
464 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
465 Prefix == X86Local::TAXD)
467 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
468 Prefix == X86Local::REP)
477 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
482 // Filter out intrinsics
484 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
486 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
487 return FILTER_STRONG;
490 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
491 // printed as a separate "instruction".
493 // Filter out instructions with segment override prefixes.
494 // They're too messy to handle now and we'll special case them if needed.
497 return FILTER_STRONG;
505 // Filter out instructions with a LOCK prefix;
506 // prefer forms that do not have the prefix
512 if (Name == "PUSH64i16" ||
513 Name == "MOVPQI2QImr" ||
514 Name == "VMOVPQI2QImr" ||
515 Name == "VMASKMOVDQU64")
518 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
519 // For now, just prefer the REP versions.
520 if (Name == "XACQUIRE_PREFIX" ||
521 Name == "XRELEASE_PREFIX")
524 return FILTER_NORMAL;
527 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
528 unsigned &physicalOperandIndex,
529 unsigned &numPhysicalOperands,
530 const unsigned *operandMapping,
531 OperandEncoding (*encodingFromString)
533 bool hasOpSizePrefix)) {
535 if (physicalOperandIndex >= numPhysicalOperands)
538 assert(physicalOperandIndex < numPhysicalOperands);
541 while (operandMapping[operandIndex] != operandIndex) {
542 Spec->operands[operandIndex].encoding = ENCODING_DUP;
543 Spec->operands[operandIndex].type =
544 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
548 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
550 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
552 Spec->operands[operandIndex].type = typeFromString(typeName,
558 ++physicalOperandIndex;
561 void RecognizableInstr::emitInstructionSpecifier() {
564 if (!ShouldBeEmitted)
569 Spec->filtered = true;
572 ShouldBeEmitted = false;
578 Spec->insnContext = insnContext();
580 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
582 unsigned numOperands = OperandList.size();
583 unsigned numPhysicalOperands = 0;
585 // operandMapping maps from operands in OperandList to their originals.
586 // If operandMapping[i] != i, then the entry is a duplicate.
587 unsigned operandMapping[X86_MAX_OPERANDS];
588 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
590 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
591 if (OperandList[operandIndex].Constraints.size()) {
592 const CGIOperandList::ConstraintInfo &Constraint =
593 OperandList[operandIndex].Constraints[0];
594 if (Constraint.isTied()) {
595 operandMapping[operandIndex] = operandIndex;
596 operandMapping[Constraint.getTiedOperand()] = operandIndex;
598 ++numPhysicalOperands;
599 operandMapping[operandIndex] = operandIndex;
602 ++numPhysicalOperands;
603 operandMapping[operandIndex] = operandIndex;
607 #define HANDLE_OPERAND(class) \
608 handleOperand(false, \
610 physicalOperandIndex, \
611 numPhysicalOperands, \
613 class##EncodingFromString);
615 #define HANDLE_OPTIONAL(class) \
616 handleOperand(true, \
618 physicalOperandIndex, \
619 numPhysicalOperands, \
621 class##EncodingFromString);
623 // operandIndex should always be < numOperands
624 unsigned operandIndex = 0;
625 // physicalOperandIndex should always be < numPhysicalOperands
626 unsigned physicalOperandIndex = 0;
629 case X86Local::RawFrm:
630 // Operand 1 (optional) is an address or immediate.
631 // Operand 2 (optional) is an immediate.
632 assert(numPhysicalOperands <= 2 &&
633 "Unexpected number of operands for RawFrm");
634 HANDLE_OPTIONAL(relocation)
635 HANDLE_OPTIONAL(immediate)
637 case X86Local::AddRegFrm:
638 // Operand 1 is added to the opcode.
639 // Operand 2 (optional) is an address.
640 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
641 "Unexpected number of operands for AddRegFrm");
642 HANDLE_OPERAND(opcodeModifier)
643 HANDLE_OPTIONAL(relocation)
645 case X86Local::MRMDestReg:
646 // Operand 1 is a register operand in the R/M field.
647 // Operand 2 is a register operand in the Reg/Opcode field.
648 // - In AVX, there is a register operand in the VEX.vvvv field here -
649 // Operand 3 (optional) is an immediate.
651 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
652 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
654 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
655 "Unexpected number of operands for MRMDestRegFrm");
657 HANDLE_OPERAND(rmRegister)
660 // FIXME: In AVX, the register below becomes the one encoded
661 // in ModRMVEX and the one above the one in the VEX.VVVV field
662 HANDLE_OPERAND(vvvvRegister)
664 HANDLE_OPERAND(roRegister)
665 HANDLE_OPTIONAL(immediate)
667 case X86Local::MRMDestMem:
668 // Operand 1 is a memory operand (possibly SIB-extended)
669 // Operand 2 is a register operand in the Reg/Opcode field.
670 // - In AVX, there is a register operand in the VEX.vvvv field here -
671 // Operand 3 (optional) is an immediate.
673 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
674 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
676 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
677 "Unexpected number of operands for MRMDestMemFrm");
678 HANDLE_OPERAND(memory)
681 HANDLE_OPERAND(writemaskRegister)
684 // FIXME: In AVX, the register below becomes the one encoded
685 // in ModRMVEX and the one above the one in the VEX.VVVV field
686 HANDLE_OPERAND(vvvvRegister)
688 HANDLE_OPERAND(roRegister)
689 HANDLE_OPTIONAL(immediate)
691 case X86Local::MRMSrcReg:
692 // Operand 1 is a register operand in the Reg/Opcode field.
693 // Operand 2 is a register operand in the R/M field.
694 // - In AVX, there is a register operand in the VEX.vvvv field here -
695 // Operand 3 (optional) is an immediate.
696 // Operand 4 (optional) is an immediate.
698 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
699 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
700 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
702 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
703 "Unexpected number of operands for MRMSrcRegFrm");
705 HANDLE_OPERAND(roRegister)
708 HANDLE_OPERAND(writemaskRegister)
711 // FIXME: In AVX, the register below becomes the one encoded
712 // in ModRMVEX and the one above the one in the VEX.VVVV field
713 HANDLE_OPERAND(vvvvRegister)
716 HANDLE_OPERAND(immediate)
718 HANDLE_OPERAND(rmRegister)
720 if (HasVEX_4VOp3Prefix)
721 HANDLE_OPERAND(vvvvRegister)
723 if (!HasMemOp4Prefix)
724 HANDLE_OPTIONAL(immediate)
725 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
726 HANDLE_OPTIONAL(immediate)
728 case X86Local::MRMSrcMem:
729 // Operand 1 is a register operand in the Reg/Opcode field.
730 // Operand 2 is a memory operand (possibly SIB-extended)
731 // - In AVX, there is a register operand in the VEX.vvvv field here -
732 // Operand 3 (optional) is an immediate.
734 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
735 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
736 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
738 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
739 "Unexpected number of operands for MRMSrcMemFrm");
741 HANDLE_OPERAND(roRegister)
744 HANDLE_OPERAND(writemaskRegister)
747 // FIXME: In AVX, the register below becomes the one encoded
748 // in ModRMVEX and the one above the one in the VEX.VVVV field
749 HANDLE_OPERAND(vvvvRegister)
752 HANDLE_OPERAND(immediate)
754 HANDLE_OPERAND(memory)
756 if (HasVEX_4VOp3Prefix)
757 HANDLE_OPERAND(vvvvRegister)
759 if (!HasMemOp4Prefix)
760 HANDLE_OPTIONAL(immediate)
761 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
763 case X86Local::MRM0r:
764 case X86Local::MRM1r:
765 case X86Local::MRM2r:
766 case X86Local::MRM3r:
767 case X86Local::MRM4r:
768 case X86Local::MRM5r:
769 case X86Local::MRM6r:
770 case X86Local::MRM7r:
772 // Operand 1 is a register operand in the R/M field.
773 // Operand 2 (optional) is an immediate or relocation.
774 // Operand 3 (optional) is an immediate.
775 unsigned kOp = (HasEVEX_K) ? 1:0;
776 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
777 if (numPhysicalOperands > 3 + kOp + Op4v)
778 llvm_unreachable("Unexpected number of operands for MRMnr");
781 HANDLE_OPERAND(vvvvRegister)
784 HANDLE_OPERAND(writemaskRegister)
785 HANDLE_OPTIONAL(rmRegister)
786 HANDLE_OPTIONAL(relocation)
787 HANDLE_OPTIONAL(immediate)
789 case X86Local::MRM0m:
790 case X86Local::MRM1m:
791 case X86Local::MRM2m:
792 case X86Local::MRM3m:
793 case X86Local::MRM4m:
794 case X86Local::MRM5m:
795 case X86Local::MRM6m:
796 case X86Local::MRM7m:
798 // Operand 1 is a memory operand (possibly SIB-extended)
799 // Operand 2 (optional) is an immediate or relocation.
800 unsigned kOp = (HasEVEX_K) ? 1:0;
801 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
802 if (numPhysicalOperands < 1 + kOp + Op4v ||
803 numPhysicalOperands > 2 + kOp + Op4v)
804 llvm_unreachable("Unexpected number of operands for MRMnm");
807 HANDLE_OPERAND(vvvvRegister)
809 HANDLE_OPERAND(writemaskRegister)
810 HANDLE_OPERAND(memory)
811 HANDLE_OPTIONAL(relocation)
813 case X86Local::RawFrmImm8:
814 // operand 1 is a 16-bit immediate
815 // operand 2 is an 8-bit immediate
816 assert(numPhysicalOperands == 2 &&
817 "Unexpected number of operands for X86Local::RawFrmImm8");
818 HANDLE_OPERAND(immediate)
819 HANDLE_OPERAND(immediate)
821 case X86Local::RawFrmImm16:
822 // operand 1 is a 16-bit immediate
823 // operand 2 is a 16-bit immediate
824 HANDLE_OPERAND(immediate)
825 HANDLE_OPERAND(immediate)
827 case X86Local::MRM_F8:
828 if (Opcode == 0xc6) {
829 assert(numPhysicalOperands == 1 &&
830 "Unexpected number of operands for X86Local::MRM_F8");
831 HANDLE_OPERAND(immediate)
832 } else if (Opcode == 0xc7) {
833 assert(numPhysicalOperands == 1 &&
834 "Unexpected number of operands for X86Local::MRM_F8");
835 HANDLE_OPERAND(relocation)
838 case X86Local::MRMInitReg:
843 #undef HANDLE_OPERAND
844 #undef HANDLE_OPTIONAL
847 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
848 // Special cases where the LLVM tables are not complete
850 #define MAP(from, to) \
851 case X86Local::MRM_##from: \
852 filter = new ExactFilter(0x##from); \
855 OpcodeType opcodeType = (OpcodeType)-1;
857 ModRMFilter* filter = NULL;
858 uint8_t opcodeToSet = 0;
861 default: llvm_unreachable("Invalid prefix!");
862 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
866 opcodeType = TWOBYTE;
870 if (needsModRMForDecode(Form))
871 filter = new ModFilter(isRegFormat(Form));
873 filter = new DumbFilter();
875 #define EXTENSION_TABLE(n) case 0x##n:
876 TWO_BYTE_EXTENSION_TABLES
877 #undef EXTENSION_TABLE
880 llvm_unreachable("Unhandled two-byte extended opcode");
881 case X86Local::MRM0r:
882 case X86Local::MRM1r:
883 case X86Local::MRM2r:
884 case X86Local::MRM3r:
885 case X86Local::MRM4r:
886 case X86Local::MRM5r:
887 case X86Local::MRM6r:
888 case X86Local::MRM7r:
889 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
891 case X86Local::MRM0m:
892 case X86Local::MRM1m:
893 case X86Local::MRM2m:
894 case X86Local::MRM3m:
895 case X86Local::MRM4m:
896 case X86Local::MRM5m:
897 case X86Local::MRM6m:
898 case X86Local::MRM7m:
899 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
905 opcodeToSet = Opcode;
910 opcodeType = THREEBYTE_38;
913 if (needsModRMForDecode(Form))
914 filter = new ModFilter(isRegFormat(Form));
916 filter = new DumbFilter();
918 #define EXTENSION_TABLE(n) case 0x##n:
919 THREE_BYTE_38_EXTENSION_TABLES
920 #undef EXTENSION_TABLE
923 llvm_unreachable("Unhandled two-byte extended opcode");
924 case X86Local::MRM0r:
925 case X86Local::MRM1r:
926 case X86Local::MRM2r:
927 case X86Local::MRM3r:
928 case X86Local::MRM4r:
929 case X86Local::MRM5r:
930 case X86Local::MRM6r:
931 case X86Local::MRM7r:
932 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
934 case X86Local::MRM0m:
935 case X86Local::MRM1m:
936 case X86Local::MRM2m:
937 case X86Local::MRM3m:
938 case X86Local::MRM4m:
939 case X86Local::MRM5m:
940 case X86Local::MRM6m:
941 case X86Local::MRM7m:
942 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
948 opcodeToSet = Opcode;
952 opcodeType = THREEBYTE_3A;
953 if (needsModRMForDecode(Form))
954 filter = new ModFilter(isRegFormat(Form));
956 filter = new DumbFilter();
957 opcodeToSet = Opcode;
960 opcodeType = THREEBYTE_A6;
961 if (needsModRMForDecode(Form))
962 filter = new ModFilter(isRegFormat(Form));
964 filter = new DumbFilter();
965 opcodeToSet = Opcode;
968 opcodeType = THREEBYTE_A7;
969 if (needsModRMForDecode(Form))
970 filter = new ModFilter(isRegFormat(Form));
972 filter = new DumbFilter();
973 opcodeToSet = Opcode;
976 opcodeType = XOP8_MAP;
977 if (needsModRMForDecode(Form))
978 filter = new ModFilter(isRegFormat(Form));
980 filter = new DumbFilter();
981 opcodeToSet = Opcode;
984 opcodeType = XOP9_MAP;
987 if (needsModRMForDecode(Form))
988 filter = new ModFilter(isRegFormat(Form));
990 filter = new DumbFilter();
992 #define EXTENSION_TABLE(n) case 0x##n:
993 XOP9_MAP_EXTENSION_TABLES
994 #undef EXTENSION_TABLE
997 llvm_unreachable("Unhandled XOP9 extended opcode");
998 case X86Local::MRM0r:
999 case X86Local::MRM1r:
1000 case X86Local::MRM2r:
1001 case X86Local::MRM3r:
1002 case X86Local::MRM4r:
1003 case X86Local::MRM5r:
1004 case X86Local::MRM6r:
1005 case X86Local::MRM7r:
1006 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1008 case X86Local::MRM0m:
1009 case X86Local::MRM1m:
1010 case X86Local::MRM2m:
1011 case X86Local::MRM3m:
1012 case X86Local::MRM4m:
1013 case X86Local::MRM5m:
1014 case X86Local::MRM6m:
1015 case X86Local::MRM7m:
1016 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1021 } // switch (Opcode)
1022 opcodeToSet = Opcode;
1024 case X86Local::XOPA:
1025 opcodeType = XOPA_MAP;
1026 if (needsModRMForDecode(Form))
1027 filter = new ModFilter(isRegFormat(Form));
1029 filter = new DumbFilter();
1030 opcodeToSet = Opcode;
1040 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1041 assert(Form == X86Local::RawFrm);
1042 opcodeType = ONEBYTE;
1043 filter = new ExactFilter(Opcode);
1044 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1048 opcodeType = ONEBYTE;
1050 #define EXTENSION_TABLE(n) case 0x##n:
1051 ONE_BYTE_EXTENSION_TABLES
1052 #undef EXTENSION_TABLE
1055 llvm_unreachable("Fell through the cracks of a single-byte "
1057 case X86Local::MRM0r:
1058 case X86Local::MRM1r:
1059 case X86Local::MRM2r:
1060 case X86Local::MRM3r:
1061 case X86Local::MRM4r:
1062 case X86Local::MRM5r:
1063 case X86Local::MRM6r:
1064 case X86Local::MRM7r:
1065 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1067 case X86Local::MRM0m:
1068 case X86Local::MRM1m:
1069 case X86Local::MRM2m:
1070 case X86Local::MRM3m:
1071 case X86Local::MRM4m:
1072 case X86Local::MRM5m:
1073 case X86Local::MRM6m:
1074 case X86Local::MRM7m:
1075 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1090 llvm_unreachable("Unhandled escape opcode form");
1091 case X86Local::MRM0r:
1092 case X86Local::MRM1r:
1093 case X86Local::MRM2r:
1094 case X86Local::MRM3r:
1095 case X86Local::MRM4r:
1096 case X86Local::MRM5r:
1097 case X86Local::MRM6r:
1098 case X86Local::MRM7r:
1099 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1101 case X86Local::MRM0m:
1102 case X86Local::MRM1m:
1103 case X86Local::MRM2m:
1104 case X86Local::MRM3m:
1105 case X86Local::MRM4m:
1106 case X86Local::MRM5m:
1107 case X86Local::MRM6m:
1108 case X86Local::MRM7m:
1109 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1114 if (needsModRMForDecode(Form))
1115 filter = new ModFilter(isRegFormat(Form));
1117 filter = new DumbFilter();
1119 } // switch (Opcode)
1120 opcodeToSet = Opcode;
1121 } // switch (Prefix)
1123 assert(opcodeType != (OpcodeType)-1 &&
1124 "Opcode type not set");
1125 assert(filter && "Filter not set");
1127 if (Form == X86Local::AddRegFrm) {
1128 assert(((opcodeToSet & 7) == 0) &&
1129 "ADDREG_FRM opcode not aligned");
1131 uint8_t currentOpcode;
1133 for (currentOpcode = opcodeToSet;
1134 currentOpcode < opcodeToSet + 8;
1136 tables.setTableFields(opcodeType,
1140 UID, Is32Bit, IgnoresVEX_L);
1142 tables.setTableFields(opcodeType,
1146 UID, Is32Bit, IgnoresVEX_L);
1154 #define TYPE(str, type) if (s == str) return type;
1155 OperandType RecognizableInstr::typeFromString(const std::string &s,
1157 bool hasREX_WPrefix,
1158 bool hasOpSizePrefix) {
1160 // For SSE instructions, we ignore the OpSize prefix and force operand
1162 TYPE("GR16", TYPE_R16)
1163 TYPE("GR32", TYPE_R32)
1164 TYPE("GR64", TYPE_R64)
1166 if(hasREX_WPrefix) {
1167 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1169 TYPE("GR32", TYPE_R32)
1171 if(!hasOpSizePrefix) {
1172 // For instructions without an OpSize prefix, a declared 16-bit register or
1173 // immediate encoding is special.
1174 TYPE("GR16", TYPE_R16)
1175 TYPE("i16imm", TYPE_IMM16)
1177 TYPE("i16mem", TYPE_Mv)
1178 TYPE("i16imm", TYPE_IMMv)
1179 TYPE("i16i8imm", TYPE_IMMv)
1180 TYPE("GR16", TYPE_Rv)
1181 TYPE("i32mem", TYPE_Mv)
1182 TYPE("i32imm", TYPE_IMMv)
1183 TYPE("i32i8imm", TYPE_IMM32)
1184 TYPE("u32u8imm", TYPE_IMM32)
1185 TYPE("GR32", TYPE_Rv)
1186 TYPE("GR32orGR64", TYPE_R32)
1187 TYPE("i64mem", TYPE_Mv)
1188 TYPE("i64i32imm", TYPE_IMM64)
1189 TYPE("i64i8imm", TYPE_IMM64)
1190 TYPE("GR64", TYPE_R64)
1191 TYPE("i8mem", TYPE_M8)
1192 TYPE("i8imm", TYPE_IMM8)
1193 TYPE("GR8", TYPE_R8)
1194 TYPE("VR128", TYPE_XMM128)
1195 TYPE("VR128X", TYPE_XMM128)
1196 TYPE("f128mem", TYPE_M128)
1197 TYPE("f256mem", TYPE_M256)
1198 TYPE("f512mem", TYPE_M512)
1199 TYPE("FR64", TYPE_XMM64)
1200 TYPE("FR64X", TYPE_XMM64)
1201 TYPE("f64mem", TYPE_M64FP)
1202 TYPE("sdmem", TYPE_M64FP)
1203 TYPE("FR32", TYPE_XMM32)
1204 TYPE("FR32X", TYPE_XMM32)
1205 TYPE("f32mem", TYPE_M32FP)
1206 TYPE("ssmem", TYPE_M32FP)
1207 TYPE("RST", TYPE_ST)
1208 TYPE("i128mem", TYPE_M128)
1209 TYPE("i256mem", TYPE_M256)
1210 TYPE("i512mem", TYPE_M512)
1211 TYPE("i64i32imm_pcrel", TYPE_REL64)
1212 TYPE("i16imm_pcrel", TYPE_REL16)
1213 TYPE("i32imm_pcrel", TYPE_REL32)
1214 TYPE("SSECC", TYPE_IMM3)
1215 TYPE("AVXCC", TYPE_IMM5)
1216 TYPE("AVX512RC", TYPE_IMM32)
1217 TYPE("brtarget", TYPE_RELv)
1218 TYPE("uncondbrtarget", TYPE_RELv)
1219 TYPE("brtarget8", TYPE_REL8)
1220 TYPE("f80mem", TYPE_M80FP)
1221 TYPE("lea32mem", TYPE_LEA)
1222 TYPE("lea64_32mem", TYPE_LEA)
1223 TYPE("lea64mem", TYPE_LEA)
1224 TYPE("VR64", TYPE_MM64)
1225 TYPE("i64imm", TYPE_IMMv)
1226 TYPE("opaque32mem", TYPE_M1616)
1227 TYPE("opaque48mem", TYPE_M1632)
1228 TYPE("opaque80mem", TYPE_M1664)
1229 TYPE("opaque512mem", TYPE_M512)
1230 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1231 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1232 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1233 TYPE("offset8", TYPE_MOFFS8)
1234 TYPE("offset16", TYPE_MOFFS16)
1235 TYPE("offset32", TYPE_MOFFS32)
1236 TYPE("offset64", TYPE_MOFFS64)
1237 TYPE("VR256", TYPE_XMM256)
1238 TYPE("VR256X", TYPE_XMM256)
1239 TYPE("VR512", TYPE_XMM512)
1240 TYPE("VK1", TYPE_VK1)
1241 TYPE("VK1WM", TYPE_VK1)
1242 TYPE("VK8", TYPE_VK8)
1243 TYPE("VK8WM", TYPE_VK8)
1244 TYPE("VK16", TYPE_VK16)
1245 TYPE("VK16WM", TYPE_VK16)
1246 TYPE("GR16_NOAX", TYPE_Rv)
1247 TYPE("GR32_NOAX", TYPE_Rv)
1248 TYPE("GR64_NOAX", TYPE_R64)
1249 TYPE("vx32mem", TYPE_M32)
1250 TYPE("vy32mem", TYPE_M32)
1251 TYPE("vz32mem", TYPE_M32)
1252 TYPE("vx64mem", TYPE_M64)
1253 TYPE("vy64mem", TYPE_M64)
1254 TYPE("vy64xmem", TYPE_M64)
1255 TYPE("vz64mem", TYPE_M64)
1256 errs() << "Unhandled type string " << s << "\n";
1257 llvm_unreachable("Unhandled type string");
1261 #define ENCODING(str, encoding) if (s == str) return encoding;
1262 OperandEncoding RecognizableInstr::immediateEncodingFromString
1263 (const std::string &s,
1264 bool hasOpSizePrefix) {
1265 if(!hasOpSizePrefix) {
1266 // For instructions without an OpSize prefix, a declared 16-bit register or
1267 // immediate encoding is special.
1268 ENCODING("i16imm", ENCODING_IW)
1270 ENCODING("i32i8imm", ENCODING_IB)
1271 ENCODING("u32u8imm", ENCODING_IB)
1272 ENCODING("SSECC", ENCODING_IB)
1273 ENCODING("AVXCC", ENCODING_IB)
1274 ENCODING("AVX512RC", ENCODING_IB)
1275 ENCODING("i16imm", ENCODING_Iv)
1276 ENCODING("i16i8imm", ENCODING_IB)
1277 ENCODING("i32imm", ENCODING_Iv)
1278 ENCODING("i64i32imm", ENCODING_ID)
1279 ENCODING("i64i8imm", ENCODING_IB)
1280 ENCODING("i8imm", ENCODING_IB)
1281 // This is not a typo. Instructions like BLENDVPD put
1282 // register IDs in 8-bit immediates nowadays.
1283 ENCODING("FR32", ENCODING_IB)
1284 ENCODING("FR64", ENCODING_IB)
1285 ENCODING("VR128", ENCODING_IB)
1286 ENCODING("VR256", ENCODING_IB)
1287 ENCODING("FR32X", ENCODING_IB)
1288 ENCODING("FR64X", ENCODING_IB)
1289 ENCODING("VR128X", ENCODING_IB)
1290 ENCODING("VR256X", ENCODING_IB)
1291 ENCODING("VR512", ENCODING_IB)
1292 errs() << "Unhandled immediate encoding " << s << "\n";
1293 llvm_unreachable("Unhandled immediate encoding");
1296 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1297 (const std::string &s,
1298 bool hasOpSizePrefix) {
1299 ENCODING("RST", ENCODING_FP)
1300 ENCODING("GR16", ENCODING_RM)
1301 ENCODING("GR32", ENCODING_RM)
1302 ENCODING("GR32orGR64", ENCODING_RM)
1303 ENCODING("GR64", ENCODING_RM)
1304 ENCODING("GR8", ENCODING_RM)
1305 ENCODING("VR128", ENCODING_RM)
1306 ENCODING("VR128X", ENCODING_RM)
1307 ENCODING("FR64", ENCODING_RM)
1308 ENCODING("FR32", ENCODING_RM)
1309 ENCODING("FR64X", ENCODING_RM)
1310 ENCODING("FR32X", ENCODING_RM)
1311 ENCODING("VR64", ENCODING_RM)
1312 ENCODING("VR256", ENCODING_RM)
1313 ENCODING("VR256X", ENCODING_RM)
1314 ENCODING("VR512", ENCODING_RM)
1315 ENCODING("VK1", ENCODING_RM)
1316 ENCODING("VK8", ENCODING_RM)
1317 ENCODING("VK16", ENCODING_RM)
1318 errs() << "Unhandled R/M register encoding " << s << "\n";
1319 llvm_unreachable("Unhandled R/M register encoding");
1322 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1323 (const std::string &s,
1324 bool hasOpSizePrefix) {
1325 ENCODING("GR16", ENCODING_REG)
1326 ENCODING("GR32", ENCODING_REG)
1327 ENCODING("GR32orGR64", ENCODING_REG)
1328 ENCODING("GR64", ENCODING_REG)
1329 ENCODING("GR8", ENCODING_REG)
1330 ENCODING("VR128", ENCODING_REG)
1331 ENCODING("FR64", ENCODING_REG)
1332 ENCODING("FR32", ENCODING_REG)
1333 ENCODING("VR64", ENCODING_REG)
1334 ENCODING("SEGMENT_REG", ENCODING_REG)
1335 ENCODING("DEBUG_REG", ENCODING_REG)
1336 ENCODING("CONTROL_REG", ENCODING_REG)
1337 ENCODING("VR256", ENCODING_REG)
1338 ENCODING("VR256X", ENCODING_REG)
1339 ENCODING("VR128X", ENCODING_REG)
1340 ENCODING("FR64X", ENCODING_REG)
1341 ENCODING("FR32X", ENCODING_REG)
1342 ENCODING("VR512", ENCODING_REG)
1343 ENCODING("VK1", ENCODING_REG)
1344 ENCODING("VK8", ENCODING_REG)
1345 ENCODING("VK16", ENCODING_REG)
1346 ENCODING("VK1WM", ENCODING_REG)
1347 ENCODING("VK8WM", ENCODING_REG)
1348 ENCODING("VK16WM", ENCODING_REG)
1349 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1350 llvm_unreachable("Unhandled reg/opcode register encoding");
1353 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1354 (const std::string &s,
1355 bool hasOpSizePrefix) {
1356 ENCODING("GR32", ENCODING_VVVV)
1357 ENCODING("GR64", ENCODING_VVVV)
1358 ENCODING("FR32", ENCODING_VVVV)
1359 ENCODING("FR64", ENCODING_VVVV)
1360 ENCODING("VR128", ENCODING_VVVV)
1361 ENCODING("VR256", ENCODING_VVVV)
1362 ENCODING("FR32X", ENCODING_VVVV)
1363 ENCODING("FR64X", ENCODING_VVVV)
1364 ENCODING("VR128X", ENCODING_VVVV)
1365 ENCODING("VR256X", ENCODING_VVVV)
1366 ENCODING("VR512", ENCODING_VVVV)
1367 ENCODING("VK1", ENCODING_VVVV)
1368 ENCODING("VK8", ENCODING_VVVV)
1369 ENCODING("VK16", ENCODING_VVVV)
1370 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1371 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1374 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1375 (const std::string &s,
1376 bool hasOpSizePrefix) {
1377 ENCODING("VK1WM", ENCODING_WRITEMASK)
1378 ENCODING("VK8WM", ENCODING_WRITEMASK)
1379 ENCODING("VK16WM", ENCODING_WRITEMASK)
1380 errs() << "Unhandled mask register encoding " << s << "\n";
1381 llvm_unreachable("Unhandled mask register encoding");
1384 OperandEncoding RecognizableInstr::memoryEncodingFromString
1385 (const std::string &s,
1386 bool hasOpSizePrefix) {
1387 ENCODING("i16mem", ENCODING_RM)
1388 ENCODING("i32mem", ENCODING_RM)
1389 ENCODING("i64mem", ENCODING_RM)
1390 ENCODING("i8mem", ENCODING_RM)
1391 ENCODING("ssmem", ENCODING_RM)
1392 ENCODING("sdmem", ENCODING_RM)
1393 ENCODING("f128mem", ENCODING_RM)
1394 ENCODING("f256mem", ENCODING_RM)
1395 ENCODING("f512mem", ENCODING_RM)
1396 ENCODING("f64mem", ENCODING_RM)
1397 ENCODING("f32mem", ENCODING_RM)
1398 ENCODING("i128mem", ENCODING_RM)
1399 ENCODING("i256mem", ENCODING_RM)
1400 ENCODING("i512mem", ENCODING_RM)
1401 ENCODING("f80mem", ENCODING_RM)
1402 ENCODING("lea32mem", ENCODING_RM)
1403 ENCODING("lea64_32mem", ENCODING_RM)
1404 ENCODING("lea64mem", ENCODING_RM)
1405 ENCODING("opaque32mem", ENCODING_RM)
1406 ENCODING("opaque48mem", ENCODING_RM)
1407 ENCODING("opaque80mem", ENCODING_RM)
1408 ENCODING("opaque512mem", ENCODING_RM)
1409 ENCODING("vx32mem", ENCODING_RM)
1410 ENCODING("vy32mem", ENCODING_RM)
1411 ENCODING("vz32mem", ENCODING_RM)
1412 ENCODING("vx64mem", ENCODING_RM)
1413 ENCODING("vy64mem", ENCODING_RM)
1414 ENCODING("vy64xmem", ENCODING_RM)
1415 ENCODING("vz64mem", ENCODING_RM)
1416 errs() << "Unhandled memory encoding " << s << "\n";
1417 llvm_unreachable("Unhandled memory encoding");
1420 OperandEncoding RecognizableInstr::relocationEncodingFromString
1421 (const std::string &s,
1422 bool hasOpSizePrefix) {
1423 if(!hasOpSizePrefix) {
1424 // For instructions without an OpSize prefix, a declared 16-bit register or
1425 // immediate encoding is special.
1426 ENCODING("i16imm", ENCODING_IW)
1428 ENCODING("i16imm", ENCODING_Iv)
1429 ENCODING("i16i8imm", ENCODING_IB)
1430 ENCODING("i32imm", ENCODING_Iv)
1431 ENCODING("i32i8imm", ENCODING_IB)
1432 ENCODING("i64i32imm", ENCODING_ID)
1433 ENCODING("i64i8imm", ENCODING_IB)
1434 ENCODING("i8imm", ENCODING_IB)
1435 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1436 ENCODING("i16imm_pcrel", ENCODING_IW)
1437 ENCODING("i32imm_pcrel", ENCODING_ID)
1438 ENCODING("brtarget", ENCODING_Iv)
1439 ENCODING("brtarget8", ENCODING_IB)
1440 ENCODING("i64imm", ENCODING_IO)
1441 ENCODING("offset8", ENCODING_Ia)
1442 ENCODING("offset16", ENCODING_Ia)
1443 ENCODING("offset32", ENCODING_Ia)
1444 ENCODING("offset64", ENCODING_Ia)
1445 errs() << "Unhandled relocation encoding " << s << "\n";
1446 llvm_unreachable("Unhandled relocation encoding");
1449 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1450 (const std::string &s,
1451 bool hasOpSizePrefix) {
1452 ENCODING("GR32", ENCODING_Rv)
1453 ENCODING("GR64", ENCODING_RO)
1454 ENCODING("GR16", ENCODING_Rv)
1455 ENCODING("GR8", ENCODING_RB)
1456 ENCODING("GR16_NOAX", ENCODING_Rv)
1457 ENCODING("GR32_NOAX", ENCODING_Rv)
1458 ENCODING("GR64_NOAX", ENCODING_RO)
1459 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1460 llvm_unreachable("Unhandled opcode modifier encoding");