1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
39 // A clone of X86 since we can't depend on something that is generated.
49 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
50 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
51 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
52 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
55 #define MAP(from, to) MRM_##from = to,
64 D8 = 3, D9 = 4, DA = 5, DB = 6,
65 DC = 7, DD = 8, DE = 9, DF = 10,
68 P_0F_AE = 16, P_0F_01 = 17
72 // If rows are added to the opcode extension tables, then corresponding entries
73 // must be added here.
75 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
76 // that byte to ONE_BYTE_EXTENSION_TABLES.
78 // If the row corresponds to two bytes where the first is 0f, add an entry for
79 // the second byte to TWO_BYTE_EXTENSION_TABLES.
81 // If the row corresponds to some other set of bytes, you will need to modify
82 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
83 // to the X86 TD files, except in two cases: if the first two bytes of such a
84 // new combination are 0f 38 or 0f 3a, you just have to add maps called
85 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
86 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
87 // in RecognizableInstr::emitDecodePath().
89 #define ONE_BYTE_EXTENSION_TABLES \
100 EXTENSION_TABLE(d1) \
101 EXTENSION_TABLE(d2) \
102 EXTENSION_TABLE(d3) \
103 EXTENSION_TABLE(f6) \
104 EXTENSION_TABLE(f7) \
105 EXTENSION_TABLE(fe) \
108 #define TWO_BYTE_EXTENSION_TABLES \
109 EXTENSION_TABLE(00) \
110 EXTENSION_TABLE(01) \
111 EXTENSION_TABLE(18) \
112 EXTENSION_TABLE(71) \
113 EXTENSION_TABLE(72) \
114 EXTENSION_TABLE(73) \
115 EXTENSION_TABLE(ae) \
116 EXTENSION_TABLE(b9) \
117 EXTENSION_TABLE(ba) \
120 using namespace X86Disassembler;
122 /// needsModRMForDecode - Indicates whether a particular instruction requires a
123 /// ModR/M byte for the instruction to be properly decoded. For example, a
124 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
127 /// @param form - The form of the instruction.
128 /// @return - true if the form implies that a ModR/M byte is required, false
130 static bool needsModRMForDecode(uint8_t form) {
131 if (form == X86Local::MRMDestReg ||
132 form == X86Local::MRMDestMem ||
133 form == X86Local::MRMSrcReg ||
134 form == X86Local::MRMSrcMem ||
135 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
136 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
142 /// isRegFormat - Indicates whether a particular form requires the Mod field of
143 /// the ModR/M byte to be 0b11.
145 /// @param form - The form of the instruction.
146 /// @return - true if the form implies that Mod must be 0b11, false
148 static bool isRegFormat(uint8_t form) {
149 if (form == X86Local::MRMDestReg ||
150 form == X86Local::MRMSrcReg ||
151 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
157 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
158 /// Useful for switch statements and the like.
160 /// @param init - A reference to the BitsInit to be decoded.
161 /// @return - The field, with the first bit in the BitsInit as the lowest
163 static uint8_t byteFromBitsInit(BitsInit &init) {
164 int width = init.getNumBits();
166 assert(width <= 8 && "Field is too large for uint8_t!");
173 for (index = 0; index < width; index++) {
174 if (static_cast<BitInit*>(init.getBit(index))->getValue())
183 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
184 /// name of the field.
186 /// @param rec - The record from which to extract the value.
187 /// @param name - The name of the field in the record.
188 /// @return - The field, as translated by byteFromBitsInit().
189 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
190 BitsInit* bits = rec->getValueAsBitsInit(name);
191 return byteFromBitsInit(*bits);
194 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
195 const CodeGenInstruction &insn,
200 Name = Rec->getName();
201 Spec = &tables.specForUID(UID);
203 if (!Rec->isSubClassOf("X86Inst")) {
204 ShouldBeEmitted = false;
208 Prefix = byteFromRec(Rec, "Prefix");
209 Opcode = byteFromRec(Rec, "Opcode");
210 Form = byteFromRec(Rec, "FormBits");
211 SegOvr = byteFromRec(Rec, "SegOvrBits");
213 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
214 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
215 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
216 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
218 Name = Rec->getName();
219 AsmString = Rec->getValueAsString("AsmString");
221 Operands = &insn.OperandList;
223 IsSSE = HasOpSizePrefix && (Name.find("16") == Name.npos);
224 HasFROperands = false;
226 ShouldBeEmitted = true;
229 void RecognizableInstr::processInstr(DisassemblerTables &tables,
230 const CodeGenInstruction &insn,
233 RecognizableInstr recogInstr(tables, insn, uid);
235 recogInstr.emitInstructionSpecifier(tables);
237 if (recogInstr.shouldBeEmitted())
238 recogInstr.emitDecodePath(tables);
241 InstructionContext RecognizableInstr::insnContext() const {
242 InstructionContext insnContext;
244 if (Name.find("64") != Name.npos || HasREX_WPrefix) {
245 if (HasREX_WPrefix && HasOpSizePrefix)
246 insnContext = IC_64BIT_REXW_OPSIZE;
247 else if (HasOpSizePrefix)
248 insnContext = IC_64BIT_OPSIZE;
249 else if (HasREX_WPrefix && Prefix == X86Local::XS)
250 insnContext = IC_64BIT_REXW_XS;
251 else if (HasREX_WPrefix && Prefix == X86Local::XD)
252 insnContext = IC_64BIT_REXW_XD;
253 else if (Prefix == X86Local::XD)
254 insnContext = IC_64BIT_XD;
255 else if (Prefix == X86Local::XS)
256 insnContext = IC_64BIT_XS;
257 else if (HasREX_WPrefix)
258 insnContext = IC_64BIT_REXW;
260 insnContext = IC_64BIT;
263 insnContext = IC_OPSIZE;
264 else if (Prefix == X86Local::XD)
266 else if (Prefix == X86Local::XS)
275 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
276 // Filter out intrinsics
278 if (!Rec->isSubClassOf("X86Inst"))
279 return FILTER_STRONG;
281 if (Form == X86Local::Pseudo ||
283 return FILTER_STRONG;
285 if (Form == X86Local::MRMInitReg)
286 return FILTER_STRONG;
289 // Filter out instructions with a LOCK prefix;
290 // prefer forms that do not have the prefix
294 // Filter out artificial instructions
296 if (Name.find("TAILJMP") != Name.npos ||
297 Name.find("_Int") != Name.npos ||
298 Name.find("_int") != Name.npos ||
299 Name.find("Int_") != Name.npos ||
300 Name.find("_NOREX") != Name.npos ||
301 Name.find("_TC") != Name.npos ||
302 Name.find("EH_RETURN") != Name.npos ||
303 Name.find("V_SET") != Name.npos ||
304 Name.find("LOCK_") != Name.npos ||
305 Name.find("WIN") != Name.npos)
306 return FILTER_STRONG;
310 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
312 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
315 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
317 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
319 if (Name.find("Fs") != Name.npos)
321 if (Name == "MOVLPDrr" ||
322 Name == "MOVLPSrr" ||
328 Name == "MOVSX16rm8" ||
329 Name == "MOVSX16rr8" ||
330 Name == "MOVZX16rm8" ||
331 Name == "MOVZX16rr8" ||
332 Name == "PUSH32i16" ||
333 Name == "PUSH64i16" ||
334 Name == "MOVPQI2QImr" ||
339 Name == "MMX_MOVD64rrv164" ||
340 Name == "CRC32m16" ||
341 Name == "MOV64ri64i32" ||
345 // Filter out instructions with segment override prefixes.
346 // They're too messy to handle now and we'll special case them if needed.
349 return FILTER_STRONG;
351 // Filter out instructions that can't be printed.
353 if (AsmString.size() == 0)
354 return FILTER_STRONG;
356 // Filter out instructions with subreg operands.
358 if (AsmString.find("subreg") != AsmString.npos)
359 return FILTER_STRONG;
361 if (HasFROperands && Name.find("MOV") != Name.npos &&
362 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
363 (Name.find("to") != Name.npos)))
366 return FILTER_NORMAL;
369 void RecognizableInstr::handleOperand(
371 unsigned &operandIndex,
372 unsigned &physicalOperandIndex,
373 unsigned &numPhysicalOperands,
374 unsigned *operandMapping,
375 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
377 if (physicalOperandIndex >= numPhysicalOperands)
380 assert(physicalOperandIndex < numPhysicalOperands);
383 while (operandMapping[operandIndex] != operandIndex) {
384 Spec->operands[operandIndex].encoding = ENCODING_DUP;
385 Spec->operands[operandIndex].type =
386 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
390 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
392 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
394 Spec->operands[operandIndex].type = typeFromString(typeName,
400 ++physicalOperandIndex;
403 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
406 if (!Rec->isSubClassOf("X86Inst"))
411 Spec->filtered = true;
414 ShouldBeEmitted = false;
420 Spec->insnContext = insnContext();
422 const std::vector<CodeGenInstruction::OperandInfo> &OperandList = *Operands;
424 unsigned operandIndex;
425 unsigned numOperands = OperandList.size();
426 unsigned numPhysicalOperands = 0;
428 // operandMapping maps from operands in OperandList to their originals.
429 // If operandMapping[i] != i, then the entry is a duplicate.
430 unsigned operandMapping[X86_MAX_OPERANDS];
432 bool hasFROperands = false;
434 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
436 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
437 if (OperandList[operandIndex].Constraints.size()) {
438 const CodeGenInstruction::ConstraintInfo &Constraint =
439 OperandList[operandIndex].Constraints[0];
440 if (Constraint.isTied()) {
441 operandMapping[operandIndex] = Constraint.getTiedOperand();
443 ++numPhysicalOperands;
444 operandMapping[operandIndex] = operandIndex;
447 ++numPhysicalOperands;
448 operandMapping[operandIndex] = operandIndex;
451 const std::string &recName = OperandList[operandIndex].Rec->getName();
453 if (recName.find("FR") != recName.npos)
454 hasFROperands = true;
457 if (hasFROperands && Name.find("MOV") != Name.npos &&
458 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
459 (Name.find("to") != Name.npos)))
460 ShouldBeEmitted = false;
462 if (!ShouldBeEmitted)
465 #define HANDLE_OPERAND(class) \
466 handleOperand(false, \
468 physicalOperandIndex, \
469 numPhysicalOperands, \
471 class##EncodingFromString);
473 #define HANDLE_OPTIONAL(class) \
474 handleOperand(true, \
476 physicalOperandIndex, \
477 numPhysicalOperands, \
479 class##EncodingFromString);
481 // operandIndex should always be < numOperands
483 // physicalOperandIndex should always be < numPhysicalOperands
484 unsigned physicalOperandIndex = 0;
487 case X86Local::RawFrm:
488 // Operand 1 (optional) is an address or immediate.
489 // Operand 2 (optional) is an immediate.
490 assert(numPhysicalOperands <= 2 &&
491 "Unexpected number of operands for RawFrm");
492 HANDLE_OPTIONAL(relocation)
493 HANDLE_OPTIONAL(immediate)
495 case X86Local::AddRegFrm:
496 // Operand 1 is added to the opcode.
497 // Operand 2 (optional) is an address.
498 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
499 "Unexpected number of operands for AddRegFrm");
500 HANDLE_OPERAND(opcodeModifier)
501 HANDLE_OPTIONAL(relocation)
503 case X86Local::MRMDestReg:
504 // Operand 1 is a register operand in the R/M field.
505 // Operand 2 is a register operand in the Reg/Opcode field.
506 // Operand 3 (optional) is an immediate.
507 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
508 "Unexpected number of operands for MRMDestRegFrm");
509 HANDLE_OPERAND(rmRegister)
510 HANDLE_OPERAND(roRegister)
511 HANDLE_OPTIONAL(immediate)
513 case X86Local::MRMDestMem:
514 // Operand 1 is a memory operand (possibly SIB-extended)
515 // Operand 2 is a register operand in the Reg/Opcode field.
516 // Operand 3 (optional) is an immediate.
517 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
518 "Unexpected number of operands for MRMDestMemFrm");
519 HANDLE_OPERAND(memory)
520 HANDLE_OPERAND(roRegister)
521 HANDLE_OPTIONAL(immediate)
523 case X86Local::MRMSrcReg:
524 // Operand 1 is a register operand in the Reg/Opcode field.
525 // Operand 2 is a register operand in the R/M field.
526 // Operand 3 (optional) is an immediate.
527 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
528 "Unexpected number of operands for MRMSrcRegFrm");
529 HANDLE_OPERAND(roRegister)
530 HANDLE_OPERAND(rmRegister)
531 HANDLE_OPTIONAL(immediate)
533 case X86Local::MRMSrcMem:
534 // Operand 1 is a register operand in the Reg/Opcode field.
535 // Operand 2 is a memory operand (possibly SIB-extended)
536 // Operand 3 (optional) is an immediate.
537 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
538 "Unexpected number of operands for MRMSrcMemFrm");
539 HANDLE_OPERAND(roRegister)
540 HANDLE_OPERAND(memory)
541 HANDLE_OPTIONAL(immediate)
543 case X86Local::MRM0r:
544 case X86Local::MRM1r:
545 case X86Local::MRM2r:
546 case X86Local::MRM3r:
547 case X86Local::MRM4r:
548 case X86Local::MRM5r:
549 case X86Local::MRM6r:
550 case X86Local::MRM7r:
551 // Operand 1 is a register operand in the R/M field.
552 // Operand 2 (optional) is an immediate or relocation.
553 assert(numPhysicalOperands <= 2 &&
554 "Unexpected number of operands for MRMnRFrm");
555 HANDLE_OPTIONAL(rmRegister)
556 HANDLE_OPTIONAL(relocation)
558 case X86Local::MRM0m:
559 case X86Local::MRM1m:
560 case X86Local::MRM2m:
561 case X86Local::MRM3m:
562 case X86Local::MRM4m:
563 case X86Local::MRM5m:
564 case X86Local::MRM6m:
565 case X86Local::MRM7m:
566 // Operand 1 is a memory operand (possibly SIB-extended)
567 // Operand 2 (optional) is an immediate or relocation.
568 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
569 "Unexpected number of operands for MRMnMFrm");
570 HANDLE_OPERAND(memory)
571 HANDLE_OPTIONAL(relocation)
573 case X86Local::MRMInitReg:
578 #undef HANDLE_OPERAND
579 #undef HANDLE_OPTIONAL
582 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
583 // Special cases where the LLVM tables are not complete
585 #define MAP(from, to) \
586 case X86Local::MRM_##from: \
587 filter = new ExactFilter(0x##from); \
590 OpcodeType opcodeType = (OpcodeType)-1;
592 ModRMFilter* filter = NULL;
593 uint8_t opcodeToSet = 0;
596 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
600 opcodeType = TWOBYTE;
604 if (needsModRMForDecode(Form))
605 filter = new ModFilter(isRegFormat(Form));
607 filter = new DumbFilter();
609 #define EXTENSION_TABLE(n) case 0x##n:
610 TWO_BYTE_EXTENSION_TABLES
611 #undef EXTENSION_TABLE
614 llvm_unreachable("Unhandled two-byte extended opcode");
615 case X86Local::MRM0r:
616 case X86Local::MRM1r:
617 case X86Local::MRM2r:
618 case X86Local::MRM3r:
619 case X86Local::MRM4r:
620 case X86Local::MRM5r:
621 case X86Local::MRM6r:
622 case X86Local::MRM7r:
623 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
625 case X86Local::MRM0m:
626 case X86Local::MRM1m:
627 case X86Local::MRM2m:
628 case X86Local::MRM3m:
629 case X86Local::MRM4m:
630 case X86Local::MRM5m:
631 case X86Local::MRM6m:
632 case X86Local::MRM7m:
633 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
639 opcodeToSet = Opcode;
642 opcodeType = THREEBYTE_38;
643 if (needsModRMForDecode(Form))
644 filter = new ModFilter(isRegFormat(Form));
646 filter = new DumbFilter();
647 opcodeToSet = Opcode;
650 opcodeType = THREEBYTE_3A;
651 if (needsModRMForDecode(Form))
652 filter = new ModFilter(isRegFormat(Form));
654 filter = new DumbFilter();
655 opcodeToSet = Opcode;
665 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
666 opcodeType = ONEBYTE;
667 if (Form == X86Local::AddRegFrm) {
668 Spec->modifierType = MODIFIER_MODRM;
669 Spec->modifierBase = Opcode;
670 filter = new AddRegEscapeFilter(Opcode);
672 filter = new EscapeFilter(true, Opcode);
674 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
677 opcodeType = ONEBYTE;
679 #define EXTENSION_TABLE(n) case 0x##n:
680 ONE_BYTE_EXTENSION_TABLES
681 #undef EXTENSION_TABLE
684 llvm_unreachable("Fell through the cracks of a single-byte "
686 case X86Local::MRM0r:
687 case X86Local::MRM1r:
688 case X86Local::MRM2r:
689 case X86Local::MRM3r:
690 case X86Local::MRM4r:
691 case X86Local::MRM5r:
692 case X86Local::MRM6r:
693 case X86Local::MRM7r:
694 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
696 case X86Local::MRM0m:
697 case X86Local::MRM1m:
698 case X86Local::MRM2m:
699 case X86Local::MRM3m:
700 case X86Local::MRM4m:
701 case X86Local::MRM5m:
702 case X86Local::MRM6m:
703 case X86Local::MRM7m:
704 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
717 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
720 if (needsModRMForDecode(Form))
721 filter = new ModFilter(isRegFormat(Form));
723 filter = new DumbFilter();
726 opcodeToSet = Opcode;
729 assert(opcodeType != (OpcodeType)-1 &&
730 "Opcode type not set");
731 assert(filter && "Filter not set");
733 if (Form == X86Local::AddRegFrm) {
734 if(Spec->modifierType != MODIFIER_MODRM) {
735 assert(opcodeToSet < 0xf9 &&
736 "Not enough room for all ADDREG_FRM operands");
738 uint8_t currentOpcode;
740 for (currentOpcode = opcodeToSet;
741 currentOpcode < opcodeToSet + 8;
743 tables.setTableFields(opcodeType,
749 Spec->modifierType = MODIFIER_OPCODE;
750 Spec->modifierBase = opcodeToSet;
752 // modifierBase was set where MODIFIER_MODRM was set
753 tables.setTableFields(opcodeType,
760 tables.setTableFields(opcodeType,
766 Spec->modifierType = MODIFIER_NONE;
767 Spec->modifierBase = opcodeToSet;
775 #define TYPE(str, type) if (s == str) return type;
776 OperandType RecognizableInstr::typeFromString(const std::string &s,
779 bool hasOpSizePrefix) {
781 // For SSE instructions, we ignore the OpSize prefix and force operand
783 TYPE("GR16", TYPE_R16)
784 TYPE("GR32", TYPE_R32)
785 TYPE("GR64", TYPE_R64)
788 // For instructions with a REX_W prefix, a declared 32-bit register encoding
790 TYPE("GR32", TYPE_R32)
792 if(!hasOpSizePrefix) {
793 // For instructions without an OpSize prefix, a declared 16-bit register or
794 // immediate encoding is special.
795 TYPE("GR16", TYPE_R16)
796 TYPE("i16imm", TYPE_IMM16)
798 TYPE("i16mem", TYPE_Mv)
799 TYPE("i16imm", TYPE_IMMv)
800 TYPE("i16i8imm", TYPE_IMMv)
801 TYPE("GR16", TYPE_Rv)
802 TYPE("i32mem", TYPE_Mv)
803 TYPE("i32imm", TYPE_IMMv)
804 TYPE("i32i8imm", TYPE_IMM32)
805 TYPE("GR32", TYPE_Rv)
806 TYPE("i64mem", TYPE_Mv)
807 TYPE("i64i32imm", TYPE_IMM64)
808 TYPE("i64i8imm", TYPE_IMM64)
809 TYPE("GR64", TYPE_R64)
810 TYPE("i8mem", TYPE_M8)
811 TYPE("i8imm", TYPE_IMM8)
813 TYPE("VR128", TYPE_XMM128)
814 TYPE("f128mem", TYPE_M128)
815 TYPE("FR64", TYPE_XMM64)
816 TYPE("f64mem", TYPE_M64FP)
817 TYPE("FR32", TYPE_XMM32)
818 TYPE("f32mem", TYPE_M32FP)
820 TYPE("i128mem", TYPE_M128)
821 TYPE("i64i32imm_pcrel", TYPE_REL64)
822 TYPE("i32imm_pcrel", TYPE_REL32)
823 TYPE("SSECC", TYPE_IMM3)
824 TYPE("brtarget", TYPE_RELv)
825 TYPE("brtarget8", TYPE_REL8)
826 TYPE("f80mem", TYPE_M80FP)
827 TYPE("lea32mem", TYPE_LEA)
828 TYPE("lea64_32mem", TYPE_LEA)
829 TYPE("lea64mem", TYPE_LEA)
830 TYPE("VR64", TYPE_MM64)
831 TYPE("i64imm", TYPE_IMMv)
832 TYPE("opaque32mem", TYPE_M1616)
833 TYPE("opaque48mem", TYPE_M1632)
834 TYPE("opaque80mem", TYPE_M1664)
835 TYPE("opaque512mem", TYPE_M512)
836 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
837 TYPE("DEBUG_REG", TYPE_DEBUGREG)
838 TYPE("CONTROL_REG", TYPE_CONTROLREG)
839 TYPE("offset8", TYPE_MOFFS8)
840 TYPE("offset16", TYPE_MOFFS16)
841 TYPE("offset32", TYPE_MOFFS32)
842 TYPE("offset64", TYPE_MOFFS64)
843 errs() << "Unhandled type string " << s << "\n";
844 llvm_unreachable("Unhandled type string");
848 #define ENCODING(str, encoding) if (s == str) return encoding;
849 OperandEncoding RecognizableInstr::immediateEncodingFromString
850 (const std::string &s,
851 bool hasOpSizePrefix) {
852 if(!hasOpSizePrefix) {
853 // For instructions without an OpSize prefix, a declared 16-bit register or
854 // immediate encoding is special.
855 ENCODING("i16imm", ENCODING_IW)
857 ENCODING("i32i8imm", ENCODING_IB)
858 ENCODING("SSECC", ENCODING_IB)
859 ENCODING("i16imm", ENCODING_Iv)
860 ENCODING("i16i8imm", ENCODING_IB)
861 ENCODING("i32imm", ENCODING_Iv)
862 ENCODING("i64i32imm", ENCODING_ID)
863 ENCODING("i64i8imm", ENCODING_IB)
864 ENCODING("i8imm", ENCODING_IB)
865 errs() << "Unhandled immediate encoding " << s << "\n";
866 llvm_unreachable("Unhandled immediate encoding");
869 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
870 (const std::string &s,
871 bool hasOpSizePrefix) {
872 ENCODING("GR16", ENCODING_RM)
873 ENCODING("GR32", ENCODING_RM)
874 ENCODING("GR64", ENCODING_RM)
875 ENCODING("GR8", ENCODING_RM)
876 ENCODING("VR128", ENCODING_RM)
877 ENCODING("FR64", ENCODING_RM)
878 ENCODING("FR32", ENCODING_RM)
879 ENCODING("VR64", ENCODING_RM)
880 errs() << "Unhandled R/M register encoding " << s << "\n";
881 llvm_unreachable("Unhandled R/M register encoding");
884 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
885 (const std::string &s,
886 bool hasOpSizePrefix) {
887 ENCODING("GR16", ENCODING_REG)
888 ENCODING("GR32", ENCODING_REG)
889 ENCODING("GR64", ENCODING_REG)
890 ENCODING("GR8", ENCODING_REG)
891 ENCODING("VR128", ENCODING_REG)
892 ENCODING("FR64", ENCODING_REG)
893 ENCODING("FR32", ENCODING_REG)
894 ENCODING("VR64", ENCODING_REG)
895 ENCODING("SEGMENT_REG", ENCODING_REG)
896 ENCODING("DEBUG_REG", ENCODING_REG)
897 ENCODING("CONTROL_REG", ENCODING_REG)
898 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
899 llvm_unreachable("Unhandled reg/opcode register encoding");
902 OperandEncoding RecognizableInstr::memoryEncodingFromString
903 (const std::string &s,
904 bool hasOpSizePrefix) {
905 ENCODING("i16mem", ENCODING_RM)
906 ENCODING("i32mem", ENCODING_RM)
907 ENCODING("i64mem", ENCODING_RM)
908 ENCODING("i8mem", ENCODING_RM)
909 ENCODING("f128mem", ENCODING_RM)
910 ENCODING("f64mem", ENCODING_RM)
911 ENCODING("f32mem", ENCODING_RM)
912 ENCODING("i128mem", ENCODING_RM)
913 ENCODING("f80mem", ENCODING_RM)
914 ENCODING("lea32mem", ENCODING_RM)
915 ENCODING("lea64_32mem", ENCODING_RM)
916 ENCODING("lea64mem", ENCODING_RM)
917 ENCODING("opaque32mem", ENCODING_RM)
918 ENCODING("opaque48mem", ENCODING_RM)
919 ENCODING("opaque80mem", ENCODING_RM)
920 ENCODING("opaque512mem", ENCODING_RM)
921 errs() << "Unhandled memory encoding " << s << "\n";
922 llvm_unreachable("Unhandled memory encoding");
925 OperandEncoding RecognizableInstr::relocationEncodingFromString
926 (const std::string &s,
927 bool hasOpSizePrefix) {
928 if(!hasOpSizePrefix) {
929 // For instructions without an OpSize prefix, a declared 16-bit register or
930 // immediate encoding is special.
931 ENCODING("i16imm", ENCODING_IW)
933 ENCODING("i16imm", ENCODING_Iv)
934 ENCODING("i16i8imm", ENCODING_IB)
935 ENCODING("i32imm", ENCODING_Iv)
936 ENCODING("i32i8imm", ENCODING_IB)
937 ENCODING("i64i32imm", ENCODING_ID)
938 ENCODING("i64i8imm", ENCODING_IB)
939 ENCODING("i8imm", ENCODING_IB)
940 ENCODING("i64i32imm_pcrel", ENCODING_ID)
941 ENCODING("i32imm_pcrel", ENCODING_ID)
942 ENCODING("brtarget", ENCODING_Iv)
943 ENCODING("brtarget8", ENCODING_IB)
944 ENCODING("i64imm", ENCODING_IO)
945 ENCODING("offset8", ENCODING_Ia)
946 ENCODING("offset16", ENCODING_Ia)
947 ENCODING("offset32", ENCODING_Ia)
948 ENCODING("offset64", ENCODING_Ia)
949 errs() << "Unhandled relocation encoding " << s << "\n";
950 llvm_unreachable("Unhandled relocation encoding");
953 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
954 (const std::string &s,
955 bool hasOpSizePrefix) {
956 ENCODING("RST", ENCODING_I)
957 ENCODING("GR32", ENCODING_Rv)
958 ENCODING("GR64", ENCODING_RO)
959 ENCODING("GR16", ENCODING_Rv)
960 ENCODING("GR8", ENCODING_RB)
961 errs() << "Unhandled opcode modifier encoding " << s << "\n";
962 llvm_unreachable("Unhandled opcode modifier encoding");