1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22, PD = 23, T8PD = 24, TAPD = 25
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
135 #define THREE_BYTE_38_EXTENSION_TABLES \
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
234 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
235 HasOpSize16Prefix = Rec->getValueAsBit("hasOpSize16Prefix");
236 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
237 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
238 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
239 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
240 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
242 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
243 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
244 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
245 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
247 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z");
248 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
249 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
250 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
251 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble");
253 Name = Rec->getName();
254 AsmString = Rec->getValueAsString("AsmString");
256 Operands = &insn.Operands.OperandList;
258 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
260 // Check for 64-bit inst which does not require REX
263 // FIXME: Is there some better way to check for In64BitMode?
264 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
265 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
266 if (Predicates[i]->getName().find("Not64Bit") != Name.npos ||
267 Predicates[i]->getName().find("In32Bit") != Name.npos) {
271 if (Predicates[i]->getName().find("In64Bit") != Name.npos) {
277 ShouldBeEmitted = true;
280 void RecognizableInstr::processInstr(DisassemblerTables &tables,
281 const CodeGenInstruction &insn,
284 // Ignore "asm parser only" instructions.
285 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
288 RecognizableInstr recogInstr(tables, insn, uid);
290 recogInstr.emitInstructionSpecifier();
292 if (recogInstr.shouldBeEmitted())
293 recogInstr.emitDecodePath(tables);
296 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \
297 (HasEVEX_K && HasEVEX_B ? n##_K_B : \
298 (HasEVEX_KZ ? n##_KZ : \
299 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))))
301 InstructionContext RecognizableInstr::insnContext() const {
302 InstructionContext insnContext;
305 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
306 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
307 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
310 if (HasVEX_LPrefix && HasVEX_WPrefix) {
311 if (HasOpSizePrefix || Prefix == X86Local::PD)
312 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
313 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
314 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
315 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
316 Prefix == X86Local::TAXD)
317 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
319 insnContext = EVEX_KB(IC_EVEX_L_W);
320 } else if (HasVEX_LPrefix) {
322 if (HasOpSizePrefix || Prefix == X86Local::PD ||
323 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
324 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
325 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
326 insnContext = EVEX_KB(IC_EVEX_L_XS);
327 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
328 Prefix == X86Local::TAXD)
329 insnContext = EVEX_KB(IC_EVEX_L_XD);
331 insnContext = EVEX_KB(IC_EVEX_L);
333 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
335 if (HasOpSizePrefix || Prefix == X86Local::PD ||
336 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
337 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
338 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
339 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
340 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
341 Prefix == X86Local::TAXD)
342 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
344 insnContext = EVEX_KB(IC_EVEX_L2_W);
345 } else if (HasEVEX_L2Prefix) {
347 if (HasOpSizePrefix || Prefix == X86Local::PD ||
348 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
349 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
350 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
351 Prefix == X86Local::TAXD)
352 insnContext = EVEX_KB(IC_EVEX_L2_XD);
353 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
354 insnContext = EVEX_KB(IC_EVEX_L2_XS);
356 insnContext = EVEX_KB(IC_EVEX_L2);
358 else if (HasVEX_WPrefix) {
360 if (HasOpSizePrefix || Prefix == X86Local::PD ||
361 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
362 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
363 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
364 insnContext = EVEX_KB(IC_EVEX_W_XS);
365 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
366 Prefix == X86Local::TAXD)
367 insnContext = EVEX_KB(IC_EVEX_W_XD);
369 insnContext = EVEX_KB(IC_EVEX_W);
372 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
373 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
374 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
375 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
376 Prefix == X86Local::TAXD)
377 insnContext = EVEX_KB(IC_EVEX_XD);
378 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
379 insnContext = EVEX_KB(IC_EVEX_XS);
381 insnContext = EVEX_KB(IC_EVEX);
383 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
384 if (HasVEX_LPrefix && HasVEX_WPrefix) {
385 if (HasOpSizePrefix || Prefix == X86Local::PD ||
386 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
387 insnContext = IC_VEX_L_W_OPSIZE;
388 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
389 insnContext = IC_VEX_L_W_XS;
390 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
391 Prefix == X86Local::TAXD)
392 insnContext = IC_VEX_L_W_XD;
394 insnContext = IC_VEX_L_W;
395 } else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
396 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
398 insnContext = IC_VEX_L_OPSIZE;
399 else if ((HasOpSizePrefix || Prefix == X86Local::PD ||
400 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) &&
402 insnContext = IC_VEX_W_OPSIZE;
403 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
404 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
405 insnContext = IC_VEX_OPSIZE;
406 else if (HasVEX_LPrefix &&
407 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
408 insnContext = IC_VEX_L_XS;
409 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
410 Prefix == X86Local::T8XD ||
411 Prefix == X86Local::TAXD))
412 insnContext = IC_VEX_L_XD;
413 else if (HasVEX_WPrefix &&
414 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
415 insnContext = IC_VEX_W_XS;
416 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
417 Prefix == X86Local::T8XD ||
418 Prefix == X86Local::TAXD))
419 insnContext = IC_VEX_W_XD;
420 else if (HasVEX_WPrefix)
421 insnContext = IC_VEX_W;
422 else if (HasVEX_LPrefix)
423 insnContext = IC_VEX_L;
424 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
425 Prefix == X86Local::TAXD)
426 insnContext = IC_VEX_XD;
427 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
428 insnContext = IC_VEX_XS;
430 insnContext = IC_VEX;
431 } else if (Is64Bit || HasREX_WPrefix) {
432 if (HasREX_WPrefix && (HasOpSizePrefix || Prefix == X86Local::PD ||
433 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD))
434 insnContext = IC_64BIT_REXW_OPSIZE;
435 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
436 Prefix == X86Local::T8XD ||
437 Prefix == X86Local::TAXD))
438 insnContext = IC_64BIT_XD_OPSIZE;
439 else if (HasOpSizePrefix &&
440 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
441 insnContext = IC_64BIT_XS_OPSIZE;
442 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
443 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
444 insnContext = IC_64BIT_OPSIZE;
445 else if (HasAdSizePrefix)
446 insnContext = IC_64BIT_ADSIZE;
447 else if (HasREX_WPrefix &&
448 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
449 insnContext = IC_64BIT_REXW_XS;
450 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
451 Prefix == X86Local::T8XD ||
452 Prefix == X86Local::TAXD))
453 insnContext = IC_64BIT_REXW_XD;
454 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
455 Prefix == X86Local::TAXD)
456 insnContext = IC_64BIT_XD;
457 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
458 insnContext = IC_64BIT_XS;
459 else if (HasREX_WPrefix)
460 insnContext = IC_64BIT_REXW;
462 insnContext = IC_64BIT;
464 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
465 Prefix == X86Local::T8XD ||
466 Prefix == X86Local::TAXD))
467 insnContext = IC_XD_OPSIZE;
468 else if (HasOpSizePrefix &&
469 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
470 insnContext = IC_XS_OPSIZE;
471 else if (HasOpSizePrefix && HasAdSizePrefix)
472 insnContext = IC_OPSIZE_ADSIZE;
473 else if (HasOpSizePrefix || Prefix == X86Local::PD ||
474 Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)
475 insnContext = IC_OPSIZE;
476 else if (HasAdSizePrefix)
477 insnContext = IC_ADSIZE;
478 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
479 Prefix == X86Local::TAXD)
481 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
482 Prefix == X86Local::REP)
491 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
496 // Filter out intrinsics
498 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
500 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble))
501 return FILTER_STRONG;
504 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
505 // printed as a separate "instruction".
513 // Filter out instructions with a LOCK prefix;
514 // prefer forms that do not have the prefix
520 if (Name == "VMASKMOVDQU64")
523 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
524 // For now, just prefer the REP versions.
525 if (Name == "XACQUIRE_PREFIX" ||
526 Name == "XRELEASE_PREFIX")
529 return FILTER_NORMAL;
532 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
533 unsigned &physicalOperandIndex,
534 unsigned &numPhysicalOperands,
535 const unsigned *operandMapping,
536 OperandEncoding (*encodingFromString)
538 bool hasOpSizePrefix)) {
540 if (physicalOperandIndex >= numPhysicalOperands)
543 assert(physicalOperandIndex < numPhysicalOperands);
546 while (operandMapping[operandIndex] != operandIndex) {
547 Spec->operands[operandIndex].encoding = ENCODING_DUP;
548 Spec->operands[operandIndex].type =
549 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
553 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
555 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
557 Spec->operands[operandIndex].type = typeFromString(typeName,
563 ++physicalOperandIndex;
566 void RecognizableInstr::emitInstructionSpecifier() {
569 if (!ShouldBeEmitted)
574 Spec->filtered = true;
577 ShouldBeEmitted = false;
583 Spec->insnContext = insnContext();
585 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
587 unsigned numOperands = OperandList.size();
588 unsigned numPhysicalOperands = 0;
590 // operandMapping maps from operands in OperandList to their originals.
591 // If operandMapping[i] != i, then the entry is a duplicate.
592 unsigned operandMapping[X86_MAX_OPERANDS];
593 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
595 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
596 if (OperandList[operandIndex].Constraints.size()) {
597 const CGIOperandList::ConstraintInfo &Constraint =
598 OperandList[operandIndex].Constraints[0];
599 if (Constraint.isTied()) {
600 operandMapping[operandIndex] = operandIndex;
601 operandMapping[Constraint.getTiedOperand()] = operandIndex;
603 ++numPhysicalOperands;
604 operandMapping[operandIndex] = operandIndex;
607 ++numPhysicalOperands;
608 operandMapping[operandIndex] = operandIndex;
612 #define HANDLE_OPERAND(class) \
613 handleOperand(false, \
615 physicalOperandIndex, \
616 numPhysicalOperands, \
618 class##EncodingFromString);
620 #define HANDLE_OPTIONAL(class) \
621 handleOperand(true, \
623 physicalOperandIndex, \
624 numPhysicalOperands, \
626 class##EncodingFromString);
628 // operandIndex should always be < numOperands
629 unsigned operandIndex = 0;
630 // physicalOperandIndex should always be < numPhysicalOperands
631 unsigned physicalOperandIndex = 0;
634 case X86Local::RawFrm:
635 // Operand 1 (optional) is an address or immediate.
636 // Operand 2 (optional) is an immediate.
637 assert(numPhysicalOperands <= 2 &&
638 "Unexpected number of operands for RawFrm");
639 HANDLE_OPTIONAL(relocation)
640 HANDLE_OPTIONAL(immediate)
642 case X86Local::AddRegFrm:
643 // Operand 1 is added to the opcode.
644 // Operand 2 (optional) is an address.
645 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
646 "Unexpected number of operands for AddRegFrm");
647 HANDLE_OPERAND(opcodeModifier)
648 HANDLE_OPTIONAL(relocation)
650 case X86Local::MRMDestReg:
651 // Operand 1 is a register operand in the R/M field.
652 // Operand 2 is a register operand in the Reg/Opcode field.
653 // - In AVX, there is a register operand in the VEX.vvvv field here -
654 // Operand 3 (optional) is an immediate.
656 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
657 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
659 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
660 "Unexpected number of operands for MRMDestRegFrm");
662 HANDLE_OPERAND(rmRegister)
665 // FIXME: In AVX, the register below becomes the one encoded
666 // in ModRMVEX and the one above the one in the VEX.VVVV field
667 HANDLE_OPERAND(vvvvRegister)
669 HANDLE_OPERAND(roRegister)
670 HANDLE_OPTIONAL(immediate)
672 case X86Local::MRMDestMem:
673 // Operand 1 is a memory operand (possibly SIB-extended)
674 // Operand 2 is a register operand in the Reg/Opcode field.
675 // - In AVX, there is a register operand in the VEX.vvvv field here -
676 // Operand 3 (optional) is an immediate.
678 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
679 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
681 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
682 "Unexpected number of operands for MRMDestMemFrm");
683 HANDLE_OPERAND(memory)
686 HANDLE_OPERAND(writemaskRegister)
689 // FIXME: In AVX, the register below becomes the one encoded
690 // in ModRMVEX and the one above the one in the VEX.VVVV field
691 HANDLE_OPERAND(vvvvRegister)
693 HANDLE_OPERAND(roRegister)
694 HANDLE_OPTIONAL(immediate)
696 case X86Local::MRMSrcReg:
697 // Operand 1 is a register operand in the Reg/Opcode field.
698 // Operand 2 is a register operand in the R/M field.
699 // - In AVX, there is a register operand in the VEX.vvvv field here -
700 // Operand 3 (optional) is an immediate.
701 // Operand 4 (optional) is an immediate.
703 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
704 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
705 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
707 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
708 "Unexpected number of operands for MRMSrcRegFrm");
710 HANDLE_OPERAND(roRegister)
713 HANDLE_OPERAND(writemaskRegister)
716 // FIXME: In AVX, the register below becomes the one encoded
717 // in ModRMVEX and the one above the one in the VEX.VVVV field
718 HANDLE_OPERAND(vvvvRegister)
721 HANDLE_OPERAND(immediate)
723 HANDLE_OPERAND(rmRegister)
725 if (HasVEX_4VOp3Prefix)
726 HANDLE_OPERAND(vvvvRegister)
728 if (!HasMemOp4Prefix)
729 HANDLE_OPTIONAL(immediate)
730 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
731 HANDLE_OPTIONAL(immediate)
733 case X86Local::MRMSrcMem:
734 // Operand 1 is a register operand in the Reg/Opcode field.
735 // Operand 2 is a memory operand (possibly SIB-extended)
736 // - In AVX, there is a register operand in the VEX.vvvv field here -
737 // Operand 3 (optional) is an immediate.
739 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
740 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
741 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
743 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
744 "Unexpected number of operands for MRMSrcMemFrm");
746 HANDLE_OPERAND(roRegister)
749 HANDLE_OPERAND(writemaskRegister)
752 // FIXME: In AVX, the register below becomes the one encoded
753 // in ModRMVEX and the one above the one in the VEX.VVVV field
754 HANDLE_OPERAND(vvvvRegister)
757 HANDLE_OPERAND(immediate)
759 HANDLE_OPERAND(memory)
761 if (HasVEX_4VOp3Prefix)
762 HANDLE_OPERAND(vvvvRegister)
764 if (!HasMemOp4Prefix)
765 HANDLE_OPTIONAL(immediate)
766 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
768 case X86Local::MRM0r:
769 case X86Local::MRM1r:
770 case X86Local::MRM2r:
771 case X86Local::MRM3r:
772 case X86Local::MRM4r:
773 case X86Local::MRM5r:
774 case X86Local::MRM6r:
775 case X86Local::MRM7r:
777 // Operand 1 is a register operand in the R/M field.
778 // Operand 2 (optional) is an immediate or relocation.
779 // Operand 3 (optional) is an immediate.
780 unsigned kOp = (HasEVEX_K) ? 1:0;
781 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
782 if (numPhysicalOperands > 3 + kOp + Op4v)
783 llvm_unreachable("Unexpected number of operands for MRMnr");
786 HANDLE_OPERAND(vvvvRegister)
789 HANDLE_OPERAND(writemaskRegister)
790 HANDLE_OPTIONAL(rmRegister)
791 HANDLE_OPTIONAL(relocation)
792 HANDLE_OPTIONAL(immediate)
794 case X86Local::MRM0m:
795 case X86Local::MRM1m:
796 case X86Local::MRM2m:
797 case X86Local::MRM3m:
798 case X86Local::MRM4m:
799 case X86Local::MRM5m:
800 case X86Local::MRM6m:
801 case X86Local::MRM7m:
803 // Operand 1 is a memory operand (possibly SIB-extended)
804 // Operand 2 (optional) is an immediate or relocation.
805 unsigned kOp = (HasEVEX_K) ? 1:0;
806 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
807 if (numPhysicalOperands < 1 + kOp + Op4v ||
808 numPhysicalOperands > 2 + kOp + Op4v)
809 llvm_unreachable("Unexpected number of operands for MRMnm");
812 HANDLE_OPERAND(vvvvRegister)
814 HANDLE_OPERAND(writemaskRegister)
815 HANDLE_OPERAND(memory)
816 HANDLE_OPTIONAL(relocation)
818 case X86Local::RawFrmImm8:
819 // operand 1 is a 16-bit immediate
820 // operand 2 is an 8-bit immediate
821 assert(numPhysicalOperands == 2 &&
822 "Unexpected number of operands for X86Local::RawFrmImm8");
823 HANDLE_OPERAND(immediate)
824 HANDLE_OPERAND(immediate)
826 case X86Local::RawFrmImm16:
827 // operand 1 is a 16-bit immediate
828 // operand 2 is a 16-bit immediate
829 HANDLE_OPERAND(immediate)
830 HANDLE_OPERAND(immediate)
832 case X86Local::MRM_F8:
833 if (Opcode == 0xc6) {
834 assert(numPhysicalOperands == 1 &&
835 "Unexpected number of operands for X86Local::MRM_F8");
836 HANDLE_OPERAND(immediate)
837 } else if (Opcode == 0xc7) {
838 assert(numPhysicalOperands == 1 &&
839 "Unexpected number of operands for X86Local::MRM_F8");
840 HANDLE_OPERAND(relocation)
843 case X86Local::MRMInitReg:
848 #undef HANDLE_OPERAND
849 #undef HANDLE_OPTIONAL
852 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
853 // Special cases where the LLVM tables are not complete
855 #define MAP(from, to) \
856 case X86Local::MRM_##from: \
857 filter = new ExactFilter(0x##from); \
860 OpcodeType opcodeType = (OpcodeType)-1;
862 ModRMFilter* filter = NULL;
863 uint8_t opcodeToSet = 0;
866 default: llvm_unreachable("Invalid prefix!");
867 // Extended two-byte opcodes can start with 66 0f, f2 0f, f3 0f, or 0f
872 opcodeType = TWOBYTE;
876 if (needsModRMForDecode(Form))
877 filter = new ModFilter(isRegFormat(Form));
879 filter = new DumbFilter();
881 #define EXTENSION_TABLE(n) case 0x##n:
882 TWO_BYTE_EXTENSION_TABLES
883 #undef EXTENSION_TABLE
886 llvm_unreachable("Unhandled two-byte extended opcode");
887 case X86Local::MRM0r:
888 case X86Local::MRM1r:
889 case X86Local::MRM2r:
890 case X86Local::MRM3r:
891 case X86Local::MRM4r:
892 case X86Local::MRM5r:
893 case X86Local::MRM6r:
894 case X86Local::MRM7r:
895 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
897 case X86Local::MRM0m:
898 case X86Local::MRM1m:
899 case X86Local::MRM2m:
900 case X86Local::MRM3m:
901 case X86Local::MRM4m:
902 case X86Local::MRM5m:
903 case X86Local::MRM6m:
904 case X86Local::MRM7m:
905 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
911 opcodeToSet = Opcode;
917 opcodeType = THREEBYTE_38;
920 if (needsModRMForDecode(Form))
921 filter = new ModFilter(isRegFormat(Form));
923 filter = new DumbFilter();
925 #define EXTENSION_TABLE(n) case 0x##n:
926 THREE_BYTE_38_EXTENSION_TABLES
927 #undef EXTENSION_TABLE
930 llvm_unreachable("Unhandled two-byte extended opcode");
931 case X86Local::MRM0r:
932 case X86Local::MRM1r:
933 case X86Local::MRM2r:
934 case X86Local::MRM3r:
935 case X86Local::MRM4r:
936 case X86Local::MRM5r:
937 case X86Local::MRM6r:
938 case X86Local::MRM7r:
939 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
941 case X86Local::MRM0m:
942 case X86Local::MRM1m:
943 case X86Local::MRM2m:
944 case X86Local::MRM3m:
945 case X86Local::MRM4m:
946 case X86Local::MRM5m:
947 case X86Local::MRM6m:
948 case X86Local::MRM7m:
949 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
955 opcodeToSet = Opcode;
960 opcodeType = THREEBYTE_3A;
961 if (needsModRMForDecode(Form))
962 filter = new ModFilter(isRegFormat(Form));
964 filter = new DumbFilter();
965 opcodeToSet = Opcode;
968 opcodeType = THREEBYTE_A6;
969 if (needsModRMForDecode(Form))
970 filter = new ModFilter(isRegFormat(Form));
972 filter = new DumbFilter();
973 opcodeToSet = Opcode;
976 opcodeType = THREEBYTE_A7;
977 if (needsModRMForDecode(Form))
978 filter = new ModFilter(isRegFormat(Form));
980 filter = new DumbFilter();
981 opcodeToSet = Opcode;
984 opcodeType = XOP8_MAP;
985 if (needsModRMForDecode(Form))
986 filter = new ModFilter(isRegFormat(Form));
988 filter = new DumbFilter();
989 opcodeToSet = Opcode;
992 opcodeType = XOP9_MAP;
995 if (needsModRMForDecode(Form))
996 filter = new ModFilter(isRegFormat(Form));
998 filter = new DumbFilter();
1000 #define EXTENSION_TABLE(n) case 0x##n:
1001 XOP9_MAP_EXTENSION_TABLES
1002 #undef EXTENSION_TABLE
1005 llvm_unreachable("Unhandled XOP9 extended opcode");
1006 case X86Local::MRM0r:
1007 case X86Local::MRM1r:
1008 case X86Local::MRM2r:
1009 case X86Local::MRM3r:
1010 case X86Local::MRM4r:
1011 case X86Local::MRM5r:
1012 case X86Local::MRM6r:
1013 case X86Local::MRM7r:
1014 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1016 case X86Local::MRM0m:
1017 case X86Local::MRM1m:
1018 case X86Local::MRM2m:
1019 case X86Local::MRM3m:
1020 case X86Local::MRM4m:
1021 case X86Local::MRM5m:
1022 case X86Local::MRM6m:
1023 case X86Local::MRM7m:
1024 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1029 } // switch (Opcode)
1030 opcodeToSet = Opcode;
1032 case X86Local::XOPA:
1033 opcodeType = XOPA_MAP;
1034 if (needsModRMForDecode(Form))
1035 filter = new ModFilter(isRegFormat(Form));
1037 filter = new DumbFilter();
1038 opcodeToSet = Opcode;
1048 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1049 assert(Form == X86Local::RawFrm);
1050 opcodeType = ONEBYTE;
1051 filter = new ExactFilter(Opcode);
1052 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1056 opcodeType = ONEBYTE;
1058 #define EXTENSION_TABLE(n) case 0x##n:
1059 ONE_BYTE_EXTENSION_TABLES
1060 #undef EXTENSION_TABLE
1063 llvm_unreachable("Fell through the cracks of a single-byte "
1065 case X86Local::MRM0r:
1066 case X86Local::MRM1r:
1067 case X86Local::MRM2r:
1068 case X86Local::MRM3r:
1069 case X86Local::MRM4r:
1070 case X86Local::MRM5r:
1071 case X86Local::MRM6r:
1072 case X86Local::MRM7r:
1073 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1075 case X86Local::MRM0m:
1076 case X86Local::MRM1m:
1077 case X86Local::MRM2m:
1078 case X86Local::MRM3m:
1079 case X86Local::MRM4m:
1080 case X86Local::MRM5m:
1081 case X86Local::MRM6m:
1082 case X86Local::MRM7m:
1083 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1098 llvm_unreachable("Unhandled escape opcode form");
1099 case X86Local::MRM0r:
1100 case X86Local::MRM1r:
1101 case X86Local::MRM2r:
1102 case X86Local::MRM3r:
1103 case X86Local::MRM4r:
1104 case X86Local::MRM5r:
1105 case X86Local::MRM6r:
1106 case X86Local::MRM7r:
1107 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1109 case X86Local::MRM0m:
1110 case X86Local::MRM1m:
1111 case X86Local::MRM2m:
1112 case X86Local::MRM3m:
1113 case X86Local::MRM4m:
1114 case X86Local::MRM5m:
1115 case X86Local::MRM6m:
1116 case X86Local::MRM7m:
1117 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1122 if (needsModRMForDecode(Form))
1123 filter = new ModFilter(isRegFormat(Form));
1125 filter = new DumbFilter();
1127 } // switch (Opcode)
1128 opcodeToSet = Opcode;
1129 } // switch (Prefix)
1131 assert(opcodeType != (OpcodeType)-1 &&
1132 "Opcode type not set");
1133 assert(filter && "Filter not set");
1135 if (Form == X86Local::AddRegFrm) {
1136 assert(((opcodeToSet & 7) == 0) &&
1137 "ADDREG_FRM opcode not aligned");
1139 uint8_t currentOpcode;
1141 for (currentOpcode = opcodeToSet;
1142 currentOpcode < opcodeToSet + 8;
1144 tables.setTableFields(opcodeType,
1148 UID, Is32Bit, IgnoresVEX_L);
1150 tables.setTableFields(opcodeType,
1154 UID, Is32Bit, IgnoresVEX_L);
1162 #define TYPE(str, type) if (s == str) return type;
1163 OperandType RecognizableInstr::typeFromString(const std::string &s,
1164 bool hasREX_WPrefix,
1165 bool hasOpSizePrefix,
1166 bool hasOpSize16Prefix) {
1167 if(hasREX_WPrefix) {
1168 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1170 TYPE("GR32", TYPE_R32)
1172 if(hasOpSizePrefix) {
1173 // For instructions with an OpSize prefix, a declared 16-bit register or
1174 // immediate encoding is special.
1175 TYPE("GR16", TYPE_Rv)
1176 TYPE("i16imm", TYPE_IMMv)
1178 if(hasOpSize16Prefix) {
1179 // For instructions with an OpSize16 prefix, a declared 32-bit register or
1180 // immediate encoding is special.
1181 TYPE("GR32", TYPE_Rv)
1183 TYPE("i16mem", TYPE_Mv)
1184 TYPE("i16imm", TYPE_IMM16)
1185 TYPE("i16i8imm", TYPE_IMMv)
1186 TYPE("GR16", TYPE_R16)
1187 TYPE("i32mem", TYPE_Mv)
1188 TYPE("i32imm", TYPE_IMMv)
1189 TYPE("i32i8imm", TYPE_IMM32)
1190 TYPE("u32u8imm", TYPE_IMM32)
1191 TYPE("GR32", TYPE_R32)
1192 TYPE("GR32orGR64", TYPE_R32)
1193 TYPE("i64mem", TYPE_Mv)
1194 TYPE("i64i32imm", TYPE_IMM64)
1195 TYPE("i64i8imm", TYPE_IMM64)
1196 TYPE("GR64", TYPE_R64)
1197 TYPE("i8mem", TYPE_M8)
1198 TYPE("i8imm", TYPE_IMM8)
1199 TYPE("GR8", TYPE_R8)
1200 TYPE("VR128", TYPE_XMM128)
1201 TYPE("VR128X", TYPE_XMM128)
1202 TYPE("f128mem", TYPE_M128)
1203 TYPE("f256mem", TYPE_M256)
1204 TYPE("f512mem", TYPE_M512)
1205 TYPE("FR64", TYPE_XMM64)
1206 TYPE("FR64X", TYPE_XMM64)
1207 TYPE("f64mem", TYPE_M64FP)
1208 TYPE("sdmem", TYPE_M64FP)
1209 TYPE("FR32", TYPE_XMM32)
1210 TYPE("FR32X", TYPE_XMM32)
1211 TYPE("f32mem", TYPE_M32FP)
1212 TYPE("ssmem", TYPE_M32FP)
1213 TYPE("RST", TYPE_ST)
1214 TYPE("i128mem", TYPE_M128)
1215 TYPE("i256mem", TYPE_M256)
1216 TYPE("i512mem", TYPE_M512)
1217 TYPE("i64i32imm_pcrel", TYPE_REL64)
1218 TYPE("i16imm_pcrel", TYPE_REL16)
1219 TYPE("i32imm_pcrel", TYPE_REL32)
1220 TYPE("SSECC", TYPE_IMM3)
1221 TYPE("AVXCC", TYPE_IMM5)
1222 TYPE("AVX512RC", TYPE_IMM32)
1223 TYPE("brtarget", TYPE_RELv)
1224 TYPE("uncondbrtarget", TYPE_RELv)
1225 TYPE("brtarget8", TYPE_REL8)
1226 TYPE("f80mem", TYPE_M80FP)
1227 TYPE("lea32mem", TYPE_LEA)
1228 TYPE("lea64_32mem", TYPE_LEA)
1229 TYPE("lea64mem", TYPE_LEA)
1230 TYPE("VR64", TYPE_MM64)
1231 TYPE("i64imm", TYPE_IMMv)
1232 TYPE("opaque32mem", TYPE_M1616)
1233 TYPE("opaque48mem", TYPE_M1632)
1234 TYPE("opaque80mem", TYPE_M1664)
1235 TYPE("opaque512mem", TYPE_M512)
1236 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1237 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1238 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1239 TYPE("offset8", TYPE_MOFFS8)
1240 TYPE("offset16", TYPE_MOFFS16)
1241 TYPE("offset32", TYPE_MOFFS32)
1242 TYPE("offset64", TYPE_MOFFS64)
1243 TYPE("VR256", TYPE_XMM256)
1244 TYPE("VR256X", TYPE_XMM256)
1245 TYPE("VR512", TYPE_XMM512)
1246 TYPE("VK1", TYPE_VK1)
1247 TYPE("VK1WM", TYPE_VK1)
1248 TYPE("VK8", TYPE_VK8)
1249 TYPE("VK8WM", TYPE_VK8)
1250 TYPE("VK16", TYPE_VK16)
1251 TYPE("VK16WM", TYPE_VK16)
1252 TYPE("GR16_NOAX", TYPE_Rv)
1253 TYPE("GR32_NOAX", TYPE_Rv)
1254 TYPE("GR64_NOAX", TYPE_R64)
1255 TYPE("vx32mem", TYPE_M32)
1256 TYPE("vy32mem", TYPE_M32)
1257 TYPE("vz32mem", TYPE_M32)
1258 TYPE("vx64mem", TYPE_M64)
1259 TYPE("vy64mem", TYPE_M64)
1260 TYPE("vy64xmem", TYPE_M64)
1261 TYPE("vz64mem", TYPE_M64)
1262 errs() << "Unhandled type string " << s << "\n";
1263 llvm_unreachable("Unhandled type string");
1267 #define ENCODING(str, encoding) if (s == str) return encoding;
1268 OperandEncoding RecognizableInstr::immediateEncodingFromString
1269 (const std::string &s,
1270 bool hasOpSizePrefix) {
1271 if(!hasOpSizePrefix) {
1272 // For instructions without an OpSize prefix, a declared 16-bit register or
1273 // immediate encoding is special.
1274 ENCODING("i16imm", ENCODING_IW)
1276 ENCODING("i32i8imm", ENCODING_IB)
1277 ENCODING("u32u8imm", ENCODING_IB)
1278 ENCODING("SSECC", ENCODING_IB)
1279 ENCODING("AVXCC", ENCODING_IB)
1280 ENCODING("AVX512RC", ENCODING_IB)
1281 ENCODING("i16imm", ENCODING_Iv)
1282 ENCODING("i16i8imm", ENCODING_IB)
1283 ENCODING("i32imm", ENCODING_Iv)
1284 ENCODING("i64i32imm", ENCODING_ID)
1285 ENCODING("i64i8imm", ENCODING_IB)
1286 ENCODING("i8imm", ENCODING_IB)
1287 // This is not a typo. Instructions like BLENDVPD put
1288 // register IDs in 8-bit immediates nowadays.
1289 ENCODING("FR32", ENCODING_IB)
1290 ENCODING("FR64", ENCODING_IB)
1291 ENCODING("VR128", ENCODING_IB)
1292 ENCODING("VR256", ENCODING_IB)
1293 ENCODING("FR32X", ENCODING_IB)
1294 ENCODING("FR64X", ENCODING_IB)
1295 ENCODING("VR128X", ENCODING_IB)
1296 ENCODING("VR256X", ENCODING_IB)
1297 ENCODING("VR512", ENCODING_IB)
1298 errs() << "Unhandled immediate encoding " << s << "\n";
1299 llvm_unreachable("Unhandled immediate encoding");
1302 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1303 (const std::string &s,
1304 bool hasOpSizePrefix) {
1305 ENCODING("RST", ENCODING_FP)
1306 ENCODING("GR16", ENCODING_RM)
1307 ENCODING("GR32", ENCODING_RM)
1308 ENCODING("GR32orGR64", ENCODING_RM)
1309 ENCODING("GR64", ENCODING_RM)
1310 ENCODING("GR8", ENCODING_RM)
1311 ENCODING("VR128", ENCODING_RM)
1312 ENCODING("VR128X", ENCODING_RM)
1313 ENCODING("FR64", ENCODING_RM)
1314 ENCODING("FR32", ENCODING_RM)
1315 ENCODING("FR64X", ENCODING_RM)
1316 ENCODING("FR32X", ENCODING_RM)
1317 ENCODING("VR64", ENCODING_RM)
1318 ENCODING("VR256", ENCODING_RM)
1319 ENCODING("VR256X", ENCODING_RM)
1320 ENCODING("VR512", ENCODING_RM)
1321 ENCODING("VK1", ENCODING_RM)
1322 ENCODING("VK8", ENCODING_RM)
1323 ENCODING("VK16", ENCODING_RM)
1324 errs() << "Unhandled R/M register encoding " << s << "\n";
1325 llvm_unreachable("Unhandled R/M register encoding");
1328 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1329 (const std::string &s,
1330 bool hasOpSizePrefix) {
1331 ENCODING("GR16", ENCODING_REG)
1332 ENCODING("GR32", ENCODING_REG)
1333 ENCODING("GR32orGR64", ENCODING_REG)
1334 ENCODING("GR64", ENCODING_REG)
1335 ENCODING("GR8", ENCODING_REG)
1336 ENCODING("VR128", ENCODING_REG)
1337 ENCODING("FR64", ENCODING_REG)
1338 ENCODING("FR32", ENCODING_REG)
1339 ENCODING("VR64", ENCODING_REG)
1340 ENCODING("SEGMENT_REG", ENCODING_REG)
1341 ENCODING("DEBUG_REG", ENCODING_REG)
1342 ENCODING("CONTROL_REG", ENCODING_REG)
1343 ENCODING("VR256", ENCODING_REG)
1344 ENCODING("VR256X", ENCODING_REG)
1345 ENCODING("VR128X", ENCODING_REG)
1346 ENCODING("FR64X", ENCODING_REG)
1347 ENCODING("FR32X", ENCODING_REG)
1348 ENCODING("VR512", ENCODING_REG)
1349 ENCODING("VK1", ENCODING_REG)
1350 ENCODING("VK8", ENCODING_REG)
1351 ENCODING("VK16", ENCODING_REG)
1352 ENCODING("VK1WM", ENCODING_REG)
1353 ENCODING("VK8WM", ENCODING_REG)
1354 ENCODING("VK16WM", ENCODING_REG)
1355 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1356 llvm_unreachable("Unhandled reg/opcode register encoding");
1359 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1360 (const std::string &s,
1361 bool hasOpSizePrefix) {
1362 ENCODING("GR32", ENCODING_VVVV)
1363 ENCODING("GR64", ENCODING_VVVV)
1364 ENCODING("FR32", ENCODING_VVVV)
1365 ENCODING("FR64", ENCODING_VVVV)
1366 ENCODING("VR128", ENCODING_VVVV)
1367 ENCODING("VR256", ENCODING_VVVV)
1368 ENCODING("FR32X", ENCODING_VVVV)
1369 ENCODING("FR64X", ENCODING_VVVV)
1370 ENCODING("VR128X", ENCODING_VVVV)
1371 ENCODING("VR256X", ENCODING_VVVV)
1372 ENCODING("VR512", ENCODING_VVVV)
1373 ENCODING("VK1", ENCODING_VVVV)
1374 ENCODING("VK8", ENCODING_VVVV)
1375 ENCODING("VK16", ENCODING_VVVV)
1376 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1377 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1380 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1381 (const std::string &s,
1382 bool hasOpSizePrefix) {
1383 ENCODING("VK1WM", ENCODING_WRITEMASK)
1384 ENCODING("VK8WM", ENCODING_WRITEMASK)
1385 ENCODING("VK16WM", ENCODING_WRITEMASK)
1386 errs() << "Unhandled mask register encoding " << s << "\n";
1387 llvm_unreachable("Unhandled mask register encoding");
1390 OperandEncoding RecognizableInstr::memoryEncodingFromString
1391 (const std::string &s,
1392 bool hasOpSizePrefix) {
1393 ENCODING("i16mem", ENCODING_RM)
1394 ENCODING("i32mem", ENCODING_RM)
1395 ENCODING("i64mem", ENCODING_RM)
1396 ENCODING("i8mem", ENCODING_RM)
1397 ENCODING("ssmem", ENCODING_RM)
1398 ENCODING("sdmem", ENCODING_RM)
1399 ENCODING("f128mem", ENCODING_RM)
1400 ENCODING("f256mem", ENCODING_RM)
1401 ENCODING("f512mem", ENCODING_RM)
1402 ENCODING("f64mem", ENCODING_RM)
1403 ENCODING("f32mem", ENCODING_RM)
1404 ENCODING("i128mem", ENCODING_RM)
1405 ENCODING("i256mem", ENCODING_RM)
1406 ENCODING("i512mem", ENCODING_RM)
1407 ENCODING("f80mem", ENCODING_RM)
1408 ENCODING("lea32mem", ENCODING_RM)
1409 ENCODING("lea64_32mem", ENCODING_RM)
1410 ENCODING("lea64mem", ENCODING_RM)
1411 ENCODING("opaque32mem", ENCODING_RM)
1412 ENCODING("opaque48mem", ENCODING_RM)
1413 ENCODING("opaque80mem", ENCODING_RM)
1414 ENCODING("opaque512mem", ENCODING_RM)
1415 ENCODING("vx32mem", ENCODING_RM)
1416 ENCODING("vy32mem", ENCODING_RM)
1417 ENCODING("vz32mem", ENCODING_RM)
1418 ENCODING("vx64mem", ENCODING_RM)
1419 ENCODING("vy64mem", ENCODING_RM)
1420 ENCODING("vy64xmem", ENCODING_RM)
1421 ENCODING("vz64mem", ENCODING_RM)
1422 errs() << "Unhandled memory encoding " << s << "\n";
1423 llvm_unreachable("Unhandled memory encoding");
1426 OperandEncoding RecognizableInstr::relocationEncodingFromString
1427 (const std::string &s,
1428 bool hasOpSizePrefix) {
1429 if(!hasOpSizePrefix) {
1430 // For instructions without an OpSize prefix, a declared 16-bit register or
1431 // immediate encoding is special.
1432 ENCODING("i16imm", ENCODING_IW)
1434 ENCODING("i16imm", ENCODING_Iv)
1435 ENCODING("i16i8imm", ENCODING_IB)
1436 ENCODING("i32imm", ENCODING_Iv)
1437 ENCODING("i32i8imm", ENCODING_IB)
1438 ENCODING("i64i32imm", ENCODING_ID)
1439 ENCODING("i64i8imm", ENCODING_IB)
1440 ENCODING("i8imm", ENCODING_IB)
1441 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1442 ENCODING("i16imm_pcrel", ENCODING_IW)
1443 ENCODING("i32imm_pcrel", ENCODING_ID)
1444 ENCODING("brtarget", ENCODING_Iv)
1445 ENCODING("brtarget8", ENCODING_IB)
1446 ENCODING("i64imm", ENCODING_IO)
1447 ENCODING("offset8", ENCODING_Ia)
1448 ENCODING("offset16", ENCODING_Ia)
1449 ENCODING("offset32", ENCODING_Ia)
1450 ENCODING("offset64", ENCODING_Ia)
1451 errs() << "Unhandled relocation encoding " << s << "\n";
1452 llvm_unreachable("Unhandled relocation encoding");
1455 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1456 (const std::string &s,
1457 bool hasOpSizePrefix) {
1458 ENCODING("GR32", ENCODING_Rv)
1459 ENCODING("GR64", ENCODING_RO)
1460 ENCODING("GR16", ENCODING_Rv)
1461 ENCODING("GR8", ENCODING_RB)
1462 ENCODING("GR16_NOAX", ENCODING_Rv)
1463 ENCODING("GR32_NOAX", ENCODING_Rv)
1464 ENCODING("GR64_NOAX", ENCODING_RO)
1465 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1466 llvm_unreachable("Unhandled opcode modifier encoding");