1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
41 // A clone of X86 since we can't depend on something that is generated.
51 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
52 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
53 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
54 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
56 #define MAP(from, to) MRM_##from = to,
67 D8 = 3, D9 = 4, DA = 5, DB = 6,
68 DC = 7, DD = 8, DE = 9, DF = 10,
71 P_0F_AE = 16, P_0F_01 = 17
75 // If rows are added to the opcode extension tables, then corresponding entries
76 // must be added here.
78 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
79 // that byte to ONE_BYTE_EXTENSION_TABLES.
81 // If the row corresponds to two bytes where the first is 0f, add an entry for
82 // the second byte to TWO_BYTE_EXTENSION_TABLES.
84 // If the row corresponds to some other set of bytes, you will need to modify
85 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
86 // to the X86 TD files, except in two cases: if the first two bytes of such a
87 // new combination are 0f 38 or 0f 3a, you just have to add maps called
88 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
89 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
90 // in RecognizableInstr::emitDecodePath().
92 #define ONE_BYTE_EXTENSION_TABLES \
100 EXTENSION_TABLE(c6) \
101 EXTENSION_TABLE(c7) \
102 EXTENSION_TABLE(d0) \
103 EXTENSION_TABLE(d1) \
104 EXTENSION_TABLE(d2) \
105 EXTENSION_TABLE(d3) \
106 EXTENSION_TABLE(f6) \
107 EXTENSION_TABLE(f7) \
108 EXTENSION_TABLE(fe) \
111 #define TWO_BYTE_EXTENSION_TABLES \
112 EXTENSION_TABLE(00) \
113 EXTENSION_TABLE(01) \
114 EXTENSION_TABLE(18) \
115 EXTENSION_TABLE(71) \
116 EXTENSION_TABLE(72) \
117 EXTENSION_TABLE(73) \
118 EXTENSION_TABLE(ae) \
119 EXTENSION_TABLE(ba) \
122 using namespace X86Disassembler;
124 /// needsModRMForDecode - Indicates whether a particular instruction requires a
125 /// ModR/M byte for the instruction to be properly decoded. For example, a
126 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
129 /// @param form - The form of the instruction.
130 /// @return - true if the form implies that a ModR/M byte is required, false
132 static bool needsModRMForDecode(uint8_t form) {
133 if (form == X86Local::MRMDestReg ||
134 form == X86Local::MRMDestMem ||
135 form == X86Local::MRMSrcReg ||
136 form == X86Local::MRMSrcMem ||
137 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
138 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
144 /// isRegFormat - Indicates whether a particular form requires the Mod field of
145 /// the ModR/M byte to be 0b11.
147 /// @param form - The form of the instruction.
148 /// @return - true if the form implies that Mod must be 0b11, false
150 static bool isRegFormat(uint8_t form) {
151 if (form == X86Local::MRMDestReg ||
152 form == X86Local::MRMSrcReg ||
153 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
159 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
160 /// Useful for switch statements and the like.
162 /// @param init - A reference to the BitsInit to be decoded.
163 /// @return - The field, with the first bit in the BitsInit as the lowest
165 static uint8_t byteFromBitsInit(BitsInit &init) {
166 int width = init.getNumBits();
168 assert(width <= 8 && "Field is too large for uint8_t!");
175 for (index = 0; index < width; index++) {
176 if (static_cast<BitInit*>(init.getBit(index))->getValue())
185 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
186 /// name of the field.
188 /// @param rec - The record from which to extract the value.
189 /// @param name - The name of the field in the record.
190 /// @return - The field, as translated by byteFromBitsInit().
191 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
192 BitsInit* bits = rec->getValueAsBitsInit(name);
193 return byteFromBitsInit(*bits);
196 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
197 const CodeGenInstruction &insn,
202 Name = Rec->getName();
203 Spec = &tables.specForUID(UID);
205 if (!Rec->isSubClassOf("X86Inst")) {
206 ShouldBeEmitted = false;
210 Prefix = byteFromRec(Rec, "Prefix");
211 Opcode = byteFromRec(Rec, "Opcode");
212 Form = byteFromRec(Rec, "FormBits");
213 SegOvr = byteFromRec(Rec, "SegOvrBits");
215 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
216 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
217 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
218 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
219 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
221 Name = Rec->getName();
222 AsmString = Rec->getValueAsString("AsmString");
224 Operands = &insn.Operands.OperandList;
226 IsSSE = HasOpSizePrefix && (Name.find("16") == Name.npos);
227 HasFROperands = false;
229 ShouldBeEmitted = true;
232 void RecognizableInstr::processInstr(DisassemblerTables &tables,
233 const CodeGenInstruction &insn,
236 // Ignore "asm parser only" instructions.
237 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
240 RecognizableInstr recogInstr(tables, insn, uid);
242 recogInstr.emitInstructionSpecifier(tables);
244 if (recogInstr.shouldBeEmitted())
245 recogInstr.emitDecodePath(tables);
248 InstructionContext RecognizableInstr::insnContext() const {
249 InstructionContext insnContext;
251 if (Name.find("64") != Name.npos || HasREX_WPrefix) {
252 if (HasREX_WPrefix && HasOpSizePrefix)
253 insnContext = IC_64BIT_REXW_OPSIZE;
254 else if (HasOpSizePrefix)
255 insnContext = IC_64BIT_OPSIZE;
256 else if (HasREX_WPrefix && Prefix == X86Local::XS)
257 insnContext = IC_64BIT_REXW_XS;
258 else if (HasREX_WPrefix && Prefix == X86Local::XD)
259 insnContext = IC_64BIT_REXW_XD;
260 else if (Prefix == X86Local::XD)
261 insnContext = IC_64BIT_XD;
262 else if (Prefix == X86Local::XS)
263 insnContext = IC_64BIT_XS;
264 else if (HasREX_WPrefix)
265 insnContext = IC_64BIT_REXW;
267 insnContext = IC_64BIT;
270 insnContext = IC_OPSIZE;
271 else if (Prefix == X86Local::XD)
273 else if (Prefix == X86Local::XS)
282 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
283 // Filter out intrinsics
285 if (!Rec->isSubClassOf("X86Inst"))
286 return FILTER_STRONG;
288 if (Form == X86Local::Pseudo ||
290 return FILTER_STRONG;
292 if (Form == X86Local::MRMInitReg)
293 return FILTER_STRONG;
296 // Filter out instructions with a LOCK prefix;
297 // prefer forms that do not have the prefix
301 // Filter out artificial instructions
303 if (Name.find("TAILJMP") != Name.npos ||
304 Name.find("_Int") != Name.npos ||
305 Name.find("_int") != Name.npos ||
306 Name.find("Int_") != Name.npos ||
307 Name.find("_NOREX") != Name.npos ||
308 Name.find("_TC") != Name.npos ||
309 Name.find("EH_RETURN") != Name.npos ||
310 Name.find("V_SET") != Name.npos ||
311 Name.find("LOCK_") != Name.npos ||
312 Name.find("WIN") != Name.npos)
313 return FILTER_STRONG;
317 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
319 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
322 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
324 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
326 if (Name.find("Fs") != Name.npos)
328 if (Name == "MOVLPDrr" ||
329 Name == "MOVLPSrr" ||
335 Name == "MOVSX16rm8" ||
336 Name == "MOVSX16rr8" ||
337 Name == "MOVZX16rm8" ||
338 Name == "MOVZX16rr8" ||
339 Name == "PUSH32i16" ||
340 Name == "PUSH64i16" ||
341 Name == "MOVPQI2QImr" ||
346 Name == "MMX_MOVD64rrv164" ||
347 Name == "CRC32m16" ||
348 Name == "MOV64ri64i32" ||
352 // Filter out instructions with segment override prefixes.
353 // They're too messy to handle now and we'll special case them if needed.
356 return FILTER_STRONG;
358 // Filter out instructions that can't be printed.
360 if (AsmString.size() == 0)
361 return FILTER_STRONG;
363 // Filter out instructions with subreg operands.
365 if (AsmString.find("subreg") != AsmString.npos)
366 return FILTER_STRONG;
368 if (HasFROperands && Name.find("MOV") != Name.npos &&
369 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
370 (Name.find("to") != Name.npos)))
373 return FILTER_NORMAL;
376 void RecognizableInstr::handleOperand(
378 unsigned &operandIndex,
379 unsigned &physicalOperandIndex,
380 unsigned &numPhysicalOperands,
381 unsigned *operandMapping,
382 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
384 if (physicalOperandIndex >= numPhysicalOperands)
387 assert(physicalOperandIndex < numPhysicalOperands);
390 while (operandMapping[operandIndex] != operandIndex) {
391 Spec->operands[operandIndex].encoding = ENCODING_DUP;
392 Spec->operands[operandIndex].type =
393 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
397 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
399 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
401 Spec->operands[operandIndex].type = typeFromString(typeName,
407 ++physicalOperandIndex;
410 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
413 if (!Rec->isSubClassOf("X86Inst"))
418 Spec->filtered = true;
421 ShouldBeEmitted = false;
427 Spec->insnContext = insnContext();
429 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
431 unsigned operandIndex;
432 unsigned numOperands = OperandList.size();
433 unsigned numPhysicalOperands = 0;
435 // operandMapping maps from operands in OperandList to their originals.
436 // If operandMapping[i] != i, then the entry is a duplicate.
437 unsigned operandMapping[X86_MAX_OPERANDS];
439 bool hasFROperands = false;
441 assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
443 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
444 if (OperandList[operandIndex].Constraints.size()) {
445 const CGIOperandList::ConstraintInfo &Constraint =
446 OperandList[operandIndex].Constraints[0];
447 if (Constraint.isTied()) {
448 operandMapping[operandIndex] = Constraint.getTiedOperand();
450 ++numPhysicalOperands;
451 operandMapping[operandIndex] = operandIndex;
454 ++numPhysicalOperands;
455 operandMapping[operandIndex] = operandIndex;
458 const std::string &recName = OperandList[operandIndex].Rec->getName();
460 if (recName.find("FR") != recName.npos)
461 hasFROperands = true;
464 if (hasFROperands && Name.find("MOV") != Name.npos &&
465 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
466 (Name.find("to") != Name.npos)))
467 ShouldBeEmitted = false;
469 if (!ShouldBeEmitted)
472 #define HANDLE_OPERAND(class) \
473 handleOperand(false, \
475 physicalOperandIndex, \
476 numPhysicalOperands, \
478 class##EncodingFromString);
480 #define HANDLE_OPTIONAL(class) \
481 handleOperand(true, \
483 physicalOperandIndex, \
484 numPhysicalOperands, \
486 class##EncodingFromString);
488 // operandIndex should always be < numOperands
490 // physicalOperandIndex should always be < numPhysicalOperands
491 unsigned physicalOperandIndex = 0;
494 case X86Local::RawFrm:
495 // Operand 1 (optional) is an address or immediate.
496 // Operand 2 (optional) is an immediate.
497 assert(numPhysicalOperands <= 2 &&
498 "Unexpected number of operands for RawFrm");
499 HANDLE_OPTIONAL(relocation)
500 HANDLE_OPTIONAL(immediate)
502 case X86Local::AddRegFrm:
503 // Operand 1 is added to the opcode.
504 // Operand 2 (optional) is an address.
505 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
506 "Unexpected number of operands for AddRegFrm");
507 HANDLE_OPERAND(opcodeModifier)
508 HANDLE_OPTIONAL(relocation)
510 case X86Local::MRMDestReg:
511 // Operand 1 is a register operand in the R/M field.
512 // Operand 2 is a register operand in the Reg/Opcode field.
513 // Operand 3 (optional) is an immediate.
514 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
515 "Unexpected number of operands for MRMDestRegFrm");
516 HANDLE_OPERAND(rmRegister)
517 HANDLE_OPERAND(roRegister)
518 HANDLE_OPTIONAL(immediate)
520 case X86Local::MRMDestMem:
521 // Operand 1 is a memory operand (possibly SIB-extended)
522 // Operand 2 is a register operand in the Reg/Opcode field.
523 // Operand 3 (optional) is an immediate.
524 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
525 "Unexpected number of operands for MRMDestMemFrm");
526 HANDLE_OPERAND(memory)
527 HANDLE_OPERAND(roRegister)
528 HANDLE_OPTIONAL(immediate)
530 case X86Local::MRMSrcReg:
531 // Operand 1 is a register operand in the Reg/Opcode field.
532 // Operand 2 is a register operand in the R/M field.
533 // Operand 3 (optional) is an immediate.
534 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
535 "Unexpected number of operands for MRMSrcRegFrm");
536 HANDLE_OPERAND(roRegister)
537 HANDLE_OPERAND(rmRegister)
540 // FIXME: In AVX, the register below becomes the one encoded
541 // in ModRMVEX and the one above the one in the VEX.VVVV field
542 HANDLE_OPTIONAL(rmRegister)
544 HANDLE_OPTIONAL(immediate)
546 case X86Local::MRMSrcMem:
547 // Operand 1 is a register operand in the Reg/Opcode field.
548 // Operand 2 is a memory operand (possibly SIB-extended)
549 // Operand 3 (optional) is an immediate.
550 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
551 "Unexpected number of operands for MRMSrcMemFrm");
552 HANDLE_OPERAND(roRegister)
555 // FIXME: In AVX, the register below becomes the one encoded
556 // in ModRMVEX and the one above the one in the VEX.VVVV field
557 HANDLE_OPTIONAL(rmRegister)
559 HANDLE_OPERAND(memory)
560 HANDLE_OPTIONAL(immediate)
562 case X86Local::MRM0r:
563 case X86Local::MRM1r:
564 case X86Local::MRM2r:
565 case X86Local::MRM3r:
566 case X86Local::MRM4r:
567 case X86Local::MRM5r:
568 case X86Local::MRM6r:
569 case X86Local::MRM7r:
570 // Operand 1 is a register operand in the R/M field.
571 // Operand 2 (optional) is an immediate or relocation.
572 assert(numPhysicalOperands <= 2 &&
573 "Unexpected number of operands for MRMnRFrm");
574 HANDLE_OPTIONAL(rmRegister)
575 HANDLE_OPTIONAL(relocation)
577 case X86Local::MRM0m:
578 case X86Local::MRM1m:
579 case X86Local::MRM2m:
580 case X86Local::MRM3m:
581 case X86Local::MRM4m:
582 case X86Local::MRM5m:
583 case X86Local::MRM6m:
584 case X86Local::MRM7m:
585 // Operand 1 is a memory operand (possibly SIB-extended)
586 // Operand 2 (optional) is an immediate or relocation.
587 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
588 "Unexpected number of operands for MRMnMFrm");
589 HANDLE_OPERAND(memory)
590 HANDLE_OPTIONAL(relocation)
592 case X86Local::RawFrmImm8:
593 // operand 1 is a 16-bit immediate
594 // operand 2 is an 8-bit immediate
595 assert(numPhysicalOperands == 2 &&
596 "Unexpected number of operands for X86Local::RawFrmImm8");
597 HANDLE_OPERAND(immediate)
598 HANDLE_OPERAND(immediate)
600 case X86Local::RawFrmImm16:
601 // operand 1 is a 16-bit immediate
602 // operand 2 is a 16-bit immediate
603 HANDLE_OPERAND(immediate)
604 HANDLE_OPERAND(immediate)
606 case X86Local::MRMInitReg:
611 #undef HANDLE_OPERAND
612 #undef HANDLE_OPTIONAL
615 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
616 // Special cases where the LLVM tables are not complete
618 #define MAP(from, to) \
619 case X86Local::MRM_##from: \
620 filter = new ExactFilter(0x##from); \
623 OpcodeType opcodeType = (OpcodeType)-1;
625 ModRMFilter* filter = NULL;
626 uint8_t opcodeToSet = 0;
629 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
633 opcodeType = TWOBYTE;
637 if (needsModRMForDecode(Form))
638 filter = new ModFilter(isRegFormat(Form));
640 filter = new DumbFilter();
642 #define EXTENSION_TABLE(n) case 0x##n:
643 TWO_BYTE_EXTENSION_TABLES
644 #undef EXTENSION_TABLE
647 llvm_unreachable("Unhandled two-byte extended opcode");
648 case X86Local::MRM0r:
649 case X86Local::MRM1r:
650 case X86Local::MRM2r:
651 case X86Local::MRM3r:
652 case X86Local::MRM4r:
653 case X86Local::MRM5r:
654 case X86Local::MRM6r:
655 case X86Local::MRM7r:
656 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
658 case X86Local::MRM0m:
659 case X86Local::MRM1m:
660 case X86Local::MRM2m:
661 case X86Local::MRM3m:
662 case X86Local::MRM4m:
663 case X86Local::MRM5m:
664 case X86Local::MRM6m:
665 case X86Local::MRM7m:
666 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
672 opcodeToSet = Opcode;
675 opcodeType = THREEBYTE_38;
676 if (needsModRMForDecode(Form))
677 filter = new ModFilter(isRegFormat(Form));
679 filter = new DumbFilter();
680 opcodeToSet = Opcode;
683 opcodeType = THREEBYTE_3A;
684 if (needsModRMForDecode(Form))
685 filter = new ModFilter(isRegFormat(Form));
687 filter = new DumbFilter();
688 opcodeToSet = Opcode;
698 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
699 opcodeType = ONEBYTE;
700 if (Form == X86Local::AddRegFrm) {
701 Spec->modifierType = MODIFIER_MODRM;
702 Spec->modifierBase = Opcode;
703 filter = new AddRegEscapeFilter(Opcode);
705 filter = new EscapeFilter(true, Opcode);
707 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
710 opcodeType = ONEBYTE;
712 #define EXTENSION_TABLE(n) case 0x##n:
713 ONE_BYTE_EXTENSION_TABLES
714 #undef EXTENSION_TABLE
717 llvm_unreachable("Fell through the cracks of a single-byte "
719 case X86Local::MRM0r:
720 case X86Local::MRM1r:
721 case X86Local::MRM2r:
722 case X86Local::MRM3r:
723 case X86Local::MRM4r:
724 case X86Local::MRM5r:
725 case X86Local::MRM6r:
726 case X86Local::MRM7r:
727 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
729 case X86Local::MRM0m:
730 case X86Local::MRM1m:
731 case X86Local::MRM2m:
732 case X86Local::MRM3m:
733 case X86Local::MRM4m:
734 case X86Local::MRM5m:
735 case X86Local::MRM6m:
736 case X86Local::MRM7m:
737 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
750 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
753 if (needsModRMForDecode(Form))
754 filter = new ModFilter(isRegFormat(Form));
756 filter = new DumbFilter();
759 opcodeToSet = Opcode;
762 assert(opcodeType != (OpcodeType)-1 &&
763 "Opcode type not set");
764 assert(filter && "Filter not set");
766 if (Form == X86Local::AddRegFrm) {
767 if(Spec->modifierType != MODIFIER_MODRM) {
768 assert(opcodeToSet < 0xf9 &&
769 "Not enough room for all ADDREG_FRM operands");
771 uint8_t currentOpcode;
773 for (currentOpcode = opcodeToSet;
774 currentOpcode < opcodeToSet + 8;
776 tables.setTableFields(opcodeType,
782 Spec->modifierType = MODIFIER_OPCODE;
783 Spec->modifierBase = opcodeToSet;
785 // modifierBase was set where MODIFIER_MODRM was set
786 tables.setTableFields(opcodeType,
793 tables.setTableFields(opcodeType,
799 Spec->modifierType = MODIFIER_NONE;
800 Spec->modifierBase = opcodeToSet;
808 #define TYPE(str, type) if (s == str) return type;
809 OperandType RecognizableInstr::typeFromString(const std::string &s,
812 bool hasOpSizePrefix) {
814 // For SSE instructions, we ignore the OpSize prefix and force operand
816 TYPE("GR16", TYPE_R16)
817 TYPE("GR32", TYPE_R32)
818 TYPE("GR64", TYPE_R64)
821 // For instructions with a REX_W prefix, a declared 32-bit register encoding
823 TYPE("GR32", TYPE_R32)
825 if(!hasOpSizePrefix) {
826 // For instructions without an OpSize prefix, a declared 16-bit register or
827 // immediate encoding is special.
828 TYPE("GR16", TYPE_R16)
829 TYPE("i16imm", TYPE_IMM16)
831 TYPE("i16mem", TYPE_Mv)
832 TYPE("i16imm", TYPE_IMMv)
833 TYPE("i16i8imm", TYPE_IMMv)
834 TYPE("GR16", TYPE_Rv)
835 TYPE("i32mem", TYPE_Mv)
836 TYPE("i32imm", TYPE_IMMv)
837 TYPE("i32i8imm", TYPE_IMM32)
838 TYPE("GR32", TYPE_Rv)
839 TYPE("i64mem", TYPE_Mv)
840 TYPE("i64i32imm", TYPE_IMM64)
841 TYPE("i64i8imm", TYPE_IMM64)
842 TYPE("GR64", TYPE_R64)
843 TYPE("i8mem", TYPE_M8)
844 TYPE("i8imm", TYPE_IMM8)
846 TYPE("VR128", TYPE_XMM128)
847 TYPE("f128mem", TYPE_M128)
848 TYPE("f256mem", TYPE_M256)
849 TYPE("FR64", TYPE_XMM64)
850 TYPE("f64mem", TYPE_M64FP)
851 TYPE("sdmem", TYPE_M64FP)
852 TYPE("FR32", TYPE_XMM32)
853 TYPE("f32mem", TYPE_M32FP)
854 TYPE("ssmem", TYPE_M32FP)
856 TYPE("i128mem", TYPE_M128)
857 TYPE("i64i32imm_pcrel", TYPE_REL64)
858 TYPE("i16imm_pcrel", TYPE_REL16)
859 TYPE("i32imm_pcrel", TYPE_REL32)
860 TYPE("SSECC", TYPE_IMM3)
861 TYPE("brtarget", TYPE_RELv)
862 TYPE("uncondbrtarget", TYPE_RELv)
863 TYPE("brtarget8", TYPE_REL8)
864 TYPE("f80mem", TYPE_M80FP)
865 TYPE("lea32mem", TYPE_LEA)
866 TYPE("lea64_32mem", TYPE_LEA)
867 TYPE("lea64mem", TYPE_LEA)
868 TYPE("VR64", TYPE_MM64)
869 TYPE("i64imm", TYPE_IMMv)
870 TYPE("opaque32mem", TYPE_M1616)
871 TYPE("opaque48mem", TYPE_M1632)
872 TYPE("opaque80mem", TYPE_M1664)
873 TYPE("opaque512mem", TYPE_M512)
874 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
875 TYPE("DEBUG_REG", TYPE_DEBUGREG)
876 TYPE("CONTROL_REG", TYPE_CONTROLREG)
877 TYPE("offset8", TYPE_MOFFS8)
878 TYPE("offset16", TYPE_MOFFS16)
879 TYPE("offset32", TYPE_MOFFS32)
880 TYPE("offset64", TYPE_MOFFS64)
881 errs() << "Unhandled type string " << s << "\n";
882 llvm_unreachable("Unhandled type string");
886 #define ENCODING(str, encoding) if (s == str) return encoding;
887 OperandEncoding RecognizableInstr::immediateEncodingFromString
888 (const std::string &s,
889 bool hasOpSizePrefix) {
890 if(!hasOpSizePrefix) {
891 // For instructions without an OpSize prefix, a declared 16-bit register or
892 // immediate encoding is special.
893 ENCODING("i16imm", ENCODING_IW)
895 ENCODING("i32i8imm", ENCODING_IB)
896 ENCODING("SSECC", ENCODING_IB)
897 ENCODING("i16imm", ENCODING_Iv)
898 ENCODING("i16i8imm", ENCODING_IB)
899 ENCODING("i32imm", ENCODING_Iv)
900 ENCODING("i64i32imm", ENCODING_ID)
901 ENCODING("i64i8imm", ENCODING_IB)
902 ENCODING("i8imm", ENCODING_IB)
903 errs() << "Unhandled immediate encoding " << s << "\n";
904 llvm_unreachable("Unhandled immediate encoding");
907 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
908 (const std::string &s,
909 bool hasOpSizePrefix) {
910 ENCODING("GR16", ENCODING_RM)
911 ENCODING("GR32", ENCODING_RM)
912 ENCODING("GR64", ENCODING_RM)
913 ENCODING("GR8", ENCODING_RM)
914 ENCODING("VR128", ENCODING_RM)
915 ENCODING("FR64", ENCODING_RM)
916 ENCODING("FR32", ENCODING_RM)
917 ENCODING("VR64", ENCODING_RM)
918 errs() << "Unhandled R/M register encoding " << s << "\n";
919 llvm_unreachable("Unhandled R/M register encoding");
922 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
923 (const std::string &s,
924 bool hasOpSizePrefix) {
925 ENCODING("GR16", ENCODING_REG)
926 ENCODING("GR32", ENCODING_REG)
927 ENCODING("GR64", ENCODING_REG)
928 ENCODING("GR8", ENCODING_REG)
929 ENCODING("VR128", ENCODING_REG)
930 ENCODING("FR64", ENCODING_REG)
931 ENCODING("FR32", ENCODING_REG)
932 ENCODING("VR64", ENCODING_REG)
933 ENCODING("SEGMENT_REG", ENCODING_REG)
934 ENCODING("DEBUG_REG", ENCODING_REG)
935 ENCODING("CONTROL_REG", ENCODING_REG)
936 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
937 llvm_unreachable("Unhandled reg/opcode register encoding");
940 OperandEncoding RecognizableInstr::memoryEncodingFromString
941 (const std::string &s,
942 bool hasOpSizePrefix) {
943 ENCODING("i16mem", ENCODING_RM)
944 ENCODING("i32mem", ENCODING_RM)
945 ENCODING("i64mem", ENCODING_RM)
946 ENCODING("i8mem", ENCODING_RM)
947 ENCODING("ssmem", ENCODING_RM)
948 ENCODING("sdmem", ENCODING_RM)
949 ENCODING("f128mem", ENCODING_RM)
950 ENCODING("f256mem", ENCODING_RM)
951 ENCODING("f64mem", ENCODING_RM)
952 ENCODING("f32mem", ENCODING_RM)
953 ENCODING("i128mem", ENCODING_RM)
954 ENCODING("f80mem", ENCODING_RM)
955 ENCODING("lea32mem", ENCODING_RM)
956 ENCODING("lea64_32mem", ENCODING_RM)
957 ENCODING("lea64mem", ENCODING_RM)
958 ENCODING("opaque32mem", ENCODING_RM)
959 ENCODING("opaque48mem", ENCODING_RM)
960 ENCODING("opaque80mem", ENCODING_RM)
961 ENCODING("opaque512mem", ENCODING_RM)
962 errs() << "Unhandled memory encoding " << s << "\n";
963 llvm_unreachable("Unhandled memory encoding");
966 OperandEncoding RecognizableInstr::relocationEncodingFromString
967 (const std::string &s,
968 bool hasOpSizePrefix) {
969 if(!hasOpSizePrefix) {
970 // For instructions without an OpSize prefix, a declared 16-bit register or
971 // immediate encoding is special.
972 ENCODING("i16imm", ENCODING_IW)
974 ENCODING("i16imm", ENCODING_Iv)
975 ENCODING("i16i8imm", ENCODING_IB)
976 ENCODING("i32imm", ENCODING_Iv)
977 ENCODING("i32i8imm", ENCODING_IB)
978 ENCODING("i64i32imm", ENCODING_ID)
979 ENCODING("i64i8imm", ENCODING_IB)
980 ENCODING("i8imm", ENCODING_IB)
981 ENCODING("i64i32imm_pcrel", ENCODING_ID)
982 ENCODING("i16imm_pcrel", ENCODING_IW)
983 ENCODING("i32imm_pcrel", ENCODING_ID)
984 ENCODING("brtarget", ENCODING_Iv)
985 ENCODING("brtarget8", ENCODING_IB)
986 ENCODING("i64imm", ENCODING_IO)
987 ENCODING("offset8", ENCODING_Ia)
988 ENCODING("offset16", ENCODING_Ia)
989 ENCODING("offset32", ENCODING_Ia)
990 ENCODING("offset64", ENCODING_Ia)
991 errs() << "Unhandled relocation encoding " << s << "\n";
992 llvm_unreachable("Unhandled relocation encoding");
995 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
996 (const std::string &s,
997 bool hasOpSizePrefix) {
998 ENCODING("RST", ENCODING_I)
999 ENCODING("GR32", ENCODING_Rv)
1000 ENCODING("GR64", ENCODING_RO)
1001 ENCODING("GR16", ENCODING_Rv)
1002 ENCODING("GR8", ENCODING_RB)
1003 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1004 llvm_unreachable("Unhandled opcode modifier encoding");