1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
49 // A clone of X86 since we can't depend on something that is generated.
59 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
60 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
61 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
62 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
66 #define MAP(from, to) MRM_##from = to,
75 D8 = 3, D9 = 4, DA = 5, DB = 6,
76 DC = 7, DD = 8, DE = 9, DF = 10,
79 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
83 // If rows are added to the opcode extension tables, then corresponding entries
84 // must be added here.
86 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
87 // that byte to ONE_BYTE_EXTENSION_TABLES.
89 // If the row corresponds to two bytes where the first is 0f, add an entry for
90 // the second byte to TWO_BYTE_EXTENSION_TABLES.
92 // If the row corresponds to some other set of bytes, you will need to modify
93 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
94 // to the X86 TD files, except in two cases: if the first two bytes of such a
95 // new combination are 0f 38 or 0f 3a, you just have to add maps called
96 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
97 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
98 // in RecognizableInstr::emitDecodePath().
100 #define ONE_BYTE_EXTENSION_TABLES \
101 EXTENSION_TABLE(80) \
102 EXTENSION_TABLE(81) \
103 EXTENSION_TABLE(82) \
104 EXTENSION_TABLE(83) \
105 EXTENSION_TABLE(8f) \
106 EXTENSION_TABLE(c0) \
107 EXTENSION_TABLE(c1) \
108 EXTENSION_TABLE(c6) \
109 EXTENSION_TABLE(c7) \
110 EXTENSION_TABLE(d0) \
111 EXTENSION_TABLE(d1) \
112 EXTENSION_TABLE(d2) \
113 EXTENSION_TABLE(d3) \
114 EXTENSION_TABLE(f6) \
115 EXTENSION_TABLE(f7) \
116 EXTENSION_TABLE(fe) \
119 #define TWO_BYTE_EXTENSION_TABLES \
120 EXTENSION_TABLE(00) \
121 EXTENSION_TABLE(01) \
122 EXTENSION_TABLE(18) \
123 EXTENSION_TABLE(71) \
124 EXTENSION_TABLE(72) \
125 EXTENSION_TABLE(73) \
126 EXTENSION_TABLE(ae) \
127 EXTENSION_TABLE(ba) \
130 #define THREE_BYTE_38_EXTENSION_TABLES \
133 using namespace X86Disassembler;
135 /// needsModRMForDecode - Indicates whether a particular instruction requires a
136 /// ModR/M byte for the instruction to be properly decoded. For example, a
137 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
140 /// @param form - The form of the instruction.
141 /// @return - true if the form implies that a ModR/M byte is required, false
143 static bool needsModRMForDecode(uint8_t form) {
144 if (form == X86Local::MRMDestReg ||
145 form == X86Local::MRMDestMem ||
146 form == X86Local::MRMSrcReg ||
147 form == X86Local::MRMSrcMem ||
148 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
149 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
155 /// isRegFormat - Indicates whether a particular form requires the Mod field of
156 /// the ModR/M byte to be 0b11.
158 /// @param form - The form of the instruction.
159 /// @return - true if the form implies that Mod must be 0b11, false
161 static bool isRegFormat(uint8_t form) {
162 if (form == X86Local::MRMDestReg ||
163 form == X86Local::MRMSrcReg ||
164 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
170 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
171 /// Useful for switch statements and the like.
173 /// @param init - A reference to the BitsInit to be decoded.
174 /// @return - The field, with the first bit in the BitsInit as the lowest
176 static uint8_t byteFromBitsInit(BitsInit &init) {
177 int width = init.getNumBits();
179 assert(width <= 8 && "Field is too large for uint8_t!");
186 for (index = 0; index < width; index++) {
187 if (static_cast<BitInit*>(init.getBit(index))->getValue())
196 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
197 /// name of the field.
199 /// @param rec - The record from which to extract the value.
200 /// @param name - The name of the field in the record.
201 /// @return - The field, as translated by byteFromBitsInit().
202 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
203 BitsInit* bits = rec->getValueAsBitsInit(name);
204 return byteFromBitsInit(*bits);
207 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
208 const CodeGenInstruction &insn,
213 Name = Rec->getName();
214 Spec = &tables.specForUID(UID);
216 if (!Rec->isSubClassOf("X86Inst")) {
217 ShouldBeEmitted = false;
221 Prefix = byteFromRec(Rec, "Prefix");
222 Opcode = byteFromRec(Rec, "Opcode");
223 Form = byteFromRec(Rec, "FormBits");
224 SegOvr = byteFromRec(Rec, "SegOvrBits");
226 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
227 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
228 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
229 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
230 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
231 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
232 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
233 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
234 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
235 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
236 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
238 Name = Rec->getName();
239 AsmString = Rec->getValueAsString("AsmString");
241 Operands = &insn.Operands.OperandList;
243 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
244 (Name.find("CRC32") != Name.npos);
245 HasFROperands = hasFROperands();
246 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
248 // Check for 64-bit inst which does not require REX
251 // FIXME: Is there some better way to check for In64BitMode?
252 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
253 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
254 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
258 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
263 // FIXME: These instructions aren't marked as 64-bit in any way
264 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
265 Rec->getName() == "MASKMOVDQU64" ||
266 Rec->getName() == "POPFS64" ||
267 Rec->getName() == "POPGS64" ||
268 Rec->getName() == "PUSHFS64" ||
269 Rec->getName() == "PUSHGS64" ||
270 Rec->getName() == "REX64_PREFIX" ||
271 Rec->getName().find("MOV64") != Name.npos ||
272 Rec->getName().find("PUSH64") != Name.npos ||
273 Rec->getName().find("POP64") != Name.npos;
275 ShouldBeEmitted = true;
278 void RecognizableInstr::processInstr(DisassemblerTables &tables,
279 const CodeGenInstruction &insn,
282 // Ignore "asm parser only" instructions.
283 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
286 RecognizableInstr recogInstr(tables, insn, uid);
288 recogInstr.emitInstructionSpecifier(tables);
290 if (recogInstr.shouldBeEmitted())
291 recogInstr.emitDecodePath(tables);
294 InstructionContext RecognizableInstr::insnContext() const {
295 InstructionContext insnContext;
297 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
298 if (HasVEX_LPrefix && HasVEX_WPrefix) {
300 insnContext = IC_VEX_L_W_OPSIZE;
302 llvm_unreachable("Don't support VEX.L and VEX.W together");
303 } else if (HasOpSizePrefix && HasVEX_LPrefix)
304 insnContext = IC_VEX_L_OPSIZE;
305 else if (HasOpSizePrefix && HasVEX_WPrefix)
306 insnContext = IC_VEX_W_OPSIZE;
307 else if (HasOpSizePrefix)
308 insnContext = IC_VEX_OPSIZE;
309 else if (HasVEX_LPrefix &&
310 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
311 insnContext = IC_VEX_L_XS;
312 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
313 Prefix == X86Local::T8XD ||
314 Prefix == X86Local::TAXD))
315 insnContext = IC_VEX_L_XD;
316 else if (HasVEX_WPrefix &&
317 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
318 insnContext = IC_VEX_W_XS;
319 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
320 Prefix == X86Local::T8XD ||
321 Prefix == X86Local::TAXD))
322 insnContext = IC_VEX_W_XD;
323 else if (HasVEX_WPrefix)
324 insnContext = IC_VEX_W;
325 else if (HasVEX_LPrefix)
326 insnContext = IC_VEX_L;
327 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
328 Prefix == X86Local::TAXD)
329 insnContext = IC_VEX_XD;
330 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
331 insnContext = IC_VEX_XS;
333 insnContext = IC_VEX;
334 } else if (Is64Bit || HasREX_WPrefix) {
335 if (HasREX_WPrefix && HasOpSizePrefix)
336 insnContext = IC_64BIT_REXW_OPSIZE;
337 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
338 Prefix == X86Local::T8XD ||
339 Prefix == X86Local::TAXD))
340 insnContext = IC_64BIT_XD_OPSIZE;
341 else if (HasOpSizePrefix &&
342 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
343 insnContext = IC_64BIT_XS_OPSIZE;
344 else if (HasOpSizePrefix)
345 insnContext = IC_64BIT_OPSIZE;
346 else if (HasAdSizePrefix)
347 insnContext = IC_64BIT_ADSIZE;
348 else if (HasREX_WPrefix &&
349 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
350 insnContext = IC_64BIT_REXW_XS;
351 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
352 Prefix == X86Local::T8XD ||
353 Prefix == X86Local::TAXD))
354 insnContext = IC_64BIT_REXW_XD;
355 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
356 Prefix == X86Local::TAXD)
357 insnContext = IC_64BIT_XD;
358 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
359 insnContext = IC_64BIT_XS;
360 else if (HasREX_WPrefix)
361 insnContext = IC_64BIT_REXW;
363 insnContext = IC_64BIT;
365 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
366 Prefix == X86Local::T8XD ||
367 Prefix == X86Local::TAXD))
368 insnContext = IC_XD_OPSIZE;
369 else if (HasOpSizePrefix &&
370 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
371 insnContext = IC_XS_OPSIZE;
372 else if (HasOpSizePrefix)
373 insnContext = IC_OPSIZE;
374 else if (HasAdSizePrefix)
375 insnContext = IC_ADSIZE;
376 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
377 Prefix == X86Local::TAXD)
379 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
380 Prefix == X86Local::REP)
389 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
394 // Filter out intrinsics
396 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
398 if (Form == X86Local::Pseudo ||
399 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
400 return FILTER_STRONG;
403 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
404 // printed as a separate "instruction".
406 if (Name.find("_Int") != Name.npos ||
407 Name.find("Int_") != Name.npos)
408 return FILTER_STRONG;
410 // Filter out instructions with segment override prefixes.
411 // They're too messy to handle now and we'll special case them if needed.
414 return FILTER_STRONG;
422 // Filter out instructions with a LOCK prefix;
423 // prefer forms that do not have the prefix
427 // Filter out alternate forms of AVX instructions
428 if (Name.find("_alt") != Name.npos ||
429 Name.find("XrYr") != Name.npos ||
430 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
431 Name.find("_64mr") != Name.npos ||
432 Name.find("Xrr") != Name.npos ||
433 Name.find("rr64") != Name.npos)
438 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
440 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
443 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
445 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
447 if (Name.find("Fs") != Name.npos)
449 if (Name == "PUSH64i16" ||
450 Name == "MOVPQI2QImr" ||
451 Name == "VMOVPQI2QImr" ||
452 Name == "MMX_MOVD64rrv164" ||
453 Name == "MOV64ri64i32" ||
454 Name == "VMASKMOVDQU64" ||
455 Name == "VEXTRACTPSrr64" ||
456 Name == "VMOVQd64rr" ||
457 Name == "VMOVQs64rr")
460 if (HasFROperands && Name.find("MOV") != Name.npos &&
461 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
462 (Name.find("to") != Name.npos)))
463 return FILTER_STRONG;
465 return FILTER_NORMAL;
468 bool RecognizableInstr::hasFROperands() const {
469 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
470 unsigned numOperands = OperandList.size();
472 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
473 const std::string &recName = OperandList[operandIndex].Rec->getName();
475 if (recName.find("FR") != recName.npos)
481 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
482 unsigned &physicalOperandIndex,
483 unsigned &numPhysicalOperands,
484 const unsigned *operandMapping,
485 OperandEncoding (*encodingFromString)
487 bool hasOpSizePrefix)) {
489 if (physicalOperandIndex >= numPhysicalOperands)
492 assert(physicalOperandIndex < numPhysicalOperands);
495 while (operandMapping[operandIndex] != operandIndex) {
496 Spec->operands[operandIndex].encoding = ENCODING_DUP;
497 Spec->operands[operandIndex].type =
498 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
502 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
504 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
506 Spec->operands[operandIndex].type = typeFromString(typeName,
512 ++physicalOperandIndex;
515 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
518 if (!ShouldBeEmitted)
523 Spec->filtered = true;
526 ShouldBeEmitted = false;
532 Spec->insnContext = insnContext();
534 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
536 unsigned numOperands = OperandList.size();
537 unsigned numPhysicalOperands = 0;
539 // operandMapping maps from operands in OperandList to their originals.
540 // If operandMapping[i] != i, then the entry is a duplicate.
541 unsigned operandMapping[X86_MAX_OPERANDS];
542 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
544 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
545 if (OperandList[operandIndex].Constraints.size()) {
546 const CGIOperandList::ConstraintInfo &Constraint =
547 OperandList[operandIndex].Constraints[0];
548 if (Constraint.isTied()) {
549 operandMapping[operandIndex] = operandIndex;
550 operandMapping[Constraint.getTiedOperand()] = operandIndex;
552 ++numPhysicalOperands;
553 operandMapping[operandIndex] = operandIndex;
556 ++numPhysicalOperands;
557 operandMapping[operandIndex] = operandIndex;
561 #define HANDLE_OPERAND(class) \
562 handleOperand(false, \
564 physicalOperandIndex, \
565 numPhysicalOperands, \
567 class##EncodingFromString);
569 #define HANDLE_OPTIONAL(class) \
570 handleOperand(true, \
572 physicalOperandIndex, \
573 numPhysicalOperands, \
575 class##EncodingFromString);
577 // operandIndex should always be < numOperands
578 unsigned operandIndex = 0;
579 // physicalOperandIndex should always be < numPhysicalOperands
580 unsigned physicalOperandIndex = 0;
583 case X86Local::RawFrm:
584 // Operand 1 (optional) is an address or immediate.
585 // Operand 2 (optional) is an immediate.
586 assert(numPhysicalOperands <= 2 &&
587 "Unexpected number of operands for RawFrm");
588 HANDLE_OPTIONAL(relocation)
589 HANDLE_OPTIONAL(immediate)
591 case X86Local::AddRegFrm:
592 // Operand 1 is added to the opcode.
593 // Operand 2 (optional) is an address.
594 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
595 "Unexpected number of operands for AddRegFrm");
596 HANDLE_OPERAND(opcodeModifier)
597 HANDLE_OPTIONAL(relocation)
599 case X86Local::MRMDestReg:
600 // Operand 1 is a register operand in the R/M field.
601 // Operand 2 is a register operand in the Reg/Opcode field.
602 // - In AVX, there is a register operand in the VEX.vvvv field here -
603 // Operand 3 (optional) is an immediate.
605 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
606 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
608 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
609 "Unexpected number of operands for MRMDestRegFrm");
611 HANDLE_OPERAND(rmRegister)
614 // FIXME: In AVX, the register below becomes the one encoded
615 // in ModRMVEX and the one above the one in the VEX.VVVV field
616 HANDLE_OPERAND(vvvvRegister)
618 HANDLE_OPERAND(roRegister)
619 HANDLE_OPTIONAL(immediate)
621 case X86Local::MRMDestMem:
622 // Operand 1 is a memory operand (possibly SIB-extended)
623 // Operand 2 is a register operand in the Reg/Opcode field.
624 // - In AVX, there is a register operand in the VEX.vvvv field here -
625 // Operand 3 (optional) is an immediate.
627 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
628 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
630 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
631 "Unexpected number of operands for MRMDestMemFrm");
632 HANDLE_OPERAND(memory)
635 // FIXME: In AVX, the register below becomes the one encoded
636 // in ModRMVEX and the one above the one in the VEX.VVVV field
637 HANDLE_OPERAND(vvvvRegister)
639 HANDLE_OPERAND(roRegister)
640 HANDLE_OPTIONAL(immediate)
642 case X86Local::MRMSrcReg:
643 // Operand 1 is a register operand in the Reg/Opcode field.
644 // Operand 2 is a register operand in the R/M field.
645 // - In AVX, there is a register operand in the VEX.vvvv field here -
646 // Operand 3 (optional) is an immediate.
647 // Operand 4 (optional) is an immediate.
649 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
650 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
651 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
653 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
654 "Unexpected number of operands for MRMSrcRegFrm");
656 HANDLE_OPERAND(roRegister)
659 // FIXME: In AVX, the register below becomes the one encoded
660 // in ModRMVEX and the one above the one in the VEX.VVVV field
661 HANDLE_OPERAND(vvvvRegister)
664 HANDLE_OPERAND(immediate)
666 HANDLE_OPERAND(rmRegister)
668 if (HasVEX_4VOp3Prefix)
669 HANDLE_OPERAND(vvvvRegister)
671 if (!HasMemOp4Prefix)
672 HANDLE_OPTIONAL(immediate)
673 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
674 HANDLE_OPTIONAL(immediate)
676 case X86Local::MRMSrcMem:
677 // Operand 1 is a register operand in the Reg/Opcode field.
678 // Operand 2 is a memory operand (possibly SIB-extended)
679 // - In AVX, there is a register operand in the VEX.vvvv field here -
680 // Operand 3 (optional) is an immediate.
682 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
683 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
684 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
686 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
687 "Unexpected number of operands for MRMSrcMemFrm");
689 HANDLE_OPERAND(roRegister)
692 // FIXME: In AVX, the register below becomes the one encoded
693 // in ModRMVEX and the one above the one in the VEX.VVVV field
694 HANDLE_OPERAND(vvvvRegister)
697 HANDLE_OPERAND(immediate)
699 HANDLE_OPERAND(memory)
701 if (HasVEX_4VOp3Prefix)
702 HANDLE_OPERAND(vvvvRegister)
704 if (!HasMemOp4Prefix)
705 HANDLE_OPTIONAL(immediate)
706 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
708 case X86Local::MRM0r:
709 case X86Local::MRM1r:
710 case X86Local::MRM2r:
711 case X86Local::MRM3r:
712 case X86Local::MRM4r:
713 case X86Local::MRM5r:
714 case X86Local::MRM6r:
715 case X86Local::MRM7r:
716 // Operand 1 is a register operand in the R/M field.
717 // Operand 2 (optional) is an immediate or relocation.
718 // Operand 3 (optional) is an immediate.
720 assert(numPhysicalOperands <= 3 &&
721 "Unexpected number of operands for MRMnRFrm with VEX_4V");
723 assert(numPhysicalOperands <= 3 &&
724 "Unexpected number of operands for MRMnRFrm");
726 HANDLE_OPERAND(vvvvRegister)
727 HANDLE_OPTIONAL(rmRegister)
728 HANDLE_OPTIONAL(relocation)
729 HANDLE_OPTIONAL(immediate)
731 case X86Local::MRM0m:
732 case X86Local::MRM1m:
733 case X86Local::MRM2m:
734 case X86Local::MRM3m:
735 case X86Local::MRM4m:
736 case X86Local::MRM5m:
737 case X86Local::MRM6m:
738 case X86Local::MRM7m:
739 // Operand 1 is a memory operand (possibly SIB-extended)
740 // Operand 2 (optional) is an immediate or relocation.
742 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
743 "Unexpected number of operands for MRMnMFrm");
745 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
746 "Unexpected number of operands for MRMnMFrm");
748 HANDLE_OPERAND(vvvvRegister)
749 HANDLE_OPERAND(memory)
750 HANDLE_OPTIONAL(relocation)
752 case X86Local::RawFrmImm8:
753 // operand 1 is a 16-bit immediate
754 // operand 2 is an 8-bit immediate
755 assert(numPhysicalOperands == 2 &&
756 "Unexpected number of operands for X86Local::RawFrmImm8");
757 HANDLE_OPERAND(immediate)
758 HANDLE_OPERAND(immediate)
760 case X86Local::RawFrmImm16:
761 // operand 1 is a 16-bit immediate
762 // operand 2 is a 16-bit immediate
763 HANDLE_OPERAND(immediate)
764 HANDLE_OPERAND(immediate)
766 case X86Local::MRMInitReg:
771 #undef HANDLE_OPERAND
772 #undef HANDLE_OPTIONAL
775 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
776 // Special cases where the LLVM tables are not complete
778 #define MAP(from, to) \
779 case X86Local::MRM_##from: \
780 filter = new ExactFilter(0x##from); \
783 OpcodeType opcodeType = (OpcodeType)-1;
785 ModRMFilter* filter = NULL;
786 uint8_t opcodeToSet = 0;
789 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
793 opcodeType = TWOBYTE;
797 if (needsModRMForDecode(Form))
798 filter = new ModFilter(isRegFormat(Form));
800 filter = new DumbFilter();
802 #define EXTENSION_TABLE(n) case 0x##n:
803 TWO_BYTE_EXTENSION_TABLES
804 #undef EXTENSION_TABLE
807 llvm_unreachable("Unhandled two-byte extended opcode");
808 case X86Local::MRM0r:
809 case X86Local::MRM1r:
810 case X86Local::MRM2r:
811 case X86Local::MRM3r:
812 case X86Local::MRM4r:
813 case X86Local::MRM5r:
814 case X86Local::MRM6r:
815 case X86Local::MRM7r:
816 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
818 case X86Local::MRM0m:
819 case X86Local::MRM1m:
820 case X86Local::MRM2m:
821 case X86Local::MRM3m:
822 case X86Local::MRM4m:
823 case X86Local::MRM5m:
824 case X86Local::MRM6m:
825 case X86Local::MRM7m:
826 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
832 opcodeToSet = Opcode;
837 opcodeType = THREEBYTE_38;
840 if (needsModRMForDecode(Form))
841 filter = new ModFilter(isRegFormat(Form));
843 filter = new DumbFilter();
845 #define EXTENSION_TABLE(n) case 0x##n:
846 THREE_BYTE_38_EXTENSION_TABLES
847 #undef EXTENSION_TABLE
850 llvm_unreachable("Unhandled two-byte extended opcode");
851 case X86Local::MRM0r:
852 case X86Local::MRM1r:
853 case X86Local::MRM2r:
854 case X86Local::MRM3r:
855 case X86Local::MRM4r:
856 case X86Local::MRM5r:
857 case X86Local::MRM6r:
858 case X86Local::MRM7r:
859 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
861 case X86Local::MRM0m:
862 case X86Local::MRM1m:
863 case X86Local::MRM2m:
864 case X86Local::MRM3m:
865 case X86Local::MRM4m:
866 case X86Local::MRM5m:
867 case X86Local::MRM6m:
868 case X86Local::MRM7m:
869 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
875 opcodeToSet = Opcode;
879 opcodeType = THREEBYTE_3A;
880 if (needsModRMForDecode(Form))
881 filter = new ModFilter(isRegFormat(Form));
883 filter = new DumbFilter();
884 opcodeToSet = Opcode;
887 opcodeType = THREEBYTE_A6;
888 if (needsModRMForDecode(Form))
889 filter = new ModFilter(isRegFormat(Form));
891 filter = new DumbFilter();
892 opcodeToSet = Opcode;
895 opcodeType = THREEBYTE_A7;
896 if (needsModRMForDecode(Form))
897 filter = new ModFilter(isRegFormat(Form));
899 filter = new DumbFilter();
900 opcodeToSet = Opcode;
910 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
911 opcodeType = ONEBYTE;
912 if (Form == X86Local::AddRegFrm) {
913 Spec->modifierType = MODIFIER_MODRM;
914 Spec->modifierBase = Opcode;
915 filter = new AddRegEscapeFilter(Opcode);
917 filter = new EscapeFilter(true, Opcode);
919 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
923 opcodeType = ONEBYTE;
925 #define EXTENSION_TABLE(n) case 0x##n:
926 ONE_BYTE_EXTENSION_TABLES
927 #undef EXTENSION_TABLE
930 llvm_unreachable("Fell through the cracks of a single-byte "
932 case X86Local::MRM0r:
933 case X86Local::MRM1r:
934 case X86Local::MRM2r:
935 case X86Local::MRM3r:
936 case X86Local::MRM4r:
937 case X86Local::MRM5r:
938 case X86Local::MRM6r:
939 case X86Local::MRM7r:
940 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
942 case X86Local::MRM0m:
943 case X86Local::MRM1m:
944 case X86Local::MRM2m:
945 case X86Local::MRM3m:
946 case X86Local::MRM4m:
947 case X86Local::MRM5m:
948 case X86Local::MRM6m:
949 case X86Local::MRM7m:
950 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
963 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
966 if (needsModRMForDecode(Form))
967 filter = new ModFilter(isRegFormat(Form));
969 filter = new DumbFilter();
972 opcodeToSet = Opcode;
975 assert(opcodeType != (OpcodeType)-1 &&
976 "Opcode type not set");
977 assert(filter && "Filter not set");
979 if (Form == X86Local::AddRegFrm) {
980 if(Spec->modifierType != MODIFIER_MODRM) {
981 assert(opcodeToSet < 0xf9 &&
982 "Not enough room for all ADDREG_FRM operands");
984 uint8_t currentOpcode;
986 for (currentOpcode = opcodeToSet;
987 currentOpcode < opcodeToSet + 8;
989 tables.setTableFields(opcodeType,
993 UID, Is32Bit, IgnoresVEX_L);
995 Spec->modifierType = MODIFIER_OPCODE;
996 Spec->modifierBase = opcodeToSet;
998 // modifierBase was set where MODIFIER_MODRM was set
999 tables.setTableFields(opcodeType,
1003 UID, Is32Bit, IgnoresVEX_L);
1006 tables.setTableFields(opcodeType,
1010 UID, Is32Bit, IgnoresVEX_L);
1012 Spec->modifierType = MODIFIER_NONE;
1013 Spec->modifierBase = opcodeToSet;
1021 #define TYPE(str, type) if (s == str) return type;
1022 OperandType RecognizableInstr::typeFromString(const std::string &s,
1024 bool hasREX_WPrefix,
1025 bool hasOpSizePrefix) {
1027 // For SSE instructions, we ignore the OpSize prefix and force operand
1029 TYPE("GR16", TYPE_R16)
1030 TYPE("GR32", TYPE_R32)
1031 TYPE("GR64", TYPE_R64)
1033 if(hasREX_WPrefix) {
1034 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1036 TYPE("GR32", TYPE_R32)
1038 if(!hasOpSizePrefix) {
1039 // For instructions without an OpSize prefix, a declared 16-bit register or
1040 // immediate encoding is special.
1041 TYPE("GR16", TYPE_R16)
1042 TYPE("i16imm", TYPE_IMM16)
1044 TYPE("i16mem", TYPE_Mv)
1045 TYPE("i16imm", TYPE_IMMv)
1046 TYPE("i16i8imm", TYPE_IMMv)
1047 TYPE("GR16", TYPE_Rv)
1048 TYPE("i32mem", TYPE_Mv)
1049 TYPE("i32imm", TYPE_IMMv)
1050 TYPE("i32i8imm", TYPE_IMM32)
1051 TYPE("u32u8imm", TYPE_IMM32)
1052 TYPE("GR32", TYPE_Rv)
1053 TYPE("i64mem", TYPE_Mv)
1054 TYPE("i64i32imm", TYPE_IMM64)
1055 TYPE("i64i8imm", TYPE_IMM64)
1056 TYPE("GR64", TYPE_R64)
1057 TYPE("i8mem", TYPE_M8)
1058 TYPE("i8imm", TYPE_IMM8)
1059 TYPE("GR8", TYPE_R8)
1060 TYPE("VR128", TYPE_XMM128)
1061 TYPE("f128mem", TYPE_M128)
1062 TYPE("f256mem", TYPE_M256)
1063 TYPE("FR64", TYPE_XMM64)
1064 TYPE("f64mem", TYPE_M64FP)
1065 TYPE("sdmem", TYPE_M64FP)
1066 TYPE("FR32", TYPE_XMM32)
1067 TYPE("f32mem", TYPE_M32FP)
1068 TYPE("ssmem", TYPE_M32FP)
1069 TYPE("RST", TYPE_ST)
1070 TYPE("i128mem", TYPE_M128)
1071 TYPE("i256mem", TYPE_M256)
1072 TYPE("i64i32imm_pcrel", TYPE_REL64)
1073 TYPE("i16imm_pcrel", TYPE_REL16)
1074 TYPE("i32imm_pcrel", TYPE_REL32)
1075 TYPE("SSECC", TYPE_IMM3)
1076 TYPE("AVXCC", TYPE_IMM5)
1077 TYPE("brtarget", TYPE_RELv)
1078 TYPE("uncondbrtarget", TYPE_RELv)
1079 TYPE("brtarget8", TYPE_REL8)
1080 TYPE("f80mem", TYPE_M80FP)
1081 TYPE("lea32mem", TYPE_LEA)
1082 TYPE("lea64_32mem", TYPE_LEA)
1083 TYPE("lea64mem", TYPE_LEA)
1084 TYPE("VR64", TYPE_MM64)
1085 TYPE("i64imm", TYPE_IMMv)
1086 TYPE("opaque32mem", TYPE_M1616)
1087 TYPE("opaque48mem", TYPE_M1632)
1088 TYPE("opaque80mem", TYPE_M1664)
1089 TYPE("opaque512mem", TYPE_M512)
1090 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1091 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1092 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1093 TYPE("offset8", TYPE_MOFFS8)
1094 TYPE("offset16", TYPE_MOFFS16)
1095 TYPE("offset32", TYPE_MOFFS32)
1096 TYPE("offset64", TYPE_MOFFS64)
1097 TYPE("VR256", TYPE_XMM256)
1098 TYPE("GR16_NOAX", TYPE_Rv)
1099 TYPE("GR32_NOAX", TYPE_Rv)
1100 TYPE("GR64_NOAX", TYPE_R64)
1101 TYPE("vx32mem", TYPE_M32)
1102 TYPE("vy32mem", TYPE_M32)
1103 TYPE("vx64mem", TYPE_M64)
1104 TYPE("vy64mem", TYPE_M64)
1105 errs() << "Unhandled type string " << s << "\n";
1106 llvm_unreachable("Unhandled type string");
1110 #define ENCODING(str, encoding) if (s == str) return encoding;
1111 OperandEncoding RecognizableInstr::immediateEncodingFromString
1112 (const std::string &s,
1113 bool hasOpSizePrefix) {
1114 if(!hasOpSizePrefix) {
1115 // For instructions without an OpSize prefix, a declared 16-bit register or
1116 // immediate encoding is special.
1117 ENCODING("i16imm", ENCODING_IW)
1119 ENCODING("i32i8imm", ENCODING_IB)
1120 ENCODING("u32u8imm", ENCODING_IB)
1121 ENCODING("SSECC", ENCODING_IB)
1122 ENCODING("AVXCC", ENCODING_IB)
1123 ENCODING("i16imm", ENCODING_Iv)
1124 ENCODING("i16i8imm", ENCODING_IB)
1125 ENCODING("i32imm", ENCODING_Iv)
1126 ENCODING("i64i32imm", ENCODING_ID)
1127 ENCODING("i64i8imm", ENCODING_IB)
1128 ENCODING("i8imm", ENCODING_IB)
1129 // This is not a typo. Instructions like BLENDVPD put
1130 // register IDs in 8-bit immediates nowadays.
1131 ENCODING("VR256", ENCODING_IB)
1132 ENCODING("VR128", ENCODING_IB)
1133 ENCODING("FR32", ENCODING_IB)
1134 ENCODING("FR64", ENCODING_IB)
1135 errs() << "Unhandled immediate encoding " << s << "\n";
1136 llvm_unreachable("Unhandled immediate encoding");
1139 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1140 (const std::string &s,
1141 bool hasOpSizePrefix) {
1142 ENCODING("GR16", ENCODING_RM)
1143 ENCODING("GR32", ENCODING_RM)
1144 ENCODING("GR64", ENCODING_RM)
1145 ENCODING("GR8", ENCODING_RM)
1146 ENCODING("VR128", ENCODING_RM)
1147 ENCODING("FR64", ENCODING_RM)
1148 ENCODING("FR32", ENCODING_RM)
1149 ENCODING("VR64", ENCODING_RM)
1150 ENCODING("VR256", ENCODING_RM)
1151 errs() << "Unhandled R/M register encoding " << s << "\n";
1152 llvm_unreachable("Unhandled R/M register encoding");
1155 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1156 (const std::string &s,
1157 bool hasOpSizePrefix) {
1158 ENCODING("GR16", ENCODING_REG)
1159 ENCODING("GR32", ENCODING_REG)
1160 ENCODING("GR64", ENCODING_REG)
1161 ENCODING("GR8", ENCODING_REG)
1162 ENCODING("VR128", ENCODING_REG)
1163 ENCODING("FR64", ENCODING_REG)
1164 ENCODING("FR32", ENCODING_REG)
1165 ENCODING("VR64", ENCODING_REG)
1166 ENCODING("SEGMENT_REG", ENCODING_REG)
1167 ENCODING("DEBUG_REG", ENCODING_REG)
1168 ENCODING("CONTROL_REG", ENCODING_REG)
1169 ENCODING("VR256", ENCODING_REG)
1170 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1171 llvm_unreachable("Unhandled reg/opcode register encoding");
1174 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1175 (const std::string &s,
1176 bool hasOpSizePrefix) {
1177 ENCODING("GR32", ENCODING_VVVV)
1178 ENCODING("GR64", ENCODING_VVVV)
1179 ENCODING("FR32", ENCODING_VVVV)
1180 ENCODING("FR64", ENCODING_VVVV)
1181 ENCODING("VR128", ENCODING_VVVV)
1182 ENCODING("VR256", ENCODING_VVVV)
1183 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1184 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1187 OperandEncoding RecognizableInstr::memoryEncodingFromString
1188 (const std::string &s,
1189 bool hasOpSizePrefix) {
1190 ENCODING("i16mem", ENCODING_RM)
1191 ENCODING("i32mem", ENCODING_RM)
1192 ENCODING("i64mem", ENCODING_RM)
1193 ENCODING("i8mem", ENCODING_RM)
1194 ENCODING("ssmem", ENCODING_RM)
1195 ENCODING("sdmem", ENCODING_RM)
1196 ENCODING("f128mem", ENCODING_RM)
1197 ENCODING("f256mem", ENCODING_RM)
1198 ENCODING("f64mem", ENCODING_RM)
1199 ENCODING("f32mem", ENCODING_RM)
1200 ENCODING("i128mem", ENCODING_RM)
1201 ENCODING("i256mem", ENCODING_RM)
1202 ENCODING("f80mem", ENCODING_RM)
1203 ENCODING("lea32mem", ENCODING_RM)
1204 ENCODING("lea64_32mem", ENCODING_RM)
1205 ENCODING("lea64mem", ENCODING_RM)
1206 ENCODING("opaque32mem", ENCODING_RM)
1207 ENCODING("opaque48mem", ENCODING_RM)
1208 ENCODING("opaque80mem", ENCODING_RM)
1209 ENCODING("opaque512mem", ENCODING_RM)
1210 ENCODING("vx32mem", ENCODING_RM)
1211 ENCODING("vy32mem", ENCODING_RM)
1212 ENCODING("vx64mem", ENCODING_RM)
1213 ENCODING("vy64mem", ENCODING_RM)
1214 errs() << "Unhandled memory encoding " << s << "\n";
1215 llvm_unreachable("Unhandled memory encoding");
1218 OperandEncoding RecognizableInstr::relocationEncodingFromString
1219 (const std::string &s,
1220 bool hasOpSizePrefix) {
1221 if(!hasOpSizePrefix) {
1222 // For instructions without an OpSize prefix, a declared 16-bit register or
1223 // immediate encoding is special.
1224 ENCODING("i16imm", ENCODING_IW)
1226 ENCODING("i16imm", ENCODING_Iv)
1227 ENCODING("i16i8imm", ENCODING_IB)
1228 ENCODING("i32imm", ENCODING_Iv)
1229 ENCODING("i32i8imm", ENCODING_IB)
1230 ENCODING("i64i32imm", ENCODING_ID)
1231 ENCODING("i64i8imm", ENCODING_IB)
1232 ENCODING("i8imm", ENCODING_IB)
1233 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1234 ENCODING("i16imm_pcrel", ENCODING_IW)
1235 ENCODING("i32imm_pcrel", ENCODING_ID)
1236 ENCODING("brtarget", ENCODING_Iv)
1237 ENCODING("brtarget8", ENCODING_IB)
1238 ENCODING("i64imm", ENCODING_IO)
1239 ENCODING("offset8", ENCODING_Ia)
1240 ENCODING("offset16", ENCODING_Ia)
1241 ENCODING("offset32", ENCODING_Ia)
1242 ENCODING("offset64", ENCODING_Ia)
1243 errs() << "Unhandled relocation encoding " << s << "\n";
1244 llvm_unreachable("Unhandled relocation encoding");
1247 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1248 (const std::string &s,
1249 bool hasOpSizePrefix) {
1250 ENCODING("RST", ENCODING_I)
1251 ENCODING("GR32", ENCODING_Rv)
1252 ENCODING("GR64", ENCODING_RO)
1253 ENCODING("GR16", ENCODING_Rv)
1254 ENCODING("GR8", ENCODING_RB)
1255 ENCODING("GR16_NOAX", ENCODING_Rv)
1256 ENCODING("GR32_NOAX", ENCODING_Rv)
1257 ENCODING("GR64_NOAX", ENCODING_RO)
1258 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1259 llvm_unreachable("Unhandled opcode modifier encoding");