1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19,
83 XOP8 = 20, XOP9 = 21, XOPA = 22
87 // If rows are added to the opcode extension tables, then corresponding entries
88 // must be added here.
90 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
91 // that byte to ONE_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to two bytes where the first is 0f, add an entry for
94 // the second byte to TWO_BYTE_EXTENSION_TABLES.
96 // If the row corresponds to some other set of bytes, you will need to modify
97 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
98 // to the X86 TD files, except in two cases: if the first two bytes of such a
99 // new combination are 0f 38 or 0f 3a, you just have to add maps called
100 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
101 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
102 // in RecognizableInstr::emitDecodePath().
104 #define ONE_BYTE_EXTENSION_TABLES \
105 EXTENSION_TABLE(80) \
106 EXTENSION_TABLE(81) \
107 EXTENSION_TABLE(82) \
108 EXTENSION_TABLE(83) \
109 EXTENSION_TABLE(8f) \
110 EXTENSION_TABLE(c0) \
111 EXTENSION_TABLE(c1) \
112 EXTENSION_TABLE(c6) \
113 EXTENSION_TABLE(c7) \
114 EXTENSION_TABLE(d0) \
115 EXTENSION_TABLE(d1) \
116 EXTENSION_TABLE(d2) \
117 EXTENSION_TABLE(d3) \
118 EXTENSION_TABLE(f6) \
119 EXTENSION_TABLE(f7) \
120 EXTENSION_TABLE(fe) \
123 #define TWO_BYTE_EXTENSION_TABLES \
124 EXTENSION_TABLE(00) \
125 EXTENSION_TABLE(01) \
126 EXTENSION_TABLE(0d) \
127 EXTENSION_TABLE(18) \
128 EXTENSION_TABLE(71) \
129 EXTENSION_TABLE(72) \
130 EXTENSION_TABLE(73) \
131 EXTENSION_TABLE(ae) \
132 EXTENSION_TABLE(ba) \
135 #define THREE_BYTE_38_EXTENSION_TABLES \
138 #define XOP9_MAP_EXTENSION_TABLES \
139 EXTENSION_TABLE(01) \
142 using namespace X86Disassembler;
144 /// needsModRMForDecode - Indicates whether a particular instruction requires a
145 /// ModR/M byte for the instruction to be properly decoded. For example, a
146 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
149 /// @param form - The form of the instruction.
150 /// @return - true if the form implies that a ModR/M byte is required, false
152 static bool needsModRMForDecode(uint8_t form) {
153 if (form == X86Local::MRMDestReg ||
154 form == X86Local::MRMDestMem ||
155 form == X86Local::MRMSrcReg ||
156 form == X86Local::MRMSrcMem ||
157 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
158 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
164 /// isRegFormat - Indicates whether a particular form requires the Mod field of
165 /// the ModR/M byte to be 0b11.
167 /// @param form - The form of the instruction.
168 /// @return - true if the form implies that Mod must be 0b11, false
170 static bool isRegFormat(uint8_t form) {
171 if (form == X86Local::MRMDestReg ||
172 form == X86Local::MRMSrcReg ||
173 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
179 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
180 /// Useful for switch statements and the like.
182 /// @param init - A reference to the BitsInit to be decoded.
183 /// @return - The field, with the first bit in the BitsInit as the lowest
185 static uint8_t byteFromBitsInit(BitsInit &init) {
186 int width = init.getNumBits();
188 assert(width <= 8 && "Field is too large for uint8_t!");
195 for (index = 0; index < width; index++) {
196 if (static_cast<BitInit*>(init.getBit(index))->getValue())
205 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
206 /// name of the field.
208 /// @param rec - The record from which to extract the value.
209 /// @param name - The name of the field in the record.
210 /// @return - The field, as translated by byteFromBitsInit().
211 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
212 BitsInit* bits = rec->getValueAsBitsInit(name);
213 return byteFromBitsInit(*bits);
216 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
217 const CodeGenInstruction &insn,
222 Name = Rec->getName();
223 Spec = &tables.specForUID(UID);
225 if (!Rec->isSubClassOf("X86Inst")) {
226 ShouldBeEmitted = false;
230 Prefix = byteFromRec(Rec, "Prefix");
231 Opcode = byteFromRec(Rec, "Opcode");
232 Form = byteFromRec(Rec, "FormBits");
233 SegOvr = byteFromRec(Rec, "SegOvrBits");
235 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
236 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
237 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
238 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
239 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
240 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
241 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
242 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
243 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
244 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
245 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
246 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
247 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
248 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
249 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
251 Name = Rec->getName();
252 AsmString = Rec->getValueAsString("AsmString");
254 Operands = &insn.Operands.OperandList;
256 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
257 (Name.find("CRC32") != Name.npos);
258 HasFROperands = hasFROperands();
259 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
261 // Check for 64-bit inst which does not require REX
264 // FIXME: Is there some better way to check for In64BitMode?
265 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
266 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
267 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
271 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
276 // FIXME: These instructions aren't marked as 64-bit in any way
277 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
278 Rec->getName() == "MASKMOVDQU64" ||
279 Rec->getName() == "POPFS64" ||
280 Rec->getName() == "POPGS64" ||
281 Rec->getName() == "PUSHFS64" ||
282 Rec->getName() == "PUSHGS64" ||
283 Rec->getName() == "REX64_PREFIX" ||
284 Rec->getName().find("MOV64") != Name.npos ||
285 Rec->getName().find("PUSH64") != Name.npos ||
286 Rec->getName().find("POP64") != Name.npos;
288 ShouldBeEmitted = true;
291 void RecognizableInstr::processInstr(DisassemblerTables &tables,
292 const CodeGenInstruction &insn,
295 // Ignore "asm parser only" instructions.
296 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
299 RecognizableInstr recogInstr(tables, insn, uid);
301 recogInstr.emitInstructionSpecifier(tables);
303 if (recogInstr.shouldBeEmitted())
304 recogInstr.emitDecodePath(tables);
307 #define EVEX_KB(n) (HasEVEX_K && HasEVEX_B? n##_K_B : \
308 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))
310 InstructionContext RecognizableInstr::insnContext() const {
311 InstructionContext insnContext;
314 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
315 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
316 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
319 if (HasVEX_LPrefix && HasVEX_WPrefix) {
321 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
322 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
323 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
324 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
325 Prefix == X86Local::TAXD)
326 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
328 insnContext = EVEX_KB(IC_EVEX_L_W);
329 } else if (HasVEX_LPrefix) {
332 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
333 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
334 insnContext = EVEX_KB(IC_EVEX_L_XS);
335 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
336 Prefix == X86Local::TAXD)
337 insnContext = EVEX_KB(IC_EVEX_L_XD);
339 insnContext = EVEX_KB(IC_EVEX_L);
341 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
344 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
345 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
346 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
347 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
348 Prefix == X86Local::TAXD)
349 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
351 insnContext = EVEX_KB(IC_EVEX_L2_W);
352 } else if (HasEVEX_L2Prefix) {
355 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
356 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
357 Prefix == X86Local::TAXD)
358 insnContext = EVEX_KB(IC_EVEX_L2_XD);
359 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
360 insnContext = EVEX_KB(IC_EVEX_L2_XS);
362 insnContext = EVEX_KB(IC_EVEX_L2);
364 else if (HasVEX_WPrefix) {
367 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
368 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
369 insnContext = EVEX_KB(IC_EVEX_W_XS);
370 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
371 Prefix == X86Local::TAXD)
372 insnContext = EVEX_KB(IC_EVEX_W_XD);
374 insnContext = EVEX_KB(IC_EVEX_W);
377 else if (HasOpSizePrefix)
378 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
379 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
380 Prefix == X86Local::TAXD)
381 insnContext = EVEX_KB(IC_EVEX_XD);
382 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
383 insnContext = EVEX_KB(IC_EVEX_XS);
385 insnContext = EVEX_KB(IC_EVEX);
387 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
388 if (HasVEX_LPrefix && HasVEX_WPrefix) {
390 insnContext = IC_VEX_L_W_OPSIZE;
391 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
392 insnContext = IC_VEX_L_W_XS;
393 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
394 Prefix == X86Local::TAXD)
395 insnContext = IC_VEX_L_W_XD;
397 insnContext = IC_VEX_L_W;
398 } else if (HasOpSizePrefix && HasVEX_LPrefix)
399 insnContext = IC_VEX_L_OPSIZE;
400 else if (HasOpSizePrefix && HasVEX_WPrefix)
401 insnContext = IC_VEX_W_OPSIZE;
402 else if (HasOpSizePrefix)
403 insnContext = IC_VEX_OPSIZE;
404 else if (HasVEX_LPrefix &&
405 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
406 insnContext = IC_VEX_L_XS;
407 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
408 Prefix == X86Local::T8XD ||
409 Prefix == X86Local::TAXD))
410 insnContext = IC_VEX_L_XD;
411 else if (HasVEX_WPrefix &&
412 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
413 insnContext = IC_VEX_W_XS;
414 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
415 Prefix == X86Local::T8XD ||
416 Prefix == X86Local::TAXD))
417 insnContext = IC_VEX_W_XD;
418 else if (HasVEX_WPrefix)
419 insnContext = IC_VEX_W;
420 else if (HasVEX_LPrefix)
421 insnContext = IC_VEX_L;
422 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
423 Prefix == X86Local::TAXD)
424 insnContext = IC_VEX_XD;
425 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
426 insnContext = IC_VEX_XS;
428 insnContext = IC_VEX;
429 } else if (Is64Bit || HasREX_WPrefix) {
430 if (HasREX_WPrefix && HasOpSizePrefix)
431 insnContext = IC_64BIT_REXW_OPSIZE;
432 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
433 Prefix == X86Local::T8XD ||
434 Prefix == X86Local::TAXD))
435 insnContext = IC_64BIT_XD_OPSIZE;
436 else if (HasOpSizePrefix &&
437 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
438 insnContext = IC_64BIT_XS_OPSIZE;
439 else if (HasOpSizePrefix)
440 insnContext = IC_64BIT_OPSIZE;
441 else if (HasAdSizePrefix)
442 insnContext = IC_64BIT_ADSIZE;
443 else if (HasREX_WPrefix &&
444 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
445 insnContext = IC_64BIT_REXW_XS;
446 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
447 Prefix == X86Local::T8XD ||
448 Prefix == X86Local::TAXD))
449 insnContext = IC_64BIT_REXW_XD;
450 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
451 Prefix == X86Local::TAXD)
452 insnContext = IC_64BIT_XD;
453 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
454 insnContext = IC_64BIT_XS;
455 else if (HasREX_WPrefix)
456 insnContext = IC_64BIT_REXW;
458 insnContext = IC_64BIT;
460 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
461 Prefix == X86Local::T8XD ||
462 Prefix == X86Local::TAXD))
463 insnContext = IC_XD_OPSIZE;
464 else if (HasOpSizePrefix &&
465 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
466 insnContext = IC_XS_OPSIZE;
467 else if (HasOpSizePrefix)
468 insnContext = IC_OPSIZE;
469 else if (HasAdSizePrefix)
470 insnContext = IC_ADSIZE;
471 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
472 Prefix == X86Local::TAXD)
474 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
475 Prefix == X86Local::REP)
484 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
489 // Filter out intrinsics
491 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
493 if (Form == X86Local::Pseudo ||
494 (IsCodeGenOnly && Name.find("_REV") == Name.npos &&
495 Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos))
496 return FILTER_STRONG;
499 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
500 // printed as a separate "instruction".
502 if (Name.find("_Int") != Name.npos ||
503 Name.find("Int_") != Name.npos)
504 return FILTER_STRONG;
506 // Filter out instructions with segment override prefixes.
507 // They're too messy to handle now and we'll special case them if needed.
510 return FILTER_STRONG;
518 // Filter out instructions with a LOCK prefix;
519 // prefer forms that do not have the prefix
523 // Filter out alternate forms of AVX instructions
524 if (Name.find("_alt") != Name.npos ||
525 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos && Name.find("r64r8") == Name.npos) ||
526 Name.find("_64mr") != Name.npos ||
527 Name.find("rr64") != Name.npos)
532 if (Name == "PUSH64i16" ||
533 Name == "MOVPQI2QImr" ||
534 Name == "VMOVPQI2QImr" ||
535 Name == "VMASKMOVDQU64")
538 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
539 // For now, just prefer the REP versions.
540 if (Name == "XACQUIRE_PREFIX" ||
541 Name == "XRELEASE_PREFIX")
544 if (HasFROperands && Name.find("MOV") != Name.npos &&
545 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
546 (Name.find("to") != Name.npos)))
547 return FILTER_STRONG;
549 return FILTER_NORMAL;
552 bool RecognizableInstr::hasFROperands() const {
553 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
554 unsigned numOperands = OperandList.size();
556 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
557 const std::string &recName = OperandList[operandIndex].Rec->getName();
559 if (recName.find("FR") != recName.npos)
565 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
566 unsigned &physicalOperandIndex,
567 unsigned &numPhysicalOperands,
568 const unsigned *operandMapping,
569 OperandEncoding (*encodingFromString)
571 bool hasOpSizePrefix)) {
573 if (physicalOperandIndex >= numPhysicalOperands)
576 assert(physicalOperandIndex < numPhysicalOperands);
579 while (operandMapping[operandIndex] != operandIndex) {
580 Spec->operands[operandIndex].encoding = ENCODING_DUP;
581 Spec->operands[operandIndex].type =
582 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
586 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
588 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
590 Spec->operands[operandIndex].type = typeFromString(typeName,
596 ++physicalOperandIndex;
599 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
602 if (!ShouldBeEmitted)
607 Spec->filtered = true;
610 ShouldBeEmitted = false;
616 Spec->insnContext = insnContext();
618 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
620 unsigned numOperands = OperandList.size();
621 unsigned numPhysicalOperands = 0;
623 // operandMapping maps from operands in OperandList to their originals.
624 // If operandMapping[i] != i, then the entry is a duplicate.
625 unsigned operandMapping[X86_MAX_OPERANDS];
626 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
628 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
629 if (OperandList[operandIndex].Constraints.size()) {
630 const CGIOperandList::ConstraintInfo &Constraint =
631 OperandList[operandIndex].Constraints[0];
632 if (Constraint.isTied()) {
633 operandMapping[operandIndex] = operandIndex;
634 operandMapping[Constraint.getTiedOperand()] = operandIndex;
636 ++numPhysicalOperands;
637 operandMapping[operandIndex] = operandIndex;
640 ++numPhysicalOperands;
641 operandMapping[operandIndex] = operandIndex;
645 #define HANDLE_OPERAND(class) \
646 handleOperand(false, \
648 physicalOperandIndex, \
649 numPhysicalOperands, \
651 class##EncodingFromString);
653 #define HANDLE_OPTIONAL(class) \
654 handleOperand(true, \
656 physicalOperandIndex, \
657 numPhysicalOperands, \
659 class##EncodingFromString);
661 // operandIndex should always be < numOperands
662 unsigned operandIndex = 0;
663 // physicalOperandIndex should always be < numPhysicalOperands
664 unsigned physicalOperandIndex = 0;
667 case X86Local::RawFrm:
668 // Operand 1 (optional) is an address or immediate.
669 // Operand 2 (optional) is an immediate.
670 assert(numPhysicalOperands <= 2 &&
671 "Unexpected number of operands for RawFrm");
672 HANDLE_OPTIONAL(relocation)
673 HANDLE_OPTIONAL(immediate)
675 case X86Local::AddRegFrm:
676 // Operand 1 is added to the opcode.
677 // Operand 2 (optional) is an address.
678 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
679 "Unexpected number of operands for AddRegFrm");
680 HANDLE_OPERAND(opcodeModifier)
681 HANDLE_OPTIONAL(relocation)
683 case X86Local::MRMDestReg:
684 // Operand 1 is a register operand in the R/M field.
685 // Operand 2 is a register operand in the Reg/Opcode field.
686 // - In AVX, there is a register operand in the VEX.vvvv field here -
687 // Operand 3 (optional) is an immediate.
689 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
690 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
692 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
693 "Unexpected number of operands for MRMDestRegFrm");
695 HANDLE_OPERAND(rmRegister)
698 // FIXME: In AVX, the register below becomes the one encoded
699 // in ModRMVEX and the one above the one in the VEX.VVVV field
700 HANDLE_OPERAND(vvvvRegister)
702 HANDLE_OPERAND(roRegister)
703 HANDLE_OPTIONAL(immediate)
705 case X86Local::MRMDestMem:
706 // Operand 1 is a memory operand (possibly SIB-extended)
707 // Operand 2 is a register operand in the Reg/Opcode field.
708 // - In AVX, there is a register operand in the VEX.vvvv field here -
709 // Operand 3 (optional) is an immediate.
711 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
712 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
714 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
715 "Unexpected number of operands for MRMDestMemFrm");
716 HANDLE_OPERAND(memory)
719 HANDLE_OPERAND(writemaskRegister)
722 // FIXME: In AVX, the register below becomes the one encoded
723 // in ModRMVEX and the one above the one in the VEX.VVVV field
724 HANDLE_OPERAND(vvvvRegister)
726 HANDLE_OPERAND(roRegister)
727 HANDLE_OPTIONAL(immediate)
729 case X86Local::MRMSrcReg:
730 // Operand 1 is a register operand in the Reg/Opcode field.
731 // Operand 2 is a register operand in the R/M field.
732 // - In AVX, there is a register operand in the VEX.vvvv field here -
733 // Operand 3 (optional) is an immediate.
734 // Operand 4 (optional) is an immediate.
736 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
737 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
738 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
740 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
741 "Unexpected number of operands for MRMSrcRegFrm");
743 HANDLE_OPERAND(roRegister)
746 HANDLE_OPERAND(writemaskRegister)
749 // FIXME: In AVX, the register below becomes the one encoded
750 // in ModRMVEX and the one above the one in the VEX.VVVV field
751 HANDLE_OPERAND(vvvvRegister)
754 HANDLE_OPERAND(immediate)
756 HANDLE_OPERAND(rmRegister)
758 if (HasVEX_4VOp3Prefix)
759 HANDLE_OPERAND(vvvvRegister)
761 if (!HasMemOp4Prefix)
762 HANDLE_OPTIONAL(immediate)
763 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
764 HANDLE_OPTIONAL(immediate)
766 case X86Local::MRMSrcMem:
767 // Operand 1 is a register operand in the Reg/Opcode field.
768 // Operand 2 is a memory operand (possibly SIB-extended)
769 // - In AVX, there is a register operand in the VEX.vvvv field here -
770 // Operand 3 (optional) is an immediate.
772 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
773 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
774 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
776 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
777 "Unexpected number of operands for MRMSrcMemFrm");
779 HANDLE_OPERAND(roRegister)
782 HANDLE_OPERAND(writemaskRegister)
785 // FIXME: In AVX, the register below becomes the one encoded
786 // in ModRMVEX and the one above the one in the VEX.VVVV field
787 HANDLE_OPERAND(vvvvRegister)
790 HANDLE_OPERAND(immediate)
792 HANDLE_OPERAND(memory)
794 if (HasVEX_4VOp3Prefix)
795 HANDLE_OPERAND(vvvvRegister)
797 if (!HasMemOp4Prefix)
798 HANDLE_OPTIONAL(immediate)
799 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
801 case X86Local::MRM0r:
802 case X86Local::MRM1r:
803 case X86Local::MRM2r:
804 case X86Local::MRM3r:
805 case X86Local::MRM4r:
806 case X86Local::MRM5r:
807 case X86Local::MRM6r:
808 case X86Local::MRM7r:
810 // Operand 1 is a register operand in the R/M field.
811 // Operand 2 (optional) is an immediate or relocation.
812 // Operand 3 (optional) is an immediate.
813 unsigned kOp = (HasEVEX_K) ? 1:0;
814 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
815 if (numPhysicalOperands > 3 + kOp + Op4v)
816 llvm_unreachable("Unexpected number of operands for MRMnr");
819 HANDLE_OPERAND(vvvvRegister)
822 HANDLE_OPERAND(writemaskRegister)
823 HANDLE_OPTIONAL(rmRegister)
824 HANDLE_OPTIONAL(relocation)
825 HANDLE_OPTIONAL(immediate)
827 case X86Local::MRM0m:
828 case X86Local::MRM1m:
829 case X86Local::MRM2m:
830 case X86Local::MRM3m:
831 case X86Local::MRM4m:
832 case X86Local::MRM5m:
833 case X86Local::MRM6m:
834 case X86Local::MRM7m:
836 // Operand 1 is a memory operand (possibly SIB-extended)
837 // Operand 2 (optional) is an immediate or relocation.
838 unsigned kOp = (HasEVEX_K) ? 1:0;
839 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
840 if (numPhysicalOperands < 1 + kOp + Op4v ||
841 numPhysicalOperands > 2 + kOp + Op4v)
842 llvm_unreachable("Unexpected number of operands for MRMnm");
845 HANDLE_OPERAND(vvvvRegister)
847 HANDLE_OPERAND(writemaskRegister)
848 HANDLE_OPERAND(memory)
849 HANDLE_OPTIONAL(relocation)
851 case X86Local::RawFrmImm8:
852 // operand 1 is a 16-bit immediate
853 // operand 2 is an 8-bit immediate
854 assert(numPhysicalOperands == 2 &&
855 "Unexpected number of operands for X86Local::RawFrmImm8");
856 HANDLE_OPERAND(immediate)
857 HANDLE_OPERAND(immediate)
859 case X86Local::RawFrmImm16:
860 // operand 1 is a 16-bit immediate
861 // operand 2 is a 16-bit immediate
862 HANDLE_OPERAND(immediate)
863 HANDLE_OPERAND(immediate)
865 case X86Local::MRM_F8:
866 if (Opcode == 0xc6) {
867 assert(numPhysicalOperands == 1 &&
868 "Unexpected number of operands for X86Local::MRM_F8");
869 HANDLE_OPERAND(immediate)
870 } else if (Opcode == 0xc7) {
871 assert(numPhysicalOperands == 1 &&
872 "Unexpected number of operands for X86Local::MRM_F8");
873 HANDLE_OPERAND(relocation)
876 case X86Local::MRMInitReg:
881 #undef HANDLE_OPERAND
882 #undef HANDLE_OPTIONAL
885 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
886 // Special cases where the LLVM tables are not complete
888 #define MAP(from, to) \
889 case X86Local::MRM_##from: \
890 filter = new ExactFilter(0x##from); \
893 OpcodeType opcodeType = (OpcodeType)-1;
895 ModRMFilter* filter = NULL;
896 uint8_t opcodeToSet = 0;
899 default: llvm_unreachable("Invalid prefix!");
900 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
904 opcodeType = TWOBYTE;
908 if (needsModRMForDecode(Form))
909 filter = new ModFilter(isRegFormat(Form));
911 filter = new DumbFilter();
913 #define EXTENSION_TABLE(n) case 0x##n:
914 TWO_BYTE_EXTENSION_TABLES
915 #undef EXTENSION_TABLE
918 llvm_unreachable("Unhandled two-byte extended opcode");
919 case X86Local::MRM0r:
920 case X86Local::MRM1r:
921 case X86Local::MRM2r:
922 case X86Local::MRM3r:
923 case X86Local::MRM4r:
924 case X86Local::MRM5r:
925 case X86Local::MRM6r:
926 case X86Local::MRM7r:
927 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
929 case X86Local::MRM0m:
930 case X86Local::MRM1m:
931 case X86Local::MRM2m:
932 case X86Local::MRM3m:
933 case X86Local::MRM4m:
934 case X86Local::MRM5m:
935 case X86Local::MRM6m:
936 case X86Local::MRM7m:
937 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
943 opcodeToSet = Opcode;
948 opcodeType = THREEBYTE_38;
951 if (needsModRMForDecode(Form))
952 filter = new ModFilter(isRegFormat(Form));
954 filter = new DumbFilter();
956 #define EXTENSION_TABLE(n) case 0x##n:
957 THREE_BYTE_38_EXTENSION_TABLES
958 #undef EXTENSION_TABLE
961 llvm_unreachable("Unhandled two-byte extended opcode");
962 case X86Local::MRM0r:
963 case X86Local::MRM1r:
964 case X86Local::MRM2r:
965 case X86Local::MRM3r:
966 case X86Local::MRM4r:
967 case X86Local::MRM5r:
968 case X86Local::MRM6r:
969 case X86Local::MRM7r:
970 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
972 case X86Local::MRM0m:
973 case X86Local::MRM1m:
974 case X86Local::MRM2m:
975 case X86Local::MRM3m:
976 case X86Local::MRM4m:
977 case X86Local::MRM5m:
978 case X86Local::MRM6m:
979 case X86Local::MRM7m:
980 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
986 opcodeToSet = Opcode;
990 opcodeType = THREEBYTE_3A;
991 if (needsModRMForDecode(Form))
992 filter = new ModFilter(isRegFormat(Form));
994 filter = new DumbFilter();
995 opcodeToSet = Opcode;
998 opcodeType = THREEBYTE_A6;
999 if (needsModRMForDecode(Form))
1000 filter = new ModFilter(isRegFormat(Form));
1002 filter = new DumbFilter();
1003 opcodeToSet = Opcode;
1006 opcodeType = THREEBYTE_A7;
1007 if (needsModRMForDecode(Form))
1008 filter = new ModFilter(isRegFormat(Form));
1010 filter = new DumbFilter();
1011 opcodeToSet = Opcode;
1013 case X86Local::XOP8:
1014 opcodeType = XOP8_MAP;
1015 if (needsModRMForDecode(Form))
1016 filter = new ModFilter(isRegFormat(Form));
1018 filter = new DumbFilter();
1019 opcodeToSet = Opcode;
1021 case X86Local::XOP9:
1022 opcodeType = XOP9_MAP;
1025 if (needsModRMForDecode(Form))
1026 filter = new ModFilter(isRegFormat(Form));
1028 filter = new DumbFilter();
1030 #define EXTENSION_TABLE(n) case 0x##n:
1031 XOP9_MAP_EXTENSION_TABLES
1032 #undef EXTENSION_TABLE
1035 llvm_unreachable("Unhandled XOP9 extended opcode");
1036 case X86Local::MRM0r:
1037 case X86Local::MRM1r:
1038 case X86Local::MRM2r:
1039 case X86Local::MRM3r:
1040 case X86Local::MRM4r:
1041 case X86Local::MRM5r:
1042 case X86Local::MRM6r:
1043 case X86Local::MRM7r:
1044 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1046 case X86Local::MRM0m:
1047 case X86Local::MRM1m:
1048 case X86Local::MRM2m:
1049 case X86Local::MRM3m:
1050 case X86Local::MRM4m:
1051 case X86Local::MRM5m:
1052 case X86Local::MRM6m:
1053 case X86Local::MRM7m:
1054 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1059 } // switch (Opcode)
1060 opcodeToSet = Opcode;
1062 case X86Local::XOPA:
1063 opcodeType = XOPA_MAP;
1064 if (needsModRMForDecode(Form))
1065 filter = new ModFilter(isRegFormat(Form));
1067 filter = new DumbFilter();
1068 opcodeToSet = Opcode;
1078 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1079 opcodeType = ONEBYTE;
1080 if (Form == X86Local::AddRegFrm) {
1081 Spec->modifierType = MODIFIER_MODRM;
1082 Spec->modifierBase = Opcode;
1083 filter = new AddRegEscapeFilter(Opcode);
1085 filter = new EscapeFilter(true, Opcode);
1087 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1091 opcodeType = ONEBYTE;
1093 #define EXTENSION_TABLE(n) case 0x##n:
1094 ONE_BYTE_EXTENSION_TABLES
1095 #undef EXTENSION_TABLE
1098 llvm_unreachable("Fell through the cracks of a single-byte "
1100 case X86Local::MRM0r:
1101 case X86Local::MRM1r:
1102 case X86Local::MRM2r:
1103 case X86Local::MRM3r:
1104 case X86Local::MRM4r:
1105 case X86Local::MRM5r:
1106 case X86Local::MRM6r:
1107 case X86Local::MRM7r:
1108 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1110 case X86Local::MRM0m:
1111 case X86Local::MRM1m:
1112 case X86Local::MRM2m:
1113 case X86Local::MRM3m:
1114 case X86Local::MRM4m:
1115 case X86Local::MRM5m:
1116 case X86Local::MRM6m:
1117 case X86Local::MRM7m:
1118 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1131 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1134 if (needsModRMForDecode(Form))
1135 filter = new ModFilter(isRegFormat(Form));
1137 filter = new DumbFilter();
1139 } // switch (Opcode)
1140 opcodeToSet = Opcode;
1141 } // switch (Prefix)
1143 assert(opcodeType != (OpcodeType)-1 &&
1144 "Opcode type not set");
1145 assert(filter && "Filter not set");
1147 if (Form == X86Local::AddRegFrm) {
1148 if(Spec->modifierType != MODIFIER_MODRM) {
1149 assert(opcodeToSet < 0xf9 &&
1150 "Not enough room for all ADDREG_FRM operands");
1152 uint8_t currentOpcode;
1154 for (currentOpcode = opcodeToSet;
1155 currentOpcode < opcodeToSet + 8;
1157 tables.setTableFields(opcodeType,
1161 UID, Is32Bit, IgnoresVEX_L);
1163 Spec->modifierType = MODIFIER_OPCODE;
1164 Spec->modifierBase = opcodeToSet;
1166 // modifierBase was set where MODIFIER_MODRM was set
1167 tables.setTableFields(opcodeType,
1171 UID, Is32Bit, IgnoresVEX_L);
1174 tables.setTableFields(opcodeType,
1178 UID, Is32Bit, IgnoresVEX_L);
1180 Spec->modifierType = MODIFIER_NONE;
1181 Spec->modifierBase = opcodeToSet;
1189 #define TYPE(str, type) if (s == str) return type;
1190 OperandType RecognizableInstr::typeFromString(const std::string &s,
1192 bool hasREX_WPrefix,
1193 bool hasOpSizePrefix) {
1195 // For SSE instructions, we ignore the OpSize prefix and force operand
1197 TYPE("GR16", TYPE_R16)
1198 TYPE("GR32", TYPE_R32)
1199 TYPE("GR64", TYPE_R64)
1201 if(hasREX_WPrefix) {
1202 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1204 TYPE("GR32", TYPE_R32)
1206 if(!hasOpSizePrefix) {
1207 // For instructions without an OpSize prefix, a declared 16-bit register or
1208 // immediate encoding is special.
1209 TYPE("GR16", TYPE_R16)
1210 TYPE("i16imm", TYPE_IMM16)
1212 TYPE("i16mem", TYPE_Mv)
1213 TYPE("i16imm", TYPE_IMMv)
1214 TYPE("i16i8imm", TYPE_IMMv)
1215 TYPE("GR16", TYPE_Rv)
1216 TYPE("i32mem", TYPE_Mv)
1217 TYPE("i32imm", TYPE_IMMv)
1218 TYPE("i32i8imm", TYPE_IMM32)
1219 TYPE("u32u8imm", TYPE_IMM32)
1220 TYPE("GR32", TYPE_Rv)
1221 TYPE("i64mem", TYPE_Mv)
1222 TYPE("i64i32imm", TYPE_IMM64)
1223 TYPE("i64i8imm", TYPE_IMM64)
1224 TYPE("GR64", TYPE_R64)
1225 TYPE("i8mem", TYPE_M8)
1226 TYPE("i8imm", TYPE_IMM8)
1227 TYPE("GR8", TYPE_R8)
1228 TYPE("VR128", TYPE_XMM128)
1229 TYPE("VR128X", TYPE_XMM128)
1230 TYPE("f128mem", TYPE_M128)
1231 TYPE("f256mem", TYPE_M256)
1232 TYPE("f512mem", TYPE_M512)
1233 TYPE("FR64", TYPE_XMM64)
1234 TYPE("FR64X", TYPE_XMM64)
1235 TYPE("f64mem", TYPE_M64FP)
1236 TYPE("sdmem", TYPE_M64FP)
1237 TYPE("FR32", TYPE_XMM32)
1238 TYPE("FR32X", TYPE_XMM32)
1239 TYPE("f32mem", TYPE_M32FP)
1240 TYPE("ssmem", TYPE_M32FP)
1241 TYPE("RST", TYPE_ST)
1242 TYPE("i128mem", TYPE_M128)
1243 TYPE("i256mem", TYPE_M256)
1244 TYPE("i512mem", TYPE_M512)
1245 TYPE("i64i32imm_pcrel", TYPE_REL64)
1246 TYPE("i16imm_pcrel", TYPE_REL16)
1247 TYPE("i32imm_pcrel", TYPE_REL32)
1248 TYPE("SSECC", TYPE_IMM3)
1249 TYPE("AVXCC", TYPE_IMM5)
1250 TYPE("brtarget", TYPE_RELv)
1251 TYPE("uncondbrtarget", TYPE_RELv)
1252 TYPE("brtarget8", TYPE_REL8)
1253 TYPE("f80mem", TYPE_M80FP)
1254 TYPE("lea32mem", TYPE_LEA)
1255 TYPE("lea64_32mem", TYPE_LEA)
1256 TYPE("lea64mem", TYPE_LEA)
1257 TYPE("VR64", TYPE_MM64)
1258 TYPE("i64imm", TYPE_IMMv)
1259 TYPE("opaque32mem", TYPE_M1616)
1260 TYPE("opaque48mem", TYPE_M1632)
1261 TYPE("opaque80mem", TYPE_M1664)
1262 TYPE("opaque512mem", TYPE_M512)
1263 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1264 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1265 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1266 TYPE("offset8", TYPE_MOFFS8)
1267 TYPE("offset16", TYPE_MOFFS16)
1268 TYPE("offset32", TYPE_MOFFS32)
1269 TYPE("offset64", TYPE_MOFFS64)
1270 TYPE("VR256", TYPE_XMM256)
1271 TYPE("VR256X", TYPE_XMM256)
1272 TYPE("VR512", TYPE_XMM512)
1273 TYPE("VK8", TYPE_VK8)
1274 TYPE("VK8WM", TYPE_VK8)
1275 TYPE("VK16", TYPE_VK16)
1276 TYPE("VK16WM", TYPE_VK16)
1277 TYPE("GR16_NOAX", TYPE_Rv)
1278 TYPE("GR32_NOAX", TYPE_Rv)
1279 TYPE("GR64_NOAX", TYPE_R64)
1280 TYPE("vx32mem", TYPE_M32)
1281 TYPE("vy32mem", TYPE_M32)
1282 TYPE("vz32mem", TYPE_M32)
1283 TYPE("vx64mem", TYPE_M64)
1284 TYPE("vy64mem", TYPE_M64)
1285 TYPE("vy64xmem", TYPE_M64)
1286 TYPE("vz64mem", TYPE_M64)
1287 errs() << "Unhandled type string " << s << "\n";
1288 llvm_unreachable("Unhandled type string");
1292 #define ENCODING(str, encoding) if (s == str) return encoding;
1293 OperandEncoding RecognizableInstr::immediateEncodingFromString
1294 (const std::string &s,
1295 bool hasOpSizePrefix) {
1296 if(!hasOpSizePrefix) {
1297 // For instructions without an OpSize prefix, a declared 16-bit register or
1298 // immediate encoding is special.
1299 ENCODING("i16imm", ENCODING_IW)
1301 ENCODING("i32i8imm", ENCODING_IB)
1302 ENCODING("u32u8imm", ENCODING_IB)
1303 ENCODING("SSECC", ENCODING_IB)
1304 ENCODING("AVXCC", ENCODING_IB)
1305 ENCODING("i16imm", ENCODING_Iv)
1306 ENCODING("i16i8imm", ENCODING_IB)
1307 ENCODING("i32imm", ENCODING_Iv)
1308 ENCODING("i64i32imm", ENCODING_ID)
1309 ENCODING("i64i8imm", ENCODING_IB)
1310 ENCODING("i8imm", ENCODING_IB)
1311 // This is not a typo. Instructions like BLENDVPD put
1312 // register IDs in 8-bit immediates nowadays.
1313 ENCODING("FR32", ENCODING_IB)
1314 ENCODING("FR64", ENCODING_IB)
1315 ENCODING("VR128", ENCODING_IB)
1316 ENCODING("VR256", ENCODING_IB)
1317 ENCODING("FR32X", ENCODING_IB)
1318 ENCODING("FR64X", ENCODING_IB)
1319 ENCODING("VR128X", ENCODING_IB)
1320 ENCODING("VR256X", ENCODING_IB)
1321 ENCODING("VR512", ENCODING_IB)
1322 errs() << "Unhandled immediate encoding " << s << "\n";
1323 llvm_unreachable("Unhandled immediate encoding");
1326 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1327 (const std::string &s,
1328 bool hasOpSizePrefix) {
1329 ENCODING("GR16", ENCODING_RM)
1330 ENCODING("GR32", ENCODING_RM)
1331 ENCODING("GR64", ENCODING_RM)
1332 ENCODING("GR8", ENCODING_RM)
1333 ENCODING("VR128", ENCODING_RM)
1334 ENCODING("VR128X", ENCODING_RM)
1335 ENCODING("FR64", ENCODING_RM)
1336 ENCODING("FR32", ENCODING_RM)
1337 ENCODING("FR64X", ENCODING_RM)
1338 ENCODING("FR32X", ENCODING_RM)
1339 ENCODING("VR64", ENCODING_RM)
1340 ENCODING("VR256", ENCODING_RM)
1341 ENCODING("VR256X", ENCODING_RM)
1342 ENCODING("VR512", ENCODING_RM)
1343 ENCODING("VK8", ENCODING_RM)
1344 ENCODING("VK16", ENCODING_RM)
1345 errs() << "Unhandled R/M register encoding " << s << "\n";
1346 llvm_unreachable("Unhandled R/M register encoding");
1349 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1350 (const std::string &s,
1351 bool hasOpSizePrefix) {
1352 ENCODING("GR16", ENCODING_REG)
1353 ENCODING("GR32", ENCODING_REG)
1354 ENCODING("GR64", ENCODING_REG)
1355 ENCODING("GR8", ENCODING_REG)
1356 ENCODING("VR128", ENCODING_REG)
1357 ENCODING("FR64", ENCODING_REG)
1358 ENCODING("FR32", ENCODING_REG)
1359 ENCODING("VR64", ENCODING_REG)
1360 ENCODING("SEGMENT_REG", ENCODING_REG)
1361 ENCODING("DEBUG_REG", ENCODING_REG)
1362 ENCODING("CONTROL_REG", ENCODING_REG)
1363 ENCODING("VR256", ENCODING_REG)
1364 ENCODING("VR256X", ENCODING_REG)
1365 ENCODING("VR128X", ENCODING_REG)
1366 ENCODING("FR64X", ENCODING_REG)
1367 ENCODING("FR32X", ENCODING_REG)
1368 ENCODING("VR512", ENCODING_REG)
1369 ENCODING("VK8", ENCODING_REG)
1370 ENCODING("VK16", ENCODING_REG)
1371 ENCODING("VK8WM", ENCODING_REG)
1372 ENCODING("VK16WM", ENCODING_REG)
1373 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1374 llvm_unreachable("Unhandled reg/opcode register encoding");
1377 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1378 (const std::string &s,
1379 bool hasOpSizePrefix) {
1380 ENCODING("GR32", ENCODING_VVVV)
1381 ENCODING("GR64", ENCODING_VVVV)
1382 ENCODING("FR32", ENCODING_VVVV)
1383 ENCODING("FR64", ENCODING_VVVV)
1384 ENCODING("VR128", ENCODING_VVVV)
1385 ENCODING("VR256", ENCODING_VVVV)
1386 ENCODING("FR32X", ENCODING_VVVV)
1387 ENCODING("FR64X", ENCODING_VVVV)
1388 ENCODING("VR128X", ENCODING_VVVV)
1389 ENCODING("VR256X", ENCODING_VVVV)
1390 ENCODING("VR512", ENCODING_VVVV)
1391 ENCODING("VK8", ENCODING_VVVV)
1392 ENCODING("VK16", ENCODING_VVVV)
1393 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1394 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1397 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1398 (const std::string &s,
1399 bool hasOpSizePrefix) {
1400 ENCODING("VK8WM", ENCODING_WRITEMASK)
1401 ENCODING("VK16WM", ENCODING_WRITEMASK)
1402 errs() << "Unhandled mask register encoding " << s << "\n";
1403 llvm_unreachable("Unhandled mask register encoding");
1406 OperandEncoding RecognizableInstr::memoryEncodingFromString
1407 (const std::string &s,
1408 bool hasOpSizePrefix) {
1409 ENCODING("i16mem", ENCODING_RM)
1410 ENCODING("i32mem", ENCODING_RM)
1411 ENCODING("i64mem", ENCODING_RM)
1412 ENCODING("i8mem", ENCODING_RM)
1413 ENCODING("ssmem", ENCODING_RM)
1414 ENCODING("sdmem", ENCODING_RM)
1415 ENCODING("f128mem", ENCODING_RM)
1416 ENCODING("f256mem", ENCODING_RM)
1417 ENCODING("f512mem", ENCODING_RM)
1418 ENCODING("f64mem", ENCODING_RM)
1419 ENCODING("f32mem", ENCODING_RM)
1420 ENCODING("i128mem", ENCODING_RM)
1421 ENCODING("i256mem", ENCODING_RM)
1422 ENCODING("i512mem", ENCODING_RM)
1423 ENCODING("f80mem", ENCODING_RM)
1424 ENCODING("lea32mem", ENCODING_RM)
1425 ENCODING("lea64_32mem", ENCODING_RM)
1426 ENCODING("lea64mem", ENCODING_RM)
1427 ENCODING("opaque32mem", ENCODING_RM)
1428 ENCODING("opaque48mem", ENCODING_RM)
1429 ENCODING("opaque80mem", ENCODING_RM)
1430 ENCODING("opaque512mem", ENCODING_RM)
1431 ENCODING("vx32mem", ENCODING_RM)
1432 ENCODING("vy32mem", ENCODING_RM)
1433 ENCODING("vz32mem", ENCODING_RM)
1434 ENCODING("vx64mem", ENCODING_RM)
1435 ENCODING("vy64mem", ENCODING_RM)
1436 ENCODING("vy64xmem", ENCODING_RM)
1437 ENCODING("vz64mem", ENCODING_RM)
1438 errs() << "Unhandled memory encoding " << s << "\n";
1439 llvm_unreachable("Unhandled memory encoding");
1442 OperandEncoding RecognizableInstr::relocationEncodingFromString
1443 (const std::string &s,
1444 bool hasOpSizePrefix) {
1445 if(!hasOpSizePrefix) {
1446 // For instructions without an OpSize prefix, a declared 16-bit register or
1447 // immediate encoding is special.
1448 ENCODING("i16imm", ENCODING_IW)
1450 ENCODING("i16imm", ENCODING_Iv)
1451 ENCODING("i16i8imm", ENCODING_IB)
1452 ENCODING("i32imm", ENCODING_Iv)
1453 ENCODING("i32i8imm", ENCODING_IB)
1454 ENCODING("i64i32imm", ENCODING_ID)
1455 ENCODING("i64i8imm", ENCODING_IB)
1456 ENCODING("i8imm", ENCODING_IB)
1457 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1458 ENCODING("i16imm_pcrel", ENCODING_IW)
1459 ENCODING("i32imm_pcrel", ENCODING_ID)
1460 ENCODING("brtarget", ENCODING_Iv)
1461 ENCODING("brtarget8", ENCODING_IB)
1462 ENCODING("i64imm", ENCODING_IO)
1463 ENCODING("offset8", ENCODING_Ia)
1464 ENCODING("offset16", ENCODING_Ia)
1465 ENCODING("offset32", ENCODING_Ia)
1466 ENCODING("offset64", ENCODING_Ia)
1467 errs() << "Unhandled relocation encoding " << s << "\n";
1468 llvm_unreachable("Unhandled relocation encoding");
1471 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1472 (const std::string &s,
1473 bool hasOpSizePrefix) {
1474 ENCODING("RST", ENCODING_I)
1475 ENCODING("GR32", ENCODING_Rv)
1476 ENCODING("GR64", ENCODING_RO)
1477 ENCODING("GR16", ENCODING_Rv)
1478 ENCODING("GR8", ENCODING_RB)
1479 ENCODING("GR16_NOAX", ENCODING_Rv)
1480 ENCODING("GR32_NOAX", ENCODING_Rv)
1481 ENCODING("GR64_NOAX", ENCODING_RO)
1482 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1483 llvm_unreachable("Unhandled opcode modifier encoding");