1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86RecognizableInstr.h"
18 #include "X86DisassemblerShared.h"
19 #include "X86ModRMFilters.h"
20 #include "llvm/Support/ErrorHandling.h"
52 // A clone of X86 since we can't depend on something that is generated.
62 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
69 #define MAP(from, to) MRM_##from = to,
78 D8 = 3, D9 = 4, DA = 5, DB = 6,
79 DC = 7, DD = 8, DE = 9, DF = 10,
82 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
86 // If rows are added to the opcode extension tables, then corresponding entries
87 // must be added here.
89 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
90 // that byte to ONE_BYTE_EXTENSION_TABLES.
92 // If the row corresponds to two bytes where the first is 0f, add an entry for
93 // the second byte to TWO_BYTE_EXTENSION_TABLES.
95 // If the row corresponds to some other set of bytes, you will need to modify
96 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
97 // to the X86 TD files, except in two cases: if the first two bytes of such a
98 // new combination are 0f 38 or 0f 3a, you just have to add maps called
99 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
100 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
101 // in RecognizableInstr::emitDecodePath().
103 #define ONE_BYTE_EXTENSION_TABLES \
104 EXTENSION_TABLE(80) \
105 EXTENSION_TABLE(81) \
106 EXTENSION_TABLE(82) \
107 EXTENSION_TABLE(83) \
108 EXTENSION_TABLE(8f) \
109 EXTENSION_TABLE(c0) \
110 EXTENSION_TABLE(c1) \
111 EXTENSION_TABLE(c6) \
112 EXTENSION_TABLE(c7) \
113 EXTENSION_TABLE(d0) \
114 EXTENSION_TABLE(d1) \
115 EXTENSION_TABLE(d2) \
116 EXTENSION_TABLE(d3) \
117 EXTENSION_TABLE(f6) \
118 EXTENSION_TABLE(f7) \
119 EXTENSION_TABLE(fe) \
122 #define TWO_BYTE_EXTENSION_TABLES \
123 EXTENSION_TABLE(00) \
124 EXTENSION_TABLE(01) \
125 EXTENSION_TABLE(0d) \
126 EXTENSION_TABLE(18) \
127 EXTENSION_TABLE(71) \
128 EXTENSION_TABLE(72) \
129 EXTENSION_TABLE(73) \
130 EXTENSION_TABLE(ae) \
131 EXTENSION_TABLE(ba) \
134 #define THREE_BYTE_38_EXTENSION_TABLES \
137 using namespace X86Disassembler;
139 /// needsModRMForDecode - Indicates whether a particular instruction requires a
140 /// ModR/M byte for the instruction to be properly decoded. For example, a
141 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
144 /// @param form - The form of the instruction.
145 /// @return - true if the form implies that a ModR/M byte is required, false
147 static bool needsModRMForDecode(uint8_t form) {
148 if (form == X86Local::MRMDestReg ||
149 form == X86Local::MRMDestMem ||
150 form == X86Local::MRMSrcReg ||
151 form == X86Local::MRMSrcMem ||
152 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
153 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
159 /// isRegFormat - Indicates whether a particular form requires the Mod field of
160 /// the ModR/M byte to be 0b11.
162 /// @param form - The form of the instruction.
163 /// @return - true if the form implies that Mod must be 0b11, false
165 static bool isRegFormat(uint8_t form) {
166 if (form == X86Local::MRMDestReg ||
167 form == X86Local::MRMSrcReg ||
168 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
174 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
175 /// Useful for switch statements and the like.
177 /// @param init - A reference to the BitsInit to be decoded.
178 /// @return - The field, with the first bit in the BitsInit as the lowest
180 static uint8_t byteFromBitsInit(BitsInit &init) {
181 int width = init.getNumBits();
183 assert(width <= 8 && "Field is too large for uint8_t!");
190 for (index = 0; index < width; index++) {
191 if (static_cast<BitInit*>(init.getBit(index))->getValue())
200 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
201 /// name of the field.
203 /// @param rec - The record from which to extract the value.
204 /// @param name - The name of the field in the record.
205 /// @return - The field, as translated by byteFromBitsInit().
206 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
207 BitsInit* bits = rec->getValueAsBitsInit(name);
208 return byteFromBitsInit(*bits);
211 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
212 const CodeGenInstruction &insn,
217 Name = Rec->getName();
218 Spec = &tables.specForUID(UID);
220 if (!Rec->isSubClassOf("X86Inst")) {
221 ShouldBeEmitted = false;
225 Prefix = byteFromRec(Rec, "Prefix");
226 Opcode = byteFromRec(Rec, "Opcode");
227 Form = byteFromRec(Rec, "FormBits");
228 SegOvr = byteFromRec(Rec, "SegOvrBits");
230 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
231 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
232 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
233 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
234 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
235 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
236 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
237 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
238 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
239 HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix");
240 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
241 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K");
242 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B");
243 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
244 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
246 Name = Rec->getName();
247 AsmString = Rec->getValueAsString("AsmString");
249 Operands = &insn.Operands.OperandList;
251 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
252 (Name.find("CRC32") != Name.npos);
253 HasFROperands = hasFROperands();
254 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
256 // Check for 64-bit inst which does not require REX
259 // FIXME: Is there some better way to check for In64BitMode?
260 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
261 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
262 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
266 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
271 // FIXME: These instructions aren't marked as 64-bit in any way
272 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
273 Rec->getName() == "MASKMOVDQU64" ||
274 Rec->getName() == "POPFS64" ||
275 Rec->getName() == "POPGS64" ||
276 Rec->getName() == "PUSHFS64" ||
277 Rec->getName() == "PUSHGS64" ||
278 Rec->getName() == "REX64_PREFIX" ||
279 Rec->getName().find("MOV64") != Name.npos ||
280 Rec->getName().find("PUSH64") != Name.npos ||
281 Rec->getName().find("POP64") != Name.npos;
283 ShouldBeEmitted = true;
286 void RecognizableInstr::processInstr(DisassemblerTables &tables,
287 const CodeGenInstruction &insn,
290 // Ignore "asm parser only" instructions.
291 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
294 RecognizableInstr recogInstr(tables, insn, uid);
296 recogInstr.emitInstructionSpecifier(tables);
298 if (recogInstr.shouldBeEmitted())
299 recogInstr.emitDecodePath(tables);
302 #define EVEX_KB(n) (HasEVEX_K && HasEVEX_B? n##_K_B : \
303 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))
305 InstructionContext RecognizableInstr::insnContext() const {
306 InstructionContext insnContext;
309 if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
310 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
311 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
314 if (HasVEX_LPrefix && HasVEX_WPrefix) {
316 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
317 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
318 insnContext = EVEX_KB(IC_EVEX_L_W_XS);
319 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
320 Prefix == X86Local::TAXD)
321 insnContext = EVEX_KB(IC_EVEX_L_W_XD);
323 insnContext = EVEX_KB(IC_EVEX_L_W);
324 } else if (HasVEX_LPrefix) {
327 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
328 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
329 insnContext = EVEX_KB(IC_EVEX_L_XS);
330 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
331 Prefix == X86Local::TAXD)
332 insnContext = EVEX_KB(IC_EVEX_L_XD);
334 insnContext = EVEX_KB(IC_EVEX_L);
336 else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
339 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
340 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
341 insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
342 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
343 Prefix == X86Local::TAXD)
344 insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
346 insnContext = EVEX_KB(IC_EVEX_L2_W);
347 } else if (HasEVEX_L2Prefix) {
350 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
351 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
352 Prefix == X86Local::TAXD)
353 insnContext = EVEX_KB(IC_EVEX_L2_XD);
354 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
355 insnContext = EVEX_KB(IC_EVEX_L2_XS);
357 insnContext = EVEX_KB(IC_EVEX_L2);
359 else if (HasVEX_WPrefix) {
362 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
363 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
364 insnContext = EVEX_KB(IC_EVEX_W_XS);
365 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
366 Prefix == X86Local::TAXD)
367 insnContext = EVEX_KB(IC_EVEX_W_XD);
369 insnContext = EVEX_KB(IC_EVEX_W);
372 else if (HasOpSizePrefix)
373 insnContext = EVEX_KB(IC_EVEX_OPSIZE);
374 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
375 Prefix == X86Local::TAXD)
376 insnContext = EVEX_KB(IC_EVEX_XD);
377 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
378 insnContext = EVEX_KB(IC_EVEX_XS);
380 insnContext = EVEX_KB(IC_EVEX);
382 } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
383 if (HasVEX_LPrefix && HasVEX_WPrefix) {
385 insnContext = IC_VEX_L_W_OPSIZE;
386 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
387 insnContext = IC_VEX_L_W_XS;
388 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
389 Prefix == X86Local::TAXD)
390 insnContext = IC_VEX_L_W_XD;
392 insnContext = IC_VEX_L_W;
393 } else if (HasOpSizePrefix && HasVEX_LPrefix)
394 insnContext = IC_VEX_L_OPSIZE;
395 else if (HasOpSizePrefix && HasVEX_WPrefix)
396 insnContext = IC_VEX_W_OPSIZE;
397 else if (HasOpSizePrefix)
398 insnContext = IC_VEX_OPSIZE;
399 else if (HasVEX_LPrefix &&
400 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
401 insnContext = IC_VEX_L_XS;
402 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
403 Prefix == X86Local::T8XD ||
404 Prefix == X86Local::TAXD))
405 insnContext = IC_VEX_L_XD;
406 else if (HasVEX_WPrefix &&
407 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
408 insnContext = IC_VEX_W_XS;
409 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
410 Prefix == X86Local::T8XD ||
411 Prefix == X86Local::TAXD))
412 insnContext = IC_VEX_W_XD;
413 else if (HasVEX_WPrefix)
414 insnContext = IC_VEX_W;
415 else if (HasVEX_LPrefix)
416 insnContext = IC_VEX_L;
417 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
418 Prefix == X86Local::TAXD)
419 insnContext = IC_VEX_XD;
420 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
421 insnContext = IC_VEX_XS;
423 insnContext = IC_VEX;
424 } else if (Is64Bit || HasREX_WPrefix) {
425 if (HasREX_WPrefix && HasOpSizePrefix)
426 insnContext = IC_64BIT_REXW_OPSIZE;
427 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
428 Prefix == X86Local::T8XD ||
429 Prefix == X86Local::TAXD))
430 insnContext = IC_64BIT_XD_OPSIZE;
431 else if (HasOpSizePrefix &&
432 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
433 insnContext = IC_64BIT_XS_OPSIZE;
434 else if (HasOpSizePrefix)
435 insnContext = IC_64BIT_OPSIZE;
436 else if (HasAdSizePrefix)
437 insnContext = IC_64BIT_ADSIZE;
438 else if (HasREX_WPrefix &&
439 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
440 insnContext = IC_64BIT_REXW_XS;
441 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
442 Prefix == X86Local::T8XD ||
443 Prefix == X86Local::TAXD))
444 insnContext = IC_64BIT_REXW_XD;
445 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
446 Prefix == X86Local::TAXD)
447 insnContext = IC_64BIT_XD;
448 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
449 insnContext = IC_64BIT_XS;
450 else if (HasREX_WPrefix)
451 insnContext = IC_64BIT_REXW;
453 insnContext = IC_64BIT;
455 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
456 Prefix == X86Local::T8XD ||
457 Prefix == X86Local::TAXD))
458 insnContext = IC_XD_OPSIZE;
459 else if (HasOpSizePrefix &&
460 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
461 insnContext = IC_XS_OPSIZE;
462 else if (HasOpSizePrefix)
463 insnContext = IC_OPSIZE;
464 else if (HasAdSizePrefix)
465 insnContext = IC_ADSIZE;
466 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
467 Prefix == X86Local::TAXD)
469 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
470 Prefix == X86Local::REP)
479 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
484 // Filter out intrinsics
486 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
488 if (Form == X86Local::Pseudo ||
489 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
490 return FILTER_STRONG;
493 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
494 // printed as a separate "instruction".
496 if (Name.find("_Int") != Name.npos ||
497 Name.find("Int_") != Name.npos)
498 return FILTER_STRONG;
500 // Filter out instructions with segment override prefixes.
501 // They're too messy to handle now and we'll special case them if needed.
504 return FILTER_STRONG;
512 // Filter out instructions with a LOCK prefix;
513 // prefer forms that do not have the prefix
517 // Filter out alternate forms of AVX instructions
518 if (Name.find("_alt") != Name.npos ||
519 Name.find("XrYr") != Name.npos ||
520 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
521 Name.find("_64mr") != Name.npos ||
522 Name.find("Xrr") != Name.npos ||
523 Name.find("rr64") != Name.npos)
528 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
530 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
533 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
535 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
537 if (Name.find("Fs") != Name.npos)
539 if (Name == "PUSH64i16" ||
540 Name == "MOVPQI2QImr" ||
541 Name == "VMOVPQI2QImr" ||
542 Name == "MMX_MOVD64rrv164" ||
543 Name == "MOV64ri64i32" ||
544 Name == "VMASKMOVDQU64" ||
545 Name == "VEXTRACTPSrr64" ||
546 Name == "VMOVQd64rr" ||
547 Name == "VMOVQs64rr")
550 // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
551 // For now, just prefer the REP versions.
552 if (Name == "XACQUIRE_PREFIX" ||
553 Name == "XRELEASE_PREFIX")
556 if (HasFROperands && Name.find("MOV") != Name.npos &&
557 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
558 (Name.find("to") != Name.npos)))
559 return FILTER_STRONG;
561 return FILTER_NORMAL;
564 bool RecognizableInstr::hasFROperands() const {
565 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
566 unsigned numOperands = OperandList.size();
568 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
569 const std::string &recName = OperandList[operandIndex].Rec->getName();
571 if (recName.find("FR") != recName.npos)
577 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
578 unsigned &physicalOperandIndex,
579 unsigned &numPhysicalOperands,
580 const unsigned *operandMapping,
581 OperandEncoding (*encodingFromString)
583 bool hasOpSizePrefix)) {
585 if (physicalOperandIndex >= numPhysicalOperands)
588 assert(physicalOperandIndex < numPhysicalOperands);
591 while (operandMapping[operandIndex] != operandIndex) {
592 Spec->operands[operandIndex].encoding = ENCODING_DUP;
593 Spec->operands[operandIndex].type =
594 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
598 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
600 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
602 Spec->operands[operandIndex].type = typeFromString(typeName,
608 ++physicalOperandIndex;
611 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
614 if (!ShouldBeEmitted)
619 Spec->filtered = true;
622 ShouldBeEmitted = false;
628 Spec->insnContext = insnContext();
630 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
632 unsigned numOperands = OperandList.size();
633 unsigned numPhysicalOperands = 0;
635 // operandMapping maps from operands in OperandList to their originals.
636 // If operandMapping[i] != i, then the entry is a duplicate.
637 unsigned operandMapping[X86_MAX_OPERANDS];
638 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
640 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
641 if (OperandList[operandIndex].Constraints.size()) {
642 const CGIOperandList::ConstraintInfo &Constraint =
643 OperandList[operandIndex].Constraints[0];
644 if (Constraint.isTied()) {
645 operandMapping[operandIndex] = operandIndex;
646 operandMapping[Constraint.getTiedOperand()] = operandIndex;
648 ++numPhysicalOperands;
649 operandMapping[operandIndex] = operandIndex;
652 ++numPhysicalOperands;
653 operandMapping[operandIndex] = operandIndex;
657 #define HANDLE_OPERAND(class) \
658 handleOperand(false, \
660 physicalOperandIndex, \
661 numPhysicalOperands, \
663 class##EncodingFromString);
665 #define HANDLE_OPTIONAL(class) \
666 handleOperand(true, \
668 physicalOperandIndex, \
669 numPhysicalOperands, \
671 class##EncodingFromString);
673 // operandIndex should always be < numOperands
674 unsigned operandIndex = 0;
675 // physicalOperandIndex should always be < numPhysicalOperands
676 unsigned physicalOperandIndex = 0;
679 case X86Local::RawFrm:
680 // Operand 1 (optional) is an address or immediate.
681 // Operand 2 (optional) is an immediate.
682 assert(numPhysicalOperands <= 2 &&
683 "Unexpected number of operands for RawFrm");
684 HANDLE_OPTIONAL(relocation)
685 HANDLE_OPTIONAL(immediate)
687 case X86Local::AddRegFrm:
688 // Operand 1 is added to the opcode.
689 // Operand 2 (optional) is an address.
690 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
691 "Unexpected number of operands for AddRegFrm");
692 HANDLE_OPERAND(opcodeModifier)
693 HANDLE_OPTIONAL(relocation)
695 case X86Local::MRMDestReg:
696 // Operand 1 is a register operand in the R/M field.
697 // Operand 2 is a register operand in the Reg/Opcode field.
698 // - In AVX, there is a register operand in the VEX.vvvv field here -
699 // Operand 3 (optional) is an immediate.
701 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
702 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
704 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
705 "Unexpected number of operands for MRMDestRegFrm");
707 HANDLE_OPERAND(rmRegister)
710 // FIXME: In AVX, the register below becomes the one encoded
711 // in ModRMVEX and the one above the one in the VEX.VVVV field
712 HANDLE_OPERAND(vvvvRegister)
714 HANDLE_OPERAND(roRegister)
715 HANDLE_OPTIONAL(immediate)
717 case X86Local::MRMDestMem:
718 // Operand 1 is a memory operand (possibly SIB-extended)
719 // Operand 2 is a register operand in the Reg/Opcode field.
720 // - In AVX, there is a register operand in the VEX.vvvv field here -
721 // Operand 3 (optional) is an immediate.
723 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
724 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
726 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
727 "Unexpected number of operands for MRMDestMemFrm");
728 HANDLE_OPERAND(memory)
731 HANDLE_OPERAND(writemaskRegister)
734 // FIXME: In AVX, the register below becomes the one encoded
735 // in ModRMVEX and the one above the one in the VEX.VVVV field
736 HANDLE_OPERAND(vvvvRegister)
738 HANDLE_OPERAND(roRegister)
739 HANDLE_OPTIONAL(immediate)
741 case X86Local::MRMSrcReg:
742 // Operand 1 is a register operand in the Reg/Opcode field.
743 // Operand 2 is a register operand in the R/M field.
744 // - In AVX, there is a register operand in the VEX.vvvv field here -
745 // Operand 3 (optional) is an immediate.
746 // Operand 4 (optional) is an immediate.
748 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
749 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
750 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
752 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
753 "Unexpected number of operands for MRMSrcRegFrm");
755 HANDLE_OPERAND(roRegister)
758 HANDLE_OPERAND(writemaskRegister)
761 // FIXME: In AVX, the register below becomes the one encoded
762 // in ModRMVEX and the one above the one in the VEX.VVVV field
763 HANDLE_OPERAND(vvvvRegister)
766 HANDLE_OPERAND(immediate)
768 HANDLE_OPERAND(rmRegister)
770 if (HasVEX_4VOp3Prefix)
771 HANDLE_OPERAND(vvvvRegister)
773 if (!HasMemOp4Prefix)
774 HANDLE_OPTIONAL(immediate)
775 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
776 HANDLE_OPTIONAL(immediate)
778 case X86Local::MRMSrcMem:
779 // Operand 1 is a register operand in the Reg/Opcode field.
780 // Operand 2 is a memory operand (possibly SIB-extended)
781 // - In AVX, there is a register operand in the VEX.vvvv field here -
782 // Operand 3 (optional) is an immediate.
784 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
785 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
786 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
788 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
789 "Unexpected number of operands for MRMSrcMemFrm");
791 HANDLE_OPERAND(roRegister)
794 HANDLE_OPERAND(writemaskRegister)
797 // FIXME: In AVX, the register below becomes the one encoded
798 // in ModRMVEX and the one above the one in the VEX.VVVV field
799 HANDLE_OPERAND(vvvvRegister)
802 HANDLE_OPERAND(immediate)
804 HANDLE_OPERAND(memory)
806 if (HasVEX_4VOp3Prefix)
807 HANDLE_OPERAND(vvvvRegister)
809 if (!HasMemOp4Prefix)
810 HANDLE_OPTIONAL(immediate)
811 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
813 case X86Local::MRM0r:
814 case X86Local::MRM1r:
815 case X86Local::MRM2r:
816 case X86Local::MRM3r:
817 case X86Local::MRM4r:
818 case X86Local::MRM5r:
819 case X86Local::MRM6r:
820 case X86Local::MRM7r:
822 // Operand 1 is a register operand in the R/M field.
823 // Operand 2 (optional) is an immediate or relocation.
824 // Operand 3 (optional) is an immediate.
825 unsigned kOp = (HasEVEX_K) ? 1:0;
826 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
827 if (numPhysicalOperands > 3 + kOp + Op4v)
828 llvm_unreachable("Unexpected number of operands for MRMnr");
831 HANDLE_OPERAND(vvvvRegister)
834 HANDLE_OPERAND(writemaskRegister)
835 HANDLE_OPTIONAL(rmRegister)
836 HANDLE_OPTIONAL(relocation)
837 HANDLE_OPTIONAL(immediate)
839 case X86Local::MRM0m:
840 case X86Local::MRM1m:
841 case X86Local::MRM2m:
842 case X86Local::MRM3m:
843 case X86Local::MRM4m:
844 case X86Local::MRM5m:
845 case X86Local::MRM6m:
846 case X86Local::MRM7m:
848 // Operand 1 is a memory operand (possibly SIB-extended)
849 // Operand 2 (optional) is an immediate or relocation.
850 unsigned kOp = (HasEVEX_K) ? 1:0;
851 unsigned Op4v = (HasVEX_4VPrefix) ? 1:0;
852 if (numPhysicalOperands < 1 + kOp + Op4v ||
853 numPhysicalOperands > 2 + kOp + Op4v)
854 llvm_unreachable("Unexpected number of operands for MRMnm");
857 HANDLE_OPERAND(vvvvRegister)
859 HANDLE_OPERAND(writemaskRegister)
860 HANDLE_OPERAND(memory)
861 HANDLE_OPTIONAL(relocation)
863 case X86Local::RawFrmImm8:
864 // operand 1 is a 16-bit immediate
865 // operand 2 is an 8-bit immediate
866 assert(numPhysicalOperands == 2 &&
867 "Unexpected number of operands for X86Local::RawFrmImm8");
868 HANDLE_OPERAND(immediate)
869 HANDLE_OPERAND(immediate)
871 case X86Local::RawFrmImm16:
872 // operand 1 is a 16-bit immediate
873 // operand 2 is a 16-bit immediate
874 HANDLE_OPERAND(immediate)
875 HANDLE_OPERAND(immediate)
877 case X86Local::MRM_F8:
878 if (Opcode == 0xc6) {
879 assert(numPhysicalOperands == 1 &&
880 "Unexpected number of operands for X86Local::MRM_F8");
881 HANDLE_OPERAND(immediate)
882 } else if (Opcode == 0xc7) {
883 assert(numPhysicalOperands == 1 &&
884 "Unexpected number of operands for X86Local::MRM_F8");
885 HANDLE_OPERAND(relocation)
888 case X86Local::MRMInitReg:
893 #undef HANDLE_OPERAND
894 #undef HANDLE_OPTIONAL
897 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
898 // Special cases where the LLVM tables are not complete
900 #define MAP(from, to) \
901 case X86Local::MRM_##from: \
902 filter = new ExactFilter(0x##from); \
905 OpcodeType opcodeType = (OpcodeType)-1;
907 ModRMFilter* filter = NULL;
908 uint8_t opcodeToSet = 0;
911 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
915 opcodeType = TWOBYTE;
919 if (needsModRMForDecode(Form))
920 filter = new ModFilter(isRegFormat(Form));
922 filter = new DumbFilter();
924 #define EXTENSION_TABLE(n) case 0x##n:
925 TWO_BYTE_EXTENSION_TABLES
926 #undef EXTENSION_TABLE
929 llvm_unreachable("Unhandled two-byte extended opcode");
930 case X86Local::MRM0r:
931 case X86Local::MRM1r:
932 case X86Local::MRM2r:
933 case X86Local::MRM3r:
934 case X86Local::MRM4r:
935 case X86Local::MRM5r:
936 case X86Local::MRM6r:
937 case X86Local::MRM7r:
938 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
940 case X86Local::MRM0m:
941 case X86Local::MRM1m:
942 case X86Local::MRM2m:
943 case X86Local::MRM3m:
944 case X86Local::MRM4m:
945 case X86Local::MRM5m:
946 case X86Local::MRM6m:
947 case X86Local::MRM7m:
948 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
954 opcodeToSet = Opcode;
959 opcodeType = THREEBYTE_38;
962 if (needsModRMForDecode(Form))
963 filter = new ModFilter(isRegFormat(Form));
965 filter = new DumbFilter();
967 #define EXTENSION_TABLE(n) case 0x##n:
968 THREE_BYTE_38_EXTENSION_TABLES
969 #undef EXTENSION_TABLE
972 llvm_unreachable("Unhandled two-byte extended opcode");
973 case X86Local::MRM0r:
974 case X86Local::MRM1r:
975 case X86Local::MRM2r:
976 case X86Local::MRM3r:
977 case X86Local::MRM4r:
978 case X86Local::MRM5r:
979 case X86Local::MRM6r:
980 case X86Local::MRM7r:
981 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
983 case X86Local::MRM0m:
984 case X86Local::MRM1m:
985 case X86Local::MRM2m:
986 case X86Local::MRM3m:
987 case X86Local::MRM4m:
988 case X86Local::MRM5m:
989 case X86Local::MRM6m:
990 case X86Local::MRM7m:
991 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
997 opcodeToSet = Opcode;
1000 case X86Local::TAXD:
1001 opcodeType = THREEBYTE_3A;
1002 if (needsModRMForDecode(Form))
1003 filter = new ModFilter(isRegFormat(Form));
1005 filter = new DumbFilter();
1006 opcodeToSet = Opcode;
1009 opcodeType = THREEBYTE_A6;
1010 if (needsModRMForDecode(Form))
1011 filter = new ModFilter(isRegFormat(Form));
1013 filter = new DumbFilter();
1014 opcodeToSet = Opcode;
1017 opcodeType = THREEBYTE_A7;
1018 if (needsModRMForDecode(Form))
1019 filter = new ModFilter(isRegFormat(Form));
1021 filter = new DumbFilter();
1022 opcodeToSet = Opcode;
1032 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1033 opcodeType = ONEBYTE;
1034 if (Form == X86Local::AddRegFrm) {
1035 Spec->modifierType = MODIFIER_MODRM;
1036 Spec->modifierBase = Opcode;
1037 filter = new AddRegEscapeFilter(Opcode);
1039 filter = new EscapeFilter(true, Opcode);
1041 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1045 opcodeType = ONEBYTE;
1047 #define EXTENSION_TABLE(n) case 0x##n:
1048 ONE_BYTE_EXTENSION_TABLES
1049 #undef EXTENSION_TABLE
1052 llvm_unreachable("Fell through the cracks of a single-byte "
1054 case X86Local::MRM0r:
1055 case X86Local::MRM1r:
1056 case X86Local::MRM2r:
1057 case X86Local::MRM3r:
1058 case X86Local::MRM4r:
1059 case X86Local::MRM5r:
1060 case X86Local::MRM6r:
1061 case X86Local::MRM7r:
1062 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1064 case X86Local::MRM0m:
1065 case X86Local::MRM1m:
1066 case X86Local::MRM2m:
1067 case X86Local::MRM3m:
1068 case X86Local::MRM4m:
1069 case X86Local::MRM5m:
1070 case X86Local::MRM6m:
1071 case X86Local::MRM7m:
1072 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1085 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1088 if (needsModRMForDecode(Form))
1089 filter = new ModFilter(isRegFormat(Form));
1091 filter = new DumbFilter();
1093 } // switch (Opcode)
1094 opcodeToSet = Opcode;
1095 } // switch (Prefix)
1097 assert(opcodeType != (OpcodeType)-1 &&
1098 "Opcode type not set");
1099 assert(filter && "Filter not set");
1101 if (Form == X86Local::AddRegFrm) {
1102 if(Spec->modifierType != MODIFIER_MODRM) {
1103 assert(opcodeToSet < 0xf9 &&
1104 "Not enough room for all ADDREG_FRM operands");
1106 uint8_t currentOpcode;
1108 for (currentOpcode = opcodeToSet;
1109 currentOpcode < opcodeToSet + 8;
1111 tables.setTableFields(opcodeType,
1115 UID, Is32Bit, IgnoresVEX_L);
1117 Spec->modifierType = MODIFIER_OPCODE;
1118 Spec->modifierBase = opcodeToSet;
1120 // modifierBase was set where MODIFIER_MODRM was set
1121 tables.setTableFields(opcodeType,
1125 UID, Is32Bit, IgnoresVEX_L);
1128 tables.setTableFields(opcodeType,
1132 UID, Is32Bit, IgnoresVEX_L);
1134 Spec->modifierType = MODIFIER_NONE;
1135 Spec->modifierBase = opcodeToSet;
1143 #define TYPE(str, type) if (s == str) return type;
1144 OperandType RecognizableInstr::typeFromString(const std::string &s,
1146 bool hasREX_WPrefix,
1147 bool hasOpSizePrefix) {
1149 // For SSE instructions, we ignore the OpSize prefix and force operand
1151 TYPE("GR16", TYPE_R16)
1152 TYPE("GR32", TYPE_R32)
1153 TYPE("GR64", TYPE_R64)
1155 if(hasREX_WPrefix) {
1156 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1158 TYPE("GR32", TYPE_R32)
1160 if(!hasOpSizePrefix) {
1161 // For instructions without an OpSize prefix, a declared 16-bit register or
1162 // immediate encoding is special.
1163 TYPE("GR16", TYPE_R16)
1164 TYPE("i16imm", TYPE_IMM16)
1166 TYPE("i16mem", TYPE_Mv)
1167 TYPE("i16imm", TYPE_IMMv)
1168 TYPE("i16i8imm", TYPE_IMMv)
1169 TYPE("GR16", TYPE_Rv)
1170 TYPE("i32mem", TYPE_Mv)
1171 TYPE("i32imm", TYPE_IMMv)
1172 TYPE("i32i8imm", TYPE_IMM32)
1173 TYPE("u32u8imm", TYPE_IMM32)
1174 TYPE("GR32", TYPE_Rv)
1175 TYPE("i64mem", TYPE_Mv)
1176 TYPE("i64i32imm", TYPE_IMM64)
1177 TYPE("i64i8imm", TYPE_IMM64)
1178 TYPE("GR64", TYPE_R64)
1179 TYPE("i8mem", TYPE_M8)
1180 TYPE("i8imm", TYPE_IMM8)
1181 TYPE("GR8", TYPE_R8)
1182 TYPE("VR128", TYPE_XMM128)
1183 TYPE("VR128X", TYPE_XMM128)
1184 TYPE("f128mem", TYPE_M128)
1185 TYPE("f256mem", TYPE_M256)
1186 TYPE("f512mem", TYPE_M512)
1187 TYPE("FR64", TYPE_XMM64)
1188 TYPE("FR64X", TYPE_XMM64)
1189 TYPE("f64mem", TYPE_M64FP)
1190 TYPE("sdmem", TYPE_M64FP)
1191 TYPE("FR32", TYPE_XMM32)
1192 TYPE("FR32X", TYPE_XMM32)
1193 TYPE("f32mem", TYPE_M32FP)
1194 TYPE("ssmem", TYPE_M32FP)
1195 TYPE("RST", TYPE_ST)
1196 TYPE("i128mem", TYPE_M128)
1197 TYPE("i256mem", TYPE_M256)
1198 TYPE("i512mem", TYPE_M512)
1199 TYPE("i64i32imm_pcrel", TYPE_REL64)
1200 TYPE("i16imm_pcrel", TYPE_REL16)
1201 TYPE("i32imm_pcrel", TYPE_REL32)
1202 TYPE("SSECC", TYPE_IMM3)
1203 TYPE("AVXCC", TYPE_IMM5)
1204 TYPE("brtarget", TYPE_RELv)
1205 TYPE("uncondbrtarget", TYPE_RELv)
1206 TYPE("brtarget8", TYPE_REL8)
1207 TYPE("f80mem", TYPE_M80FP)
1208 TYPE("lea32mem", TYPE_LEA)
1209 TYPE("lea64_32mem", TYPE_LEA)
1210 TYPE("lea64mem", TYPE_LEA)
1211 TYPE("VR64", TYPE_MM64)
1212 TYPE("i64imm", TYPE_IMMv)
1213 TYPE("opaque32mem", TYPE_M1616)
1214 TYPE("opaque48mem", TYPE_M1632)
1215 TYPE("opaque80mem", TYPE_M1664)
1216 TYPE("opaque512mem", TYPE_M512)
1217 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1218 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1219 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1220 TYPE("offset8", TYPE_MOFFS8)
1221 TYPE("offset16", TYPE_MOFFS16)
1222 TYPE("offset32", TYPE_MOFFS32)
1223 TYPE("offset64", TYPE_MOFFS64)
1224 TYPE("VR256", TYPE_XMM256)
1225 TYPE("VR256X", TYPE_XMM256)
1226 TYPE("VR512", TYPE_XMM512)
1227 TYPE("VK8", TYPE_VK8)
1228 TYPE("VK8WM", TYPE_VK8)
1229 TYPE("VK16", TYPE_VK16)
1230 TYPE("VK16WM", TYPE_VK16)
1231 TYPE("GR16_NOAX", TYPE_Rv)
1232 TYPE("GR32_NOAX", TYPE_Rv)
1233 TYPE("GR64_NOAX", TYPE_R64)
1234 TYPE("vx32mem", TYPE_M32)
1235 TYPE("vy32mem", TYPE_M32)
1236 TYPE("vz32mem", TYPE_M32)
1237 TYPE("vx64mem", TYPE_M64)
1238 TYPE("vy64mem", TYPE_M64)
1239 TYPE("vy64xmem", TYPE_M64)
1240 TYPE("vz64mem", TYPE_M64)
1241 errs() << "Unhandled type string " << s << "\n";
1242 llvm_unreachable("Unhandled type string");
1246 #define ENCODING(str, encoding) if (s == str) return encoding;
1247 OperandEncoding RecognizableInstr::immediateEncodingFromString
1248 (const std::string &s,
1249 bool hasOpSizePrefix) {
1250 if(!hasOpSizePrefix) {
1251 // For instructions without an OpSize prefix, a declared 16-bit register or
1252 // immediate encoding is special.
1253 ENCODING("i16imm", ENCODING_IW)
1255 ENCODING("i32i8imm", ENCODING_IB)
1256 ENCODING("u32u8imm", ENCODING_IB)
1257 ENCODING("SSECC", ENCODING_IB)
1258 ENCODING("AVXCC", ENCODING_IB)
1259 ENCODING("i16imm", ENCODING_Iv)
1260 ENCODING("i16i8imm", ENCODING_IB)
1261 ENCODING("i32imm", ENCODING_Iv)
1262 ENCODING("i64i32imm", ENCODING_ID)
1263 ENCODING("i64i8imm", ENCODING_IB)
1264 ENCODING("i8imm", ENCODING_IB)
1265 // This is not a typo. Instructions like BLENDVPD put
1266 // register IDs in 8-bit immediates nowadays.
1267 ENCODING("FR32", ENCODING_IB)
1268 ENCODING("FR64", ENCODING_IB)
1269 ENCODING("VR128", ENCODING_IB)
1270 ENCODING("VR256", ENCODING_IB)
1271 ENCODING("FR32X", ENCODING_IB)
1272 ENCODING("FR64X", ENCODING_IB)
1273 ENCODING("VR128X", ENCODING_IB)
1274 ENCODING("VR256X", ENCODING_IB)
1275 ENCODING("VR512", ENCODING_IB)
1276 errs() << "Unhandled immediate encoding " << s << "\n";
1277 llvm_unreachable("Unhandled immediate encoding");
1280 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1281 (const std::string &s,
1282 bool hasOpSizePrefix) {
1283 ENCODING("GR16", ENCODING_RM)
1284 ENCODING("GR32", ENCODING_RM)
1285 ENCODING("GR64", ENCODING_RM)
1286 ENCODING("GR8", ENCODING_RM)
1287 ENCODING("VR128", ENCODING_RM)
1288 ENCODING("VR128X", ENCODING_RM)
1289 ENCODING("FR64", ENCODING_RM)
1290 ENCODING("FR32", ENCODING_RM)
1291 ENCODING("FR64X", ENCODING_RM)
1292 ENCODING("FR32X", ENCODING_RM)
1293 ENCODING("VR64", ENCODING_RM)
1294 ENCODING("VR256", ENCODING_RM)
1295 ENCODING("VR256X", ENCODING_RM)
1296 ENCODING("VR512", ENCODING_RM)
1297 ENCODING("VK8", ENCODING_RM)
1298 ENCODING("VK16", ENCODING_RM)
1299 errs() << "Unhandled R/M register encoding " << s << "\n";
1300 llvm_unreachable("Unhandled R/M register encoding");
1303 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1304 (const std::string &s,
1305 bool hasOpSizePrefix) {
1306 ENCODING("GR16", ENCODING_REG)
1307 ENCODING("GR32", ENCODING_REG)
1308 ENCODING("GR64", ENCODING_REG)
1309 ENCODING("GR8", ENCODING_REG)
1310 ENCODING("VR128", ENCODING_REG)
1311 ENCODING("FR64", ENCODING_REG)
1312 ENCODING("FR32", ENCODING_REG)
1313 ENCODING("VR64", ENCODING_REG)
1314 ENCODING("SEGMENT_REG", ENCODING_REG)
1315 ENCODING("DEBUG_REG", ENCODING_REG)
1316 ENCODING("CONTROL_REG", ENCODING_REG)
1317 ENCODING("VR256", ENCODING_REG)
1318 ENCODING("VR256X", ENCODING_REG)
1319 ENCODING("VR128X", ENCODING_REG)
1320 ENCODING("FR64X", ENCODING_REG)
1321 ENCODING("FR32X", ENCODING_REG)
1322 ENCODING("VR512", ENCODING_REG)
1323 ENCODING("VK8", ENCODING_REG)
1324 ENCODING("VK16", ENCODING_REG)
1325 ENCODING("VK8WM", ENCODING_REG)
1326 ENCODING("VK16WM", ENCODING_REG)
1327 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1328 llvm_unreachable("Unhandled reg/opcode register encoding");
1331 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1332 (const std::string &s,
1333 bool hasOpSizePrefix) {
1334 ENCODING("GR32", ENCODING_VVVV)
1335 ENCODING("GR64", ENCODING_VVVV)
1336 ENCODING("FR32", ENCODING_VVVV)
1337 ENCODING("FR64", ENCODING_VVVV)
1338 ENCODING("VR128", ENCODING_VVVV)
1339 ENCODING("VR256", ENCODING_VVVV)
1340 ENCODING("FR32X", ENCODING_VVVV)
1341 ENCODING("FR64X", ENCODING_VVVV)
1342 ENCODING("VR128X", ENCODING_VVVV)
1343 ENCODING("VR256X", ENCODING_VVVV)
1344 ENCODING("VR512", ENCODING_VVVV)
1345 ENCODING("VK8", ENCODING_VVVV)
1346 ENCODING("VK16", ENCODING_VVVV)
1347 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1348 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1351 OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1352 (const std::string &s,
1353 bool hasOpSizePrefix) {
1354 ENCODING("VK8WM", ENCODING_WRITEMASK)
1355 ENCODING("VK16WM", ENCODING_WRITEMASK)
1356 errs() << "Unhandled mask register encoding " << s << "\n";
1357 llvm_unreachable("Unhandled mask register encoding");
1360 OperandEncoding RecognizableInstr::memoryEncodingFromString
1361 (const std::string &s,
1362 bool hasOpSizePrefix) {
1363 ENCODING("i16mem", ENCODING_RM)
1364 ENCODING("i32mem", ENCODING_RM)
1365 ENCODING("i64mem", ENCODING_RM)
1366 ENCODING("i8mem", ENCODING_RM)
1367 ENCODING("ssmem", ENCODING_RM)
1368 ENCODING("sdmem", ENCODING_RM)
1369 ENCODING("f128mem", ENCODING_RM)
1370 ENCODING("f256mem", ENCODING_RM)
1371 ENCODING("f512mem", ENCODING_RM)
1372 ENCODING("f64mem", ENCODING_RM)
1373 ENCODING("f32mem", ENCODING_RM)
1374 ENCODING("i128mem", ENCODING_RM)
1375 ENCODING("i256mem", ENCODING_RM)
1376 ENCODING("i512mem", ENCODING_RM)
1377 ENCODING("f80mem", ENCODING_RM)
1378 ENCODING("lea32mem", ENCODING_RM)
1379 ENCODING("lea64_32mem", ENCODING_RM)
1380 ENCODING("lea64mem", ENCODING_RM)
1381 ENCODING("opaque32mem", ENCODING_RM)
1382 ENCODING("opaque48mem", ENCODING_RM)
1383 ENCODING("opaque80mem", ENCODING_RM)
1384 ENCODING("opaque512mem", ENCODING_RM)
1385 ENCODING("vx32mem", ENCODING_RM)
1386 ENCODING("vy32mem", ENCODING_RM)
1387 ENCODING("vz32mem", ENCODING_RM)
1388 ENCODING("vx64mem", ENCODING_RM)
1389 ENCODING("vy64mem", ENCODING_RM)
1390 ENCODING("vy64xmem", ENCODING_RM)
1391 ENCODING("vz64mem", ENCODING_RM)
1392 errs() << "Unhandled memory encoding " << s << "\n";
1393 llvm_unreachable("Unhandled memory encoding");
1396 OperandEncoding RecognizableInstr::relocationEncodingFromString
1397 (const std::string &s,
1398 bool hasOpSizePrefix) {
1399 if(!hasOpSizePrefix) {
1400 // For instructions without an OpSize prefix, a declared 16-bit register or
1401 // immediate encoding is special.
1402 ENCODING("i16imm", ENCODING_IW)
1404 ENCODING("i16imm", ENCODING_Iv)
1405 ENCODING("i16i8imm", ENCODING_IB)
1406 ENCODING("i32imm", ENCODING_Iv)
1407 ENCODING("i32i8imm", ENCODING_IB)
1408 ENCODING("i64i32imm", ENCODING_ID)
1409 ENCODING("i64i8imm", ENCODING_IB)
1410 ENCODING("i8imm", ENCODING_IB)
1411 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1412 ENCODING("i16imm_pcrel", ENCODING_IW)
1413 ENCODING("i32imm_pcrel", ENCODING_ID)
1414 ENCODING("brtarget", ENCODING_Iv)
1415 ENCODING("brtarget8", ENCODING_IB)
1416 ENCODING("i64imm", ENCODING_IO)
1417 ENCODING("offset8", ENCODING_Ia)
1418 ENCODING("offset16", ENCODING_Ia)
1419 ENCODING("offset32", ENCODING_Ia)
1420 ENCODING("offset64", ENCODING_Ia)
1421 errs() << "Unhandled relocation encoding " << s << "\n";
1422 llvm_unreachable("Unhandled relocation encoding");
1425 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1426 (const std::string &s,
1427 bool hasOpSizePrefix) {
1428 ENCODING("RST", ENCODING_I)
1429 ENCODING("GR32", ENCODING_Rv)
1430 ENCODING("GR64", ENCODING_RO)
1431 ENCODING("GR16", ENCODING_Rv)
1432 ENCODING("GR8", ENCODING_RB)
1433 ENCODING("GR16_NOAX", ENCODING_Rv)
1434 ENCODING("GR32_NOAX", ENCODING_Rv)
1435 ENCODING("GR64_NOAX", ENCODING_RO)
1436 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1437 llvm_unreachable("Unhandled opcode modifier encoding");