1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
51 // A clone of X86 since we can't depend on something that is generated.
61 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
62 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
63 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
64 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
68 #define MAP(from, to) MRM_##from = to,
77 D8 = 3, D9 = 4, DA = 5, DB = 6,
78 DC = 7, DD = 8, DE = 9, DF = 10,
81 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
85 // If rows are added to the opcode extension tables, then corresponding entries
86 // must be added here.
88 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
89 // that byte to ONE_BYTE_EXTENSION_TABLES.
91 // If the row corresponds to two bytes where the first is 0f, add an entry for
92 // the second byte to TWO_BYTE_EXTENSION_TABLES.
94 // If the row corresponds to some other set of bytes, you will need to modify
95 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
96 // to the X86 TD files, except in two cases: if the first two bytes of such a
97 // new combination are 0f 38 or 0f 3a, you just have to add maps called
98 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
99 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
100 // in RecognizableInstr::emitDecodePath().
102 #define ONE_BYTE_EXTENSION_TABLES \
103 EXTENSION_TABLE(80) \
104 EXTENSION_TABLE(81) \
105 EXTENSION_TABLE(82) \
106 EXTENSION_TABLE(83) \
107 EXTENSION_TABLE(8f) \
108 EXTENSION_TABLE(c0) \
109 EXTENSION_TABLE(c1) \
110 EXTENSION_TABLE(c6) \
111 EXTENSION_TABLE(c7) \
112 EXTENSION_TABLE(d0) \
113 EXTENSION_TABLE(d1) \
114 EXTENSION_TABLE(d2) \
115 EXTENSION_TABLE(d3) \
116 EXTENSION_TABLE(f6) \
117 EXTENSION_TABLE(f7) \
118 EXTENSION_TABLE(fe) \
121 #define TWO_BYTE_EXTENSION_TABLES \
122 EXTENSION_TABLE(00) \
123 EXTENSION_TABLE(01) \
124 EXTENSION_TABLE(18) \
125 EXTENSION_TABLE(71) \
126 EXTENSION_TABLE(72) \
127 EXTENSION_TABLE(73) \
128 EXTENSION_TABLE(ae) \
129 EXTENSION_TABLE(ba) \
132 #define THREE_BYTE_38_EXTENSION_TABLES \
135 using namespace X86Disassembler;
137 /// needsModRMForDecode - Indicates whether a particular instruction requires a
138 /// ModR/M byte for the instruction to be properly decoded. For example, a
139 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
142 /// @param form - The form of the instruction.
143 /// @return - true if the form implies that a ModR/M byte is required, false
145 static bool needsModRMForDecode(uint8_t form) {
146 if (form == X86Local::MRMDestReg ||
147 form == X86Local::MRMDestMem ||
148 form == X86Local::MRMSrcReg ||
149 form == X86Local::MRMSrcMem ||
150 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
151 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
157 /// isRegFormat - Indicates whether a particular form requires the Mod field of
158 /// the ModR/M byte to be 0b11.
160 /// @param form - The form of the instruction.
161 /// @return - true if the form implies that Mod must be 0b11, false
163 static bool isRegFormat(uint8_t form) {
164 if (form == X86Local::MRMDestReg ||
165 form == X86Local::MRMSrcReg ||
166 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
172 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
173 /// Useful for switch statements and the like.
175 /// @param init - A reference to the BitsInit to be decoded.
176 /// @return - The field, with the first bit in the BitsInit as the lowest
178 static uint8_t byteFromBitsInit(BitsInit &init) {
179 int width = init.getNumBits();
181 assert(width <= 8 && "Field is too large for uint8_t!");
188 for (index = 0; index < width; index++) {
189 if (static_cast<BitInit*>(init.getBit(index))->getValue())
198 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
199 /// name of the field.
201 /// @param rec - The record from which to extract the value.
202 /// @param name - The name of the field in the record.
203 /// @return - The field, as translated by byteFromBitsInit().
204 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
205 BitsInit* bits = rec->getValueAsBitsInit(name);
206 return byteFromBitsInit(*bits);
209 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
210 const CodeGenInstruction &insn,
215 Name = Rec->getName();
216 Spec = &tables.specForUID(UID);
218 if (!Rec->isSubClassOf("X86Inst")) {
219 ShouldBeEmitted = false;
223 Prefix = byteFromRec(Rec, "Prefix");
224 Opcode = byteFromRec(Rec, "Opcode");
225 Form = byteFromRec(Rec, "FormBits");
226 SegOvr = byteFromRec(Rec, "SegOvrBits");
228 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
229 HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix");
230 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
231 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
232 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
233 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
234 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
235 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
236 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
237 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
238 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
240 Name = Rec->getName();
241 AsmString = Rec->getValueAsString("AsmString");
243 Operands = &insn.Operands.OperandList;
245 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
246 (Name.find("CRC32") != Name.npos);
247 HasFROperands = hasFROperands();
248 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L");
250 // Check for 64-bit inst which does not require REX
253 // FIXME: Is there some better way to check for In64BitMode?
254 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
255 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
256 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
260 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
265 // FIXME: These instructions aren't marked as 64-bit in any way
266 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
267 Rec->getName() == "MASKMOVDQU64" ||
268 Rec->getName() == "POPFS64" ||
269 Rec->getName() == "POPGS64" ||
270 Rec->getName() == "PUSHFS64" ||
271 Rec->getName() == "PUSHGS64" ||
272 Rec->getName() == "REX64_PREFIX" ||
273 Rec->getName().find("MOV64") != Name.npos ||
274 Rec->getName().find("PUSH64") != Name.npos ||
275 Rec->getName().find("POP64") != Name.npos;
277 ShouldBeEmitted = true;
280 void RecognizableInstr::processInstr(DisassemblerTables &tables,
281 const CodeGenInstruction &insn,
284 // Ignore "asm parser only" instructions.
285 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
288 RecognizableInstr recogInstr(tables, insn, uid);
290 recogInstr.emitInstructionSpecifier(tables);
292 if (recogInstr.shouldBeEmitted())
293 recogInstr.emitDecodePath(tables);
296 InstructionContext RecognizableInstr::insnContext() const {
297 InstructionContext insnContext;
299 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
300 if (HasVEX_LPrefix && HasVEX_WPrefix) {
302 insnContext = IC_VEX_L_W_OPSIZE;
304 llvm_unreachable("Don't support VEX.L and VEX.W together");
305 } else if (HasOpSizePrefix && HasVEX_LPrefix)
306 insnContext = IC_VEX_L_OPSIZE;
307 else if (HasOpSizePrefix && HasVEX_WPrefix)
308 insnContext = IC_VEX_W_OPSIZE;
309 else if (HasOpSizePrefix)
310 insnContext = IC_VEX_OPSIZE;
311 else if (HasVEX_LPrefix &&
312 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
313 insnContext = IC_VEX_L_XS;
314 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
315 Prefix == X86Local::T8XD ||
316 Prefix == X86Local::TAXD))
317 insnContext = IC_VEX_L_XD;
318 else if (HasVEX_WPrefix &&
319 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
320 insnContext = IC_VEX_W_XS;
321 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
322 Prefix == X86Local::T8XD ||
323 Prefix == X86Local::TAXD))
324 insnContext = IC_VEX_W_XD;
325 else if (HasVEX_WPrefix)
326 insnContext = IC_VEX_W;
327 else if (HasVEX_LPrefix)
328 insnContext = IC_VEX_L;
329 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
330 Prefix == X86Local::TAXD)
331 insnContext = IC_VEX_XD;
332 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
333 insnContext = IC_VEX_XS;
335 insnContext = IC_VEX;
336 } else if (Is64Bit || HasREX_WPrefix) {
337 if (HasREX_WPrefix && HasOpSizePrefix)
338 insnContext = IC_64BIT_REXW_OPSIZE;
339 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
340 Prefix == X86Local::T8XD ||
341 Prefix == X86Local::TAXD))
342 insnContext = IC_64BIT_XD_OPSIZE;
343 else if (HasOpSizePrefix &&
344 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
345 insnContext = IC_64BIT_XS_OPSIZE;
346 else if (HasOpSizePrefix)
347 insnContext = IC_64BIT_OPSIZE;
348 else if (HasAdSizePrefix)
349 insnContext = IC_64BIT_ADSIZE;
350 else if (HasREX_WPrefix &&
351 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
352 insnContext = IC_64BIT_REXW_XS;
353 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
354 Prefix == X86Local::T8XD ||
355 Prefix == X86Local::TAXD))
356 insnContext = IC_64BIT_REXW_XD;
357 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
358 Prefix == X86Local::TAXD)
359 insnContext = IC_64BIT_XD;
360 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
361 insnContext = IC_64BIT_XS;
362 else if (HasREX_WPrefix)
363 insnContext = IC_64BIT_REXW;
365 insnContext = IC_64BIT;
367 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
368 Prefix == X86Local::T8XD ||
369 Prefix == X86Local::TAXD))
370 insnContext = IC_XD_OPSIZE;
371 else if (HasOpSizePrefix &&
372 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
373 insnContext = IC_XS_OPSIZE;
374 else if (HasOpSizePrefix)
375 insnContext = IC_OPSIZE;
376 else if (HasAdSizePrefix)
377 insnContext = IC_ADSIZE;
378 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
379 Prefix == X86Local::TAXD)
381 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
382 Prefix == X86Local::REP)
391 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
396 // Filter out intrinsics
398 assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
400 if (Form == X86Local::Pseudo ||
401 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
402 return FILTER_STRONG;
405 // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
406 // printed as a separate "instruction".
408 if (Name.find("_Int") != Name.npos ||
409 Name.find("Int_") != Name.npos)
410 return FILTER_STRONG;
412 // Filter out instructions with segment override prefixes.
413 // They're too messy to handle now and we'll special case them if needed.
416 return FILTER_STRONG;
424 // Filter out instructions with a LOCK prefix;
425 // prefer forms that do not have the prefix
429 // Filter out alternate forms of AVX instructions
430 if (Name.find("_alt") != Name.npos ||
431 Name.find("XrYr") != Name.npos ||
432 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
433 Name.find("_64mr") != Name.npos ||
434 Name.find("Xrr") != Name.npos ||
435 Name.find("rr64") != Name.npos)
440 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
442 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
445 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
447 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
449 if (Name.find("Fs") != Name.npos)
451 if (Name == "PUSH64i16" ||
452 Name == "MOVPQI2QImr" ||
453 Name == "VMOVPQI2QImr" ||
454 Name == "MMX_MOVD64rrv164" ||
455 Name == "MOV64ri64i32" ||
456 Name == "VMASKMOVDQU64" ||
457 Name == "VEXTRACTPSrr64" ||
458 Name == "VMOVQd64rr" ||
459 Name == "VMOVQs64rr")
462 if (HasFROperands && Name.find("MOV") != Name.npos &&
463 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
464 (Name.find("to") != Name.npos)))
465 return FILTER_STRONG;
467 return FILTER_NORMAL;
470 bool RecognizableInstr::hasFROperands() const {
471 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
472 unsigned numOperands = OperandList.size();
474 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
475 const std::string &recName = OperandList[operandIndex].Rec->getName();
477 if (recName.find("FR") != recName.npos)
483 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
484 unsigned &physicalOperandIndex,
485 unsigned &numPhysicalOperands,
486 const unsigned *operandMapping,
487 OperandEncoding (*encodingFromString)
489 bool hasOpSizePrefix)) {
491 if (physicalOperandIndex >= numPhysicalOperands)
494 assert(physicalOperandIndex < numPhysicalOperands);
497 while (operandMapping[operandIndex] != operandIndex) {
498 Spec->operands[operandIndex].encoding = ENCODING_DUP;
499 Spec->operands[operandIndex].type =
500 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
504 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
506 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
508 Spec->operands[operandIndex].type = typeFromString(typeName,
514 ++physicalOperandIndex;
517 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
520 if (!ShouldBeEmitted)
525 Spec->filtered = true;
528 ShouldBeEmitted = false;
534 Spec->insnContext = insnContext();
536 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
538 unsigned numOperands = OperandList.size();
539 unsigned numPhysicalOperands = 0;
541 // operandMapping maps from operands in OperandList to their originals.
542 // If operandMapping[i] != i, then the entry is a duplicate.
543 unsigned operandMapping[X86_MAX_OPERANDS];
544 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
546 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
547 if (OperandList[operandIndex].Constraints.size()) {
548 const CGIOperandList::ConstraintInfo &Constraint =
549 OperandList[operandIndex].Constraints[0];
550 if (Constraint.isTied()) {
551 operandMapping[operandIndex] = operandIndex;
552 operandMapping[Constraint.getTiedOperand()] = operandIndex;
554 ++numPhysicalOperands;
555 operandMapping[operandIndex] = operandIndex;
558 ++numPhysicalOperands;
559 operandMapping[operandIndex] = operandIndex;
563 #define HANDLE_OPERAND(class) \
564 handleOperand(false, \
566 physicalOperandIndex, \
567 numPhysicalOperands, \
569 class##EncodingFromString);
571 #define HANDLE_OPTIONAL(class) \
572 handleOperand(true, \
574 physicalOperandIndex, \
575 numPhysicalOperands, \
577 class##EncodingFromString);
579 // operandIndex should always be < numOperands
580 unsigned operandIndex = 0;
581 // physicalOperandIndex should always be < numPhysicalOperands
582 unsigned physicalOperandIndex = 0;
585 case X86Local::RawFrm:
586 // Operand 1 (optional) is an address or immediate.
587 // Operand 2 (optional) is an immediate.
588 assert(numPhysicalOperands <= 2 &&
589 "Unexpected number of operands for RawFrm");
590 HANDLE_OPTIONAL(relocation)
591 HANDLE_OPTIONAL(immediate)
593 case X86Local::AddRegFrm:
594 // Operand 1 is added to the opcode.
595 // Operand 2 (optional) is an address.
596 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
597 "Unexpected number of operands for AddRegFrm");
598 HANDLE_OPERAND(opcodeModifier)
599 HANDLE_OPTIONAL(relocation)
601 case X86Local::MRMDestReg:
602 // Operand 1 is a register operand in the R/M field.
603 // Operand 2 is a register operand in the Reg/Opcode field.
604 // - In AVX, there is a register operand in the VEX.vvvv field here -
605 // Operand 3 (optional) is an immediate.
607 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
608 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
610 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
611 "Unexpected number of operands for MRMDestRegFrm");
613 HANDLE_OPERAND(rmRegister)
616 // FIXME: In AVX, the register below becomes the one encoded
617 // in ModRMVEX and the one above the one in the VEX.VVVV field
618 HANDLE_OPERAND(vvvvRegister)
620 HANDLE_OPERAND(roRegister)
621 HANDLE_OPTIONAL(immediate)
623 case X86Local::MRMDestMem:
624 // Operand 1 is a memory operand (possibly SIB-extended)
625 // Operand 2 is a register operand in the Reg/Opcode field.
626 // - In AVX, there is a register operand in the VEX.vvvv field here -
627 // Operand 3 (optional) is an immediate.
629 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
630 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
632 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
633 "Unexpected number of operands for MRMDestMemFrm");
634 HANDLE_OPERAND(memory)
637 // FIXME: In AVX, the register below becomes the one encoded
638 // in ModRMVEX and the one above the one in the VEX.VVVV field
639 HANDLE_OPERAND(vvvvRegister)
641 HANDLE_OPERAND(roRegister)
642 HANDLE_OPTIONAL(immediate)
644 case X86Local::MRMSrcReg:
645 // Operand 1 is a register operand in the Reg/Opcode field.
646 // Operand 2 is a register operand in the R/M field.
647 // - In AVX, there is a register operand in the VEX.vvvv field here -
648 // Operand 3 (optional) is an immediate.
649 // Operand 4 (optional) is an immediate.
651 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
652 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
653 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
655 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
656 "Unexpected number of operands for MRMSrcRegFrm");
658 HANDLE_OPERAND(roRegister)
661 // FIXME: In AVX, the register below becomes the one encoded
662 // in ModRMVEX and the one above the one in the VEX.VVVV field
663 HANDLE_OPERAND(vvvvRegister)
666 HANDLE_OPERAND(immediate)
668 HANDLE_OPERAND(rmRegister)
670 if (HasVEX_4VOp3Prefix)
671 HANDLE_OPERAND(vvvvRegister)
673 if (!HasMemOp4Prefix)
674 HANDLE_OPTIONAL(immediate)
675 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
676 HANDLE_OPTIONAL(immediate)
678 case X86Local::MRMSrcMem:
679 // Operand 1 is a register operand in the Reg/Opcode field.
680 // Operand 2 is a memory operand (possibly SIB-extended)
681 // - In AVX, there is a register operand in the VEX.vvvv field here -
682 // Operand 3 (optional) is an immediate.
684 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
685 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
686 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
688 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
689 "Unexpected number of operands for MRMSrcMemFrm");
691 HANDLE_OPERAND(roRegister)
694 // FIXME: In AVX, the register below becomes the one encoded
695 // in ModRMVEX and the one above the one in the VEX.VVVV field
696 HANDLE_OPERAND(vvvvRegister)
699 HANDLE_OPERAND(immediate)
701 HANDLE_OPERAND(memory)
703 if (HasVEX_4VOp3Prefix)
704 HANDLE_OPERAND(vvvvRegister)
706 if (!HasMemOp4Prefix)
707 HANDLE_OPTIONAL(immediate)
708 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
710 case X86Local::MRM0r:
711 case X86Local::MRM1r:
712 case X86Local::MRM2r:
713 case X86Local::MRM3r:
714 case X86Local::MRM4r:
715 case X86Local::MRM5r:
716 case X86Local::MRM6r:
717 case X86Local::MRM7r:
718 // Operand 1 is a register operand in the R/M field.
719 // Operand 2 (optional) is an immediate or relocation.
720 // Operand 3 (optional) is an immediate.
722 assert(numPhysicalOperands <= 3 &&
723 "Unexpected number of operands for MRMnRFrm with VEX_4V");
725 assert(numPhysicalOperands <= 3 &&
726 "Unexpected number of operands for MRMnRFrm");
728 HANDLE_OPERAND(vvvvRegister)
729 HANDLE_OPTIONAL(rmRegister)
730 HANDLE_OPTIONAL(relocation)
731 HANDLE_OPTIONAL(immediate)
733 case X86Local::MRM0m:
734 case X86Local::MRM1m:
735 case X86Local::MRM2m:
736 case X86Local::MRM3m:
737 case X86Local::MRM4m:
738 case X86Local::MRM5m:
739 case X86Local::MRM6m:
740 case X86Local::MRM7m:
741 // Operand 1 is a memory operand (possibly SIB-extended)
742 // Operand 2 (optional) is an immediate or relocation.
744 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
745 "Unexpected number of operands for MRMnMFrm");
747 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
748 "Unexpected number of operands for MRMnMFrm");
750 HANDLE_OPERAND(vvvvRegister)
751 HANDLE_OPERAND(memory)
752 HANDLE_OPTIONAL(relocation)
754 case X86Local::RawFrmImm8:
755 // operand 1 is a 16-bit immediate
756 // operand 2 is an 8-bit immediate
757 assert(numPhysicalOperands == 2 &&
758 "Unexpected number of operands for X86Local::RawFrmImm8");
759 HANDLE_OPERAND(immediate)
760 HANDLE_OPERAND(immediate)
762 case X86Local::RawFrmImm16:
763 // operand 1 is a 16-bit immediate
764 // operand 2 is a 16-bit immediate
765 HANDLE_OPERAND(immediate)
766 HANDLE_OPERAND(immediate)
768 case X86Local::MRMInitReg:
773 #undef HANDLE_OPERAND
774 #undef HANDLE_OPTIONAL
777 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
778 // Special cases where the LLVM tables are not complete
780 #define MAP(from, to) \
781 case X86Local::MRM_##from: \
782 filter = new ExactFilter(0x##from); \
785 OpcodeType opcodeType = (OpcodeType)-1;
787 ModRMFilter* filter = NULL;
788 uint8_t opcodeToSet = 0;
791 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
795 opcodeType = TWOBYTE;
799 if (needsModRMForDecode(Form))
800 filter = new ModFilter(isRegFormat(Form));
802 filter = new DumbFilter();
804 #define EXTENSION_TABLE(n) case 0x##n:
805 TWO_BYTE_EXTENSION_TABLES
806 #undef EXTENSION_TABLE
809 llvm_unreachable("Unhandled two-byte extended opcode");
810 case X86Local::MRM0r:
811 case X86Local::MRM1r:
812 case X86Local::MRM2r:
813 case X86Local::MRM3r:
814 case X86Local::MRM4r:
815 case X86Local::MRM5r:
816 case X86Local::MRM6r:
817 case X86Local::MRM7r:
818 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
820 case X86Local::MRM0m:
821 case X86Local::MRM1m:
822 case X86Local::MRM2m:
823 case X86Local::MRM3m:
824 case X86Local::MRM4m:
825 case X86Local::MRM5m:
826 case X86Local::MRM6m:
827 case X86Local::MRM7m:
828 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
834 opcodeToSet = Opcode;
839 opcodeType = THREEBYTE_38;
842 if (needsModRMForDecode(Form))
843 filter = new ModFilter(isRegFormat(Form));
845 filter = new DumbFilter();
847 #define EXTENSION_TABLE(n) case 0x##n:
848 THREE_BYTE_38_EXTENSION_TABLES
849 #undef EXTENSION_TABLE
852 llvm_unreachable("Unhandled two-byte extended opcode");
853 case X86Local::MRM0r:
854 case X86Local::MRM1r:
855 case X86Local::MRM2r:
856 case X86Local::MRM3r:
857 case X86Local::MRM4r:
858 case X86Local::MRM5r:
859 case X86Local::MRM6r:
860 case X86Local::MRM7r:
861 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
863 case X86Local::MRM0m:
864 case X86Local::MRM1m:
865 case X86Local::MRM2m:
866 case X86Local::MRM3m:
867 case X86Local::MRM4m:
868 case X86Local::MRM5m:
869 case X86Local::MRM6m:
870 case X86Local::MRM7m:
871 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
877 opcodeToSet = Opcode;
881 opcodeType = THREEBYTE_3A;
882 if (needsModRMForDecode(Form))
883 filter = new ModFilter(isRegFormat(Form));
885 filter = new DumbFilter();
886 opcodeToSet = Opcode;
889 opcodeType = THREEBYTE_A6;
890 if (needsModRMForDecode(Form))
891 filter = new ModFilter(isRegFormat(Form));
893 filter = new DumbFilter();
894 opcodeToSet = Opcode;
897 opcodeType = THREEBYTE_A7;
898 if (needsModRMForDecode(Form))
899 filter = new ModFilter(isRegFormat(Form));
901 filter = new DumbFilter();
902 opcodeToSet = Opcode;
912 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
913 opcodeType = ONEBYTE;
914 if (Form == X86Local::AddRegFrm) {
915 Spec->modifierType = MODIFIER_MODRM;
916 Spec->modifierBase = Opcode;
917 filter = new AddRegEscapeFilter(Opcode);
919 filter = new EscapeFilter(true, Opcode);
921 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
925 opcodeType = ONEBYTE;
927 #define EXTENSION_TABLE(n) case 0x##n:
928 ONE_BYTE_EXTENSION_TABLES
929 #undef EXTENSION_TABLE
932 llvm_unreachable("Fell through the cracks of a single-byte "
934 case X86Local::MRM0r:
935 case X86Local::MRM1r:
936 case X86Local::MRM2r:
937 case X86Local::MRM3r:
938 case X86Local::MRM4r:
939 case X86Local::MRM5r:
940 case X86Local::MRM6r:
941 case X86Local::MRM7r:
942 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
944 case X86Local::MRM0m:
945 case X86Local::MRM1m:
946 case X86Local::MRM2m:
947 case X86Local::MRM3m:
948 case X86Local::MRM4m:
949 case X86Local::MRM5m:
950 case X86Local::MRM6m:
951 case X86Local::MRM7m:
952 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
965 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
968 if (needsModRMForDecode(Form))
969 filter = new ModFilter(isRegFormat(Form));
971 filter = new DumbFilter();
974 opcodeToSet = Opcode;
977 assert(opcodeType != (OpcodeType)-1 &&
978 "Opcode type not set");
979 assert(filter && "Filter not set");
981 if (Form == X86Local::AddRegFrm) {
982 if(Spec->modifierType != MODIFIER_MODRM) {
983 assert(opcodeToSet < 0xf9 &&
984 "Not enough room for all ADDREG_FRM operands");
986 uint8_t currentOpcode;
988 for (currentOpcode = opcodeToSet;
989 currentOpcode < opcodeToSet + 8;
991 tables.setTableFields(opcodeType,
995 UID, Is32Bit, IgnoresVEX_L);
997 Spec->modifierType = MODIFIER_OPCODE;
998 Spec->modifierBase = opcodeToSet;
1000 // modifierBase was set where MODIFIER_MODRM was set
1001 tables.setTableFields(opcodeType,
1005 UID, Is32Bit, IgnoresVEX_L);
1008 tables.setTableFields(opcodeType,
1012 UID, Is32Bit, IgnoresVEX_L);
1014 Spec->modifierType = MODIFIER_NONE;
1015 Spec->modifierBase = opcodeToSet;
1023 #define TYPE(str, type) if (s == str) return type;
1024 OperandType RecognizableInstr::typeFromString(const std::string &s,
1026 bool hasREX_WPrefix,
1027 bool hasOpSizePrefix) {
1029 // For SSE instructions, we ignore the OpSize prefix and force operand
1031 TYPE("GR16", TYPE_R16)
1032 TYPE("GR32", TYPE_R32)
1033 TYPE("GR64", TYPE_R64)
1035 if(hasREX_WPrefix) {
1036 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1038 TYPE("GR32", TYPE_R32)
1040 if(!hasOpSizePrefix) {
1041 // For instructions without an OpSize prefix, a declared 16-bit register or
1042 // immediate encoding is special.
1043 TYPE("GR16", TYPE_R16)
1044 TYPE("i16imm", TYPE_IMM16)
1046 TYPE("i16mem", TYPE_Mv)
1047 TYPE("i16imm", TYPE_IMMv)
1048 TYPE("i16i8imm", TYPE_IMMv)
1049 TYPE("GR16", TYPE_Rv)
1050 TYPE("i32mem", TYPE_Mv)
1051 TYPE("i32imm", TYPE_IMMv)
1052 TYPE("i32i8imm", TYPE_IMM32)
1053 TYPE("u32u8imm", TYPE_IMM32)
1054 TYPE("GR32", TYPE_Rv)
1055 TYPE("i64mem", TYPE_Mv)
1056 TYPE("i64i32imm", TYPE_IMM64)
1057 TYPE("i64i8imm", TYPE_IMM64)
1058 TYPE("GR64", TYPE_R64)
1059 TYPE("i8mem", TYPE_M8)
1060 TYPE("i8imm", TYPE_IMM8)
1061 TYPE("GR8", TYPE_R8)
1062 TYPE("VR128", TYPE_XMM128)
1063 TYPE("f128mem", TYPE_M128)
1064 TYPE("f256mem", TYPE_M256)
1065 TYPE("FR64", TYPE_XMM64)
1066 TYPE("f64mem", TYPE_M64FP)
1067 TYPE("sdmem", TYPE_M64FP)
1068 TYPE("FR32", TYPE_XMM32)
1069 TYPE("f32mem", TYPE_M32FP)
1070 TYPE("ssmem", TYPE_M32FP)
1071 TYPE("RST", TYPE_ST)
1072 TYPE("i128mem", TYPE_M128)
1073 TYPE("i256mem", TYPE_M256)
1074 TYPE("i64i32imm_pcrel", TYPE_REL64)
1075 TYPE("i16imm_pcrel", TYPE_REL16)
1076 TYPE("i32imm_pcrel", TYPE_REL32)
1077 TYPE("SSECC", TYPE_IMM3)
1078 TYPE("AVXCC", TYPE_IMM5)
1079 TYPE("brtarget", TYPE_RELv)
1080 TYPE("uncondbrtarget", TYPE_RELv)
1081 TYPE("brtarget8", TYPE_REL8)
1082 TYPE("f80mem", TYPE_M80FP)
1083 TYPE("lea32mem", TYPE_LEA)
1084 TYPE("lea64_32mem", TYPE_LEA)
1085 TYPE("lea64mem", TYPE_LEA)
1086 TYPE("VR64", TYPE_MM64)
1087 TYPE("i64imm", TYPE_IMMv)
1088 TYPE("opaque32mem", TYPE_M1616)
1089 TYPE("opaque48mem", TYPE_M1632)
1090 TYPE("opaque80mem", TYPE_M1664)
1091 TYPE("opaque512mem", TYPE_M512)
1092 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1093 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1094 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1095 TYPE("offset8", TYPE_MOFFS8)
1096 TYPE("offset16", TYPE_MOFFS16)
1097 TYPE("offset32", TYPE_MOFFS32)
1098 TYPE("offset64", TYPE_MOFFS64)
1099 TYPE("VR256", TYPE_XMM256)
1100 TYPE("GR16_NOAX", TYPE_Rv)
1101 TYPE("GR32_NOAX", TYPE_Rv)
1102 TYPE("GR64_NOAX", TYPE_R64)
1103 TYPE("vx32mem", TYPE_M32)
1104 TYPE("vy32mem", TYPE_M32)
1105 TYPE("vx64mem", TYPE_M64)
1106 TYPE("vy64mem", TYPE_M64)
1107 errs() << "Unhandled type string " << s << "\n";
1108 llvm_unreachable("Unhandled type string");
1112 #define ENCODING(str, encoding) if (s == str) return encoding;
1113 OperandEncoding RecognizableInstr::immediateEncodingFromString
1114 (const std::string &s,
1115 bool hasOpSizePrefix) {
1116 if(!hasOpSizePrefix) {
1117 // For instructions without an OpSize prefix, a declared 16-bit register or
1118 // immediate encoding is special.
1119 ENCODING("i16imm", ENCODING_IW)
1121 ENCODING("i32i8imm", ENCODING_IB)
1122 ENCODING("u32u8imm", ENCODING_IB)
1123 ENCODING("SSECC", ENCODING_IB)
1124 ENCODING("AVXCC", ENCODING_IB)
1125 ENCODING("i16imm", ENCODING_Iv)
1126 ENCODING("i16i8imm", ENCODING_IB)
1127 ENCODING("i32imm", ENCODING_Iv)
1128 ENCODING("i64i32imm", ENCODING_ID)
1129 ENCODING("i64i8imm", ENCODING_IB)
1130 ENCODING("i8imm", ENCODING_IB)
1131 // This is not a typo. Instructions like BLENDVPD put
1132 // register IDs in 8-bit immediates nowadays.
1133 ENCODING("VR256", ENCODING_IB)
1134 ENCODING("VR128", ENCODING_IB)
1135 ENCODING("FR32", ENCODING_IB)
1136 ENCODING("FR64", ENCODING_IB)
1137 errs() << "Unhandled immediate encoding " << s << "\n";
1138 llvm_unreachable("Unhandled immediate encoding");
1141 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1142 (const std::string &s,
1143 bool hasOpSizePrefix) {
1144 ENCODING("GR16", ENCODING_RM)
1145 ENCODING("GR32", ENCODING_RM)
1146 ENCODING("GR64", ENCODING_RM)
1147 ENCODING("GR8", ENCODING_RM)
1148 ENCODING("VR128", ENCODING_RM)
1149 ENCODING("FR64", ENCODING_RM)
1150 ENCODING("FR32", ENCODING_RM)
1151 ENCODING("VR64", ENCODING_RM)
1152 ENCODING("VR256", ENCODING_RM)
1153 errs() << "Unhandled R/M register encoding " << s << "\n";
1154 llvm_unreachable("Unhandled R/M register encoding");
1157 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1158 (const std::string &s,
1159 bool hasOpSizePrefix) {
1160 ENCODING("GR16", ENCODING_REG)
1161 ENCODING("GR32", ENCODING_REG)
1162 ENCODING("GR64", ENCODING_REG)
1163 ENCODING("GR8", ENCODING_REG)
1164 ENCODING("VR128", ENCODING_REG)
1165 ENCODING("FR64", ENCODING_REG)
1166 ENCODING("FR32", ENCODING_REG)
1167 ENCODING("VR64", ENCODING_REG)
1168 ENCODING("SEGMENT_REG", ENCODING_REG)
1169 ENCODING("DEBUG_REG", ENCODING_REG)
1170 ENCODING("CONTROL_REG", ENCODING_REG)
1171 ENCODING("VR256", ENCODING_REG)
1172 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1173 llvm_unreachable("Unhandled reg/opcode register encoding");
1176 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1177 (const std::string &s,
1178 bool hasOpSizePrefix) {
1179 ENCODING("GR32", ENCODING_VVVV)
1180 ENCODING("GR64", ENCODING_VVVV)
1181 ENCODING("FR32", ENCODING_VVVV)
1182 ENCODING("FR64", ENCODING_VVVV)
1183 ENCODING("VR128", ENCODING_VVVV)
1184 ENCODING("VR256", ENCODING_VVVV)
1185 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1186 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1189 OperandEncoding RecognizableInstr::memoryEncodingFromString
1190 (const std::string &s,
1191 bool hasOpSizePrefix) {
1192 ENCODING("i16mem", ENCODING_RM)
1193 ENCODING("i32mem", ENCODING_RM)
1194 ENCODING("i64mem", ENCODING_RM)
1195 ENCODING("i8mem", ENCODING_RM)
1196 ENCODING("ssmem", ENCODING_RM)
1197 ENCODING("sdmem", ENCODING_RM)
1198 ENCODING("f128mem", ENCODING_RM)
1199 ENCODING("f256mem", ENCODING_RM)
1200 ENCODING("f64mem", ENCODING_RM)
1201 ENCODING("f32mem", ENCODING_RM)
1202 ENCODING("i128mem", ENCODING_RM)
1203 ENCODING("i256mem", ENCODING_RM)
1204 ENCODING("f80mem", ENCODING_RM)
1205 ENCODING("lea32mem", ENCODING_RM)
1206 ENCODING("lea64_32mem", ENCODING_RM)
1207 ENCODING("lea64mem", ENCODING_RM)
1208 ENCODING("opaque32mem", ENCODING_RM)
1209 ENCODING("opaque48mem", ENCODING_RM)
1210 ENCODING("opaque80mem", ENCODING_RM)
1211 ENCODING("opaque512mem", ENCODING_RM)
1212 ENCODING("vx32mem", ENCODING_RM)
1213 ENCODING("vy32mem", ENCODING_RM)
1214 ENCODING("vx64mem", ENCODING_RM)
1215 ENCODING("vy64mem", ENCODING_RM)
1216 errs() << "Unhandled memory encoding " << s << "\n";
1217 llvm_unreachable("Unhandled memory encoding");
1220 OperandEncoding RecognizableInstr::relocationEncodingFromString
1221 (const std::string &s,
1222 bool hasOpSizePrefix) {
1223 if(!hasOpSizePrefix) {
1224 // For instructions without an OpSize prefix, a declared 16-bit register or
1225 // immediate encoding is special.
1226 ENCODING("i16imm", ENCODING_IW)
1228 ENCODING("i16imm", ENCODING_Iv)
1229 ENCODING("i16i8imm", ENCODING_IB)
1230 ENCODING("i32imm", ENCODING_Iv)
1231 ENCODING("i32i8imm", ENCODING_IB)
1232 ENCODING("i64i32imm", ENCODING_ID)
1233 ENCODING("i64i8imm", ENCODING_IB)
1234 ENCODING("i8imm", ENCODING_IB)
1235 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1236 ENCODING("i16imm_pcrel", ENCODING_IW)
1237 ENCODING("i32imm_pcrel", ENCODING_ID)
1238 ENCODING("brtarget", ENCODING_Iv)
1239 ENCODING("brtarget8", ENCODING_IB)
1240 ENCODING("i64imm", ENCODING_IO)
1241 ENCODING("offset8", ENCODING_Ia)
1242 ENCODING("offset16", ENCODING_Ia)
1243 ENCODING("offset32", ENCODING_Ia)
1244 ENCODING("offset64", ENCODING_Ia)
1245 errs() << "Unhandled relocation encoding " << s << "\n";
1246 llvm_unreachable("Unhandled relocation encoding");
1249 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1250 (const std::string &s,
1251 bool hasOpSizePrefix) {
1252 ENCODING("RST", ENCODING_I)
1253 ENCODING("GR32", ENCODING_Rv)
1254 ENCODING("GR64", ENCODING_RO)
1255 ENCODING("GR16", ENCODING_Rv)
1256 ENCODING("GR8", ENCODING_RB)
1257 ENCODING("GR16_NOAX", ENCODING_Rv)
1258 ENCODING("GR32_NOAX", ENCODING_Rv)
1259 ENCODING("GR64_NOAX", ENCODING_RO)
1260 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1261 llvm_unreachable("Unhandled opcode modifier encoding");