1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file is part of the X86 Disassembler Emitter.
11 // It contains the implementation of a single recognizable instruction.
12 // Documentation for the disassembler emitter in general can be found in
13 // X86DisasemblerEmitter.h.
15 //===----------------------------------------------------------------------===//
17 #include "X86DisassemblerShared.h"
18 #include "X86RecognizableInstr.h"
19 #include "X86ModRMFilters.h"
21 #include "llvm/Support/ErrorHandling.h"
50 // A clone of X86 since we can't depend on something that is generated.
60 MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
61 MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
62 MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
63 MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
65 #define MAP(from, to) MRM_##from = to,
76 D8 = 3, D9 = 4, DA = 5, DB = 6,
77 DC = 7, DD = 8, DE = 9, DF = 10,
80 A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
84 // If rows are added to the opcode extension tables, then corresponding entries
85 // must be added here.
87 // If the row corresponds to a single byte (i.e., 8f), then add an entry for
88 // that byte to ONE_BYTE_EXTENSION_TABLES.
90 // If the row corresponds to two bytes where the first is 0f, add an entry for
91 // the second byte to TWO_BYTE_EXTENSION_TABLES.
93 // If the row corresponds to some other set of bytes, you will need to modify
94 // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
95 // to the X86 TD files, except in two cases: if the first two bytes of such a
96 // new combination are 0f 38 or 0f 3a, you just have to add maps called
97 // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
98 // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
99 // in RecognizableInstr::emitDecodePath().
101 #define ONE_BYTE_EXTENSION_TABLES \
102 EXTENSION_TABLE(80) \
103 EXTENSION_TABLE(81) \
104 EXTENSION_TABLE(82) \
105 EXTENSION_TABLE(83) \
106 EXTENSION_TABLE(8f) \
107 EXTENSION_TABLE(c0) \
108 EXTENSION_TABLE(c1) \
109 EXTENSION_TABLE(c6) \
110 EXTENSION_TABLE(c7) \
111 EXTENSION_TABLE(d0) \
112 EXTENSION_TABLE(d1) \
113 EXTENSION_TABLE(d2) \
114 EXTENSION_TABLE(d3) \
115 EXTENSION_TABLE(f6) \
116 EXTENSION_TABLE(f7) \
117 EXTENSION_TABLE(fe) \
120 #define TWO_BYTE_EXTENSION_TABLES \
121 EXTENSION_TABLE(00) \
122 EXTENSION_TABLE(01) \
123 EXTENSION_TABLE(18) \
124 EXTENSION_TABLE(71) \
125 EXTENSION_TABLE(72) \
126 EXTENSION_TABLE(73) \
127 EXTENSION_TABLE(ae) \
128 EXTENSION_TABLE(ba) \
131 #define THREE_BYTE_38_EXTENSION_TABLES \
134 using namespace X86Disassembler;
136 /// needsModRMForDecode - Indicates whether a particular instruction requires a
137 /// ModR/M byte for the instruction to be properly decoded. For example, a
138 /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
141 /// @param form - The form of the instruction.
142 /// @return - true if the form implies that a ModR/M byte is required, false
144 static bool needsModRMForDecode(uint8_t form) {
145 if (form == X86Local::MRMDestReg ||
146 form == X86Local::MRMDestMem ||
147 form == X86Local::MRMSrcReg ||
148 form == X86Local::MRMSrcMem ||
149 (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
150 (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
156 /// isRegFormat - Indicates whether a particular form requires the Mod field of
157 /// the ModR/M byte to be 0b11.
159 /// @param form - The form of the instruction.
160 /// @return - true if the form implies that Mod must be 0b11, false
162 static bool isRegFormat(uint8_t form) {
163 if (form == X86Local::MRMDestReg ||
164 form == X86Local::MRMSrcReg ||
165 (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
171 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
172 /// Useful for switch statements and the like.
174 /// @param init - A reference to the BitsInit to be decoded.
175 /// @return - The field, with the first bit in the BitsInit as the lowest
177 static uint8_t byteFromBitsInit(BitsInit &init) {
178 int width = init.getNumBits();
180 assert(width <= 8 && "Field is too large for uint8_t!");
187 for (index = 0; index < width; index++) {
188 if (static_cast<BitInit*>(init.getBit(index))->getValue())
197 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the
198 /// name of the field.
200 /// @param rec - The record from which to extract the value.
201 /// @param name - The name of the field in the record.
202 /// @return - The field, as translated by byteFromBitsInit().
203 static uint8_t byteFromRec(const Record* rec, const std::string &name) {
204 BitsInit* bits = rec->getValueAsBitsInit(name);
205 return byteFromBitsInit(*bits);
208 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
209 const CodeGenInstruction &insn,
214 Name = Rec->getName();
215 Spec = &tables.specForUID(UID);
217 if (!Rec->isSubClassOf("X86Inst")) {
218 ShouldBeEmitted = false;
222 Prefix = byteFromRec(Rec, "Prefix");
223 Opcode = byteFromRec(Rec, "Opcode");
224 Form = byteFromRec(Rec, "FormBits");
225 SegOvr = byteFromRec(Rec, "SegOvrBits");
227 HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix");
228 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix");
229 HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix");
230 HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix");
231 HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
232 HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix");
233 HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix");
234 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L");
235 HasLockPrefix = Rec->getValueAsBit("hasLockPrefix");
236 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly");
238 Name = Rec->getName();
239 AsmString = Rec->getValueAsString("AsmString");
241 Operands = &insn.Operands.OperandList;
243 IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
244 (Name.find("CRC32") != Name.npos);
245 HasFROperands = hasFROperands();
246 HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L");
248 // Check for 64-bit inst which does not require REX
251 // FIXME: Is there some better way to check for In64BitMode?
252 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
253 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
254 if (Predicates[i]->getName().find("32Bit") != Name.npos) {
258 if (Predicates[i]->getName().find("64Bit") != Name.npos) {
263 // FIXME: These instructions aren't marked as 64-bit in any way
264 Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
265 Rec->getName() == "MASKMOVDQU64" ||
266 Rec->getName() == "POPFS64" ||
267 Rec->getName() == "POPGS64" ||
268 Rec->getName() == "PUSHFS64" ||
269 Rec->getName() == "PUSHGS64" ||
270 Rec->getName() == "REX64_PREFIX" ||
271 Rec->getName().find("MOV64") != Name.npos ||
272 Rec->getName().find("PUSH64") != Name.npos ||
273 Rec->getName().find("POP64") != Name.npos;
275 ShouldBeEmitted = true;
278 void RecognizableInstr::processInstr(DisassemblerTables &tables,
279 const CodeGenInstruction &insn,
282 // Ignore "asm parser only" instructions.
283 if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
286 RecognizableInstr recogInstr(tables, insn, uid);
288 recogInstr.emitInstructionSpecifier(tables);
290 if (recogInstr.shouldBeEmitted())
291 recogInstr.emitDecodePath(tables);
294 InstructionContext RecognizableInstr::insnContext() const {
295 InstructionContext insnContext;
297 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
298 if (HasVEX_LPrefix && HasVEX_WPrefix) {
300 insnContext = IC_VEX_L_W_OPSIZE;
302 llvm_unreachable("Don't support VEX.L and VEX.W together");
303 } else if (HasOpSizePrefix && HasVEX_LPrefix)
304 insnContext = IC_VEX_L_OPSIZE;
305 else if (HasOpSizePrefix && HasVEX_WPrefix)
306 insnContext = IC_VEX_W_OPSIZE;
307 else if (HasOpSizePrefix)
308 insnContext = IC_VEX_OPSIZE;
309 else if (HasVEX_LPrefix &&
310 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
311 insnContext = IC_VEX_L_XS;
312 else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
313 Prefix == X86Local::T8XD ||
314 Prefix == X86Local::TAXD))
315 insnContext = IC_VEX_L_XD;
316 else if (HasVEX_WPrefix &&
317 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
318 insnContext = IC_VEX_W_XS;
319 else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
320 Prefix == X86Local::T8XD ||
321 Prefix == X86Local::TAXD))
322 insnContext = IC_VEX_W_XD;
323 else if (HasVEX_WPrefix)
324 insnContext = IC_VEX_W;
325 else if (HasVEX_LPrefix)
326 insnContext = IC_VEX_L;
327 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
328 Prefix == X86Local::TAXD)
329 insnContext = IC_VEX_XD;
330 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
331 insnContext = IC_VEX_XS;
333 insnContext = IC_VEX;
334 } else if (Is64Bit || HasREX_WPrefix) {
335 if (HasREX_WPrefix && HasOpSizePrefix)
336 insnContext = IC_64BIT_REXW_OPSIZE;
337 else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
338 Prefix == X86Local::T8XD ||
339 Prefix == X86Local::TAXD))
340 insnContext = IC_64BIT_XD_OPSIZE;
341 else if (HasOpSizePrefix &&
342 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
343 insnContext = IC_64BIT_XS_OPSIZE;
344 else if (HasOpSizePrefix)
345 insnContext = IC_64BIT_OPSIZE;
346 else if (HasREX_WPrefix &&
347 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
348 insnContext = IC_64BIT_REXW_XS;
349 else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
350 Prefix == X86Local::T8XD ||
351 Prefix == X86Local::TAXD))
352 insnContext = IC_64BIT_REXW_XD;
353 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
354 Prefix == X86Local::TAXD)
355 insnContext = IC_64BIT_XD;
356 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
357 insnContext = IC_64BIT_XS;
358 else if (HasREX_WPrefix)
359 insnContext = IC_64BIT_REXW;
361 insnContext = IC_64BIT;
363 if (HasOpSizePrefix && (Prefix == X86Local::XD ||
364 Prefix == X86Local::T8XD ||
365 Prefix == X86Local::TAXD))
366 insnContext = IC_XD_OPSIZE;
367 else if (HasOpSizePrefix &&
368 (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
369 insnContext = IC_XS_OPSIZE;
370 else if (HasOpSizePrefix)
371 insnContext = IC_OPSIZE;
372 else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
373 Prefix == X86Local::TAXD)
375 else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
376 Prefix == X86Local::REP)
385 RecognizableInstr::filter_ret RecognizableInstr::filter() const {
390 // Filter out intrinsics
392 if (!Rec->isSubClassOf("X86Inst"))
393 return FILTER_STRONG;
395 if (Form == X86Local::Pseudo ||
396 (IsCodeGenOnly && Name.find("_REV") == Name.npos))
397 return FILTER_STRONG;
399 if (Form == X86Local::MRMInitReg)
400 return FILTER_STRONG;
403 // Filter out artificial instructions
405 if (Name.find("_Int") != Name.npos ||
406 Name.find("Int_") != Name.npos ||
407 Name.find("_NOREX") != Name.npos ||
408 Name.find("2SDL") != Name.npos ||
409 Name == "LOCK_PREFIX")
410 return FILTER_STRONG;
412 // Filter out instructions with segment override prefixes.
413 // They're too messy to handle now and we'll special case them if needed.
416 return FILTER_STRONG;
418 // Filter out instructions that can't be printed.
420 if (AsmString.size() == 0)
421 return FILTER_STRONG;
423 // Filter out instructions with subreg operands.
425 if (AsmString.find("subreg") != AsmString.npos)
426 return FILTER_STRONG;
433 // Filter out instructions with a LOCK prefix;
434 // prefer forms that do not have the prefix
438 // Filter out alternate forms of AVX instructions
439 if (Name.find("_alt") != Name.npos ||
440 Name.find("XrYr") != Name.npos ||
441 (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
442 Name.find("_64mr") != Name.npos ||
443 Name.find("Xrr") != Name.npos ||
444 Name.find("rr64") != Name.npos)
449 if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
451 if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
454 if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
456 if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
458 if (Name.find("Fs") != Name.npos)
460 if (Name == "PUSH64i16" ||
461 Name == "MOVPQI2QImr" ||
462 Name == "VMOVPQI2QImr" ||
463 Name == "MMX_MOVD64rrv164" ||
464 Name == "MOV64ri64i32" ||
465 Name == "VMASKMOVDQU64" ||
466 Name == "VEXTRACTPSrr64" ||
467 Name == "VMOVQd64rr" ||
468 Name == "VMOVQs64rr")
471 if (HasFROperands && Name.find("MOV") != Name.npos &&
472 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
473 (Name.find("to") != Name.npos)))
476 return FILTER_NORMAL;
479 bool RecognizableInstr::hasFROperands() const {
480 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
481 unsigned numOperands = OperandList.size();
483 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
484 const std::string &recName = OperandList[operandIndex].Rec->getName();
486 if (recName.find("FR") != recName.npos)
492 bool RecognizableInstr::has256BitOperands() const {
493 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
494 unsigned numOperands = OperandList.size();
496 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
497 const std::string &recName = OperandList[operandIndex].Rec->getName();
499 if (!recName.compare("VR256") || !recName.compare("f256mem")) {
506 void RecognizableInstr::handleOperand(
508 unsigned &operandIndex,
509 unsigned &physicalOperandIndex,
510 unsigned &numPhysicalOperands,
511 unsigned *operandMapping,
512 OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) {
514 if (physicalOperandIndex >= numPhysicalOperands)
517 assert(physicalOperandIndex < numPhysicalOperands);
520 while (operandMapping[operandIndex] != operandIndex) {
521 Spec->operands[operandIndex].encoding = ENCODING_DUP;
522 Spec->operands[operandIndex].type =
523 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
527 const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
529 Spec->operands[operandIndex].encoding = encodingFromString(typeName,
531 Spec->operands[operandIndex].type = typeFromString(typeName,
537 ++physicalOperandIndex;
540 void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
543 if (!Rec->isSubClassOf("X86Inst"))
548 Spec->filtered = true;
551 ShouldBeEmitted = false;
557 Spec->insnContext = insnContext();
559 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
561 unsigned operandIndex;
562 unsigned numOperands = OperandList.size();
563 unsigned numPhysicalOperands = 0;
565 // operandMapping maps from operands in OperandList to their originals.
566 // If operandMapping[i] != i, then the entry is a duplicate.
567 unsigned operandMapping[X86_MAX_OPERANDS];
569 bool hasFROperands = false;
571 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
573 for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
574 if (OperandList[operandIndex].Constraints.size()) {
575 const CGIOperandList::ConstraintInfo &Constraint =
576 OperandList[operandIndex].Constraints[0];
577 if (Constraint.isTied()) {
578 operandMapping[operandIndex] = Constraint.getTiedOperand();
580 ++numPhysicalOperands;
581 operandMapping[operandIndex] = operandIndex;
584 ++numPhysicalOperands;
585 operandMapping[operandIndex] = operandIndex;
588 const std::string &recName = OperandList[operandIndex].Rec->getName();
590 if (recName.find("FR") != recName.npos)
591 hasFROperands = true;
594 if (hasFROperands && Name.find("MOV") != Name.npos &&
595 ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
596 (Name.find("to") != Name.npos)))
597 ShouldBeEmitted = false;
599 if (!ShouldBeEmitted)
602 #define HANDLE_OPERAND(class) \
603 handleOperand(false, \
605 physicalOperandIndex, \
606 numPhysicalOperands, \
608 class##EncodingFromString);
610 #define HANDLE_OPTIONAL(class) \
611 handleOperand(true, \
613 physicalOperandIndex, \
614 numPhysicalOperands, \
616 class##EncodingFromString);
618 // operandIndex should always be < numOperands
620 // physicalOperandIndex should always be < numPhysicalOperands
621 unsigned physicalOperandIndex = 0;
624 case X86Local::RawFrm:
625 // Operand 1 (optional) is an address or immediate.
626 // Operand 2 (optional) is an immediate.
627 assert(numPhysicalOperands <= 2 &&
628 "Unexpected number of operands for RawFrm");
629 HANDLE_OPTIONAL(relocation)
630 HANDLE_OPTIONAL(immediate)
632 case X86Local::AddRegFrm:
633 // Operand 1 is added to the opcode.
634 // Operand 2 (optional) is an address.
635 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
636 "Unexpected number of operands for AddRegFrm");
637 HANDLE_OPERAND(opcodeModifier)
638 HANDLE_OPTIONAL(relocation)
640 case X86Local::MRMDestReg:
641 // Operand 1 is a register operand in the R/M field.
642 // Operand 2 is a register operand in the Reg/Opcode field.
643 // - In AVX, there is a register operand in the VEX.vvvv field here -
644 // Operand 3 (optional) is an immediate.
646 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
647 "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
649 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
650 "Unexpected number of operands for MRMDestRegFrm");
652 HANDLE_OPERAND(rmRegister)
655 // FIXME: In AVX, the register below becomes the one encoded
656 // in ModRMVEX and the one above the one in the VEX.VVVV field
657 HANDLE_OPERAND(vvvvRegister)
659 HANDLE_OPERAND(roRegister)
660 HANDLE_OPTIONAL(immediate)
662 case X86Local::MRMDestMem:
663 // Operand 1 is a memory operand (possibly SIB-extended)
664 // Operand 2 is a register operand in the Reg/Opcode field.
665 // - In AVX, there is a register operand in the VEX.vvvv field here -
666 // Operand 3 (optional) is an immediate.
668 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
669 "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
671 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
672 "Unexpected number of operands for MRMDestMemFrm");
673 HANDLE_OPERAND(memory)
676 // FIXME: In AVX, the register below becomes the one encoded
677 // in ModRMVEX and the one above the one in the VEX.VVVV field
678 HANDLE_OPERAND(vvvvRegister)
680 HANDLE_OPERAND(roRegister)
681 HANDLE_OPTIONAL(immediate)
683 case X86Local::MRMSrcReg:
684 // Operand 1 is a register operand in the Reg/Opcode field.
685 // Operand 2 is a register operand in the R/M field.
686 // - In AVX, there is a register operand in the VEX.vvvv field here -
687 // Operand 3 (optional) is an immediate.
689 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
690 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
691 "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
693 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
694 "Unexpected number of operands for MRMSrcRegFrm");
696 HANDLE_OPERAND(roRegister)
699 // FIXME: In AVX, the register below becomes the one encoded
700 // in ModRMVEX and the one above the one in the VEX.VVVV field
701 HANDLE_OPERAND(vvvvRegister)
704 HANDLE_OPERAND(immediate)
706 HANDLE_OPERAND(rmRegister)
708 if (HasVEX_4VOp3Prefix)
709 HANDLE_OPERAND(vvvvRegister)
711 if (!HasMemOp4Prefix)
712 HANDLE_OPTIONAL(immediate)
713 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
715 case X86Local::MRMSrcMem:
716 // Operand 1 is a register operand in the Reg/Opcode field.
717 // Operand 2 is a memory operand (possibly SIB-extended)
718 // - In AVX, there is a register operand in the VEX.vvvv field here -
719 // Operand 3 (optional) is an immediate.
721 if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
722 assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
723 "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
725 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
726 "Unexpected number of operands for MRMSrcMemFrm");
728 HANDLE_OPERAND(roRegister)
731 // FIXME: In AVX, the register below becomes the one encoded
732 // in ModRMVEX and the one above the one in the VEX.VVVV field
733 HANDLE_OPERAND(vvvvRegister)
736 HANDLE_OPERAND(immediate)
738 HANDLE_OPERAND(memory)
740 if (HasVEX_4VOp3Prefix)
741 HANDLE_OPERAND(vvvvRegister)
743 if (!HasMemOp4Prefix)
744 HANDLE_OPTIONAL(immediate)
745 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
747 case X86Local::MRM0r:
748 case X86Local::MRM1r:
749 case X86Local::MRM2r:
750 case X86Local::MRM3r:
751 case X86Local::MRM4r:
752 case X86Local::MRM5r:
753 case X86Local::MRM6r:
754 case X86Local::MRM7r:
755 // Operand 1 is a register operand in the R/M field.
756 // Operand 2 (optional) is an immediate or relocation.
758 assert(numPhysicalOperands <= 3 &&
759 "Unexpected number of operands for MRMnRFrm with VEX_4V");
761 assert(numPhysicalOperands <= 2 &&
762 "Unexpected number of operands for MRMnRFrm");
764 HANDLE_OPERAND(vvvvRegister)
765 HANDLE_OPTIONAL(rmRegister)
766 HANDLE_OPTIONAL(relocation)
768 case X86Local::MRM0m:
769 case X86Local::MRM1m:
770 case X86Local::MRM2m:
771 case X86Local::MRM3m:
772 case X86Local::MRM4m:
773 case X86Local::MRM5m:
774 case X86Local::MRM6m:
775 case X86Local::MRM7m:
776 // Operand 1 is a memory operand (possibly SIB-extended)
777 // Operand 2 (optional) is an immediate or relocation.
779 assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
780 "Unexpected number of operands for MRMnMFrm");
782 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
783 "Unexpected number of operands for MRMnMFrm");
785 HANDLE_OPERAND(vvvvRegister)
786 HANDLE_OPERAND(memory)
787 HANDLE_OPTIONAL(relocation)
789 case X86Local::RawFrmImm8:
790 // operand 1 is a 16-bit immediate
791 // operand 2 is an 8-bit immediate
792 assert(numPhysicalOperands == 2 &&
793 "Unexpected number of operands for X86Local::RawFrmImm8");
794 HANDLE_OPERAND(immediate)
795 HANDLE_OPERAND(immediate)
797 case X86Local::RawFrmImm16:
798 // operand 1 is a 16-bit immediate
799 // operand 2 is a 16-bit immediate
800 HANDLE_OPERAND(immediate)
801 HANDLE_OPERAND(immediate)
803 case X86Local::MRMInitReg:
808 #undef HANDLE_OPERAND
809 #undef HANDLE_OPTIONAL
812 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
813 // Special cases where the LLVM tables are not complete
815 #define MAP(from, to) \
816 case X86Local::MRM_##from: \
817 filter = new ExactFilter(0x##from); \
820 OpcodeType opcodeType = (OpcodeType)-1;
822 ModRMFilter* filter = NULL;
823 uint8_t opcodeToSet = 0;
826 // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
830 opcodeType = TWOBYTE;
834 if (needsModRMForDecode(Form))
835 filter = new ModFilter(isRegFormat(Form));
837 filter = new DumbFilter();
839 #define EXTENSION_TABLE(n) case 0x##n:
840 TWO_BYTE_EXTENSION_TABLES
841 #undef EXTENSION_TABLE
844 llvm_unreachable("Unhandled two-byte extended opcode");
845 case X86Local::MRM0r:
846 case X86Local::MRM1r:
847 case X86Local::MRM2r:
848 case X86Local::MRM3r:
849 case X86Local::MRM4r:
850 case X86Local::MRM5r:
851 case X86Local::MRM6r:
852 case X86Local::MRM7r:
853 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
855 case X86Local::MRM0m:
856 case X86Local::MRM1m:
857 case X86Local::MRM2m:
858 case X86Local::MRM3m:
859 case X86Local::MRM4m:
860 case X86Local::MRM5m:
861 case X86Local::MRM6m:
862 case X86Local::MRM7m:
863 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
869 opcodeToSet = Opcode;
874 opcodeType = THREEBYTE_38;
877 if (needsModRMForDecode(Form))
878 filter = new ModFilter(isRegFormat(Form));
880 filter = new DumbFilter();
882 #define EXTENSION_TABLE(n) case 0x##n:
883 THREE_BYTE_38_EXTENSION_TABLES
884 #undef EXTENSION_TABLE
887 llvm_unreachable("Unhandled two-byte extended opcode");
888 case X86Local::MRM0r:
889 case X86Local::MRM1r:
890 case X86Local::MRM2r:
891 case X86Local::MRM3r:
892 case X86Local::MRM4r:
893 case X86Local::MRM5r:
894 case X86Local::MRM6r:
895 case X86Local::MRM7r:
896 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
898 case X86Local::MRM0m:
899 case X86Local::MRM1m:
900 case X86Local::MRM2m:
901 case X86Local::MRM3m:
902 case X86Local::MRM4m:
903 case X86Local::MRM5m:
904 case X86Local::MRM6m:
905 case X86Local::MRM7m:
906 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
912 opcodeToSet = Opcode;
916 opcodeType = THREEBYTE_3A;
917 if (needsModRMForDecode(Form))
918 filter = new ModFilter(isRegFormat(Form));
920 filter = new DumbFilter();
921 opcodeToSet = Opcode;
924 opcodeType = THREEBYTE_A6;
925 if (needsModRMForDecode(Form))
926 filter = new ModFilter(isRegFormat(Form));
928 filter = new DumbFilter();
929 opcodeToSet = Opcode;
932 opcodeType = THREEBYTE_A7;
933 if (needsModRMForDecode(Form))
934 filter = new ModFilter(isRegFormat(Form));
936 filter = new DumbFilter();
937 opcodeToSet = Opcode;
947 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
948 opcodeType = ONEBYTE;
949 if (Form == X86Local::AddRegFrm) {
950 Spec->modifierType = MODIFIER_MODRM;
951 Spec->modifierBase = Opcode;
952 filter = new AddRegEscapeFilter(Opcode);
954 filter = new EscapeFilter(true, Opcode);
956 opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
960 opcodeType = ONEBYTE;
962 #define EXTENSION_TABLE(n) case 0x##n:
963 ONE_BYTE_EXTENSION_TABLES
964 #undef EXTENSION_TABLE
967 llvm_unreachable("Fell through the cracks of a single-byte "
969 case X86Local::MRM0r:
970 case X86Local::MRM1r:
971 case X86Local::MRM2r:
972 case X86Local::MRM3r:
973 case X86Local::MRM4r:
974 case X86Local::MRM5r:
975 case X86Local::MRM6r:
976 case X86Local::MRM7r:
977 filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
979 case X86Local::MRM0m:
980 case X86Local::MRM1m:
981 case X86Local::MRM2m:
982 case X86Local::MRM3m:
983 case X86Local::MRM4m:
984 case X86Local::MRM5m:
985 case X86Local::MRM6m:
986 case X86Local::MRM7m:
987 filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1000 filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1003 if (needsModRMForDecode(Form))
1004 filter = new ModFilter(isRegFormat(Form));
1006 filter = new DumbFilter();
1008 } // switch (Opcode)
1009 opcodeToSet = Opcode;
1010 } // switch (Prefix)
1012 assert(opcodeType != (OpcodeType)-1 &&
1013 "Opcode type not set");
1014 assert(filter && "Filter not set");
1016 if (Form == X86Local::AddRegFrm) {
1017 if(Spec->modifierType != MODIFIER_MODRM) {
1018 assert(opcodeToSet < 0xf9 &&
1019 "Not enough room for all ADDREG_FRM operands");
1021 uint8_t currentOpcode;
1023 for (currentOpcode = opcodeToSet;
1024 currentOpcode < opcodeToSet + 8;
1026 tables.setTableFields(opcodeType,
1030 UID, Is32Bit, IgnoresVEX_L);
1032 Spec->modifierType = MODIFIER_OPCODE;
1033 Spec->modifierBase = opcodeToSet;
1035 // modifierBase was set where MODIFIER_MODRM was set
1036 tables.setTableFields(opcodeType,
1040 UID, Is32Bit, IgnoresVEX_L);
1043 tables.setTableFields(opcodeType,
1047 UID, Is32Bit, IgnoresVEX_L);
1049 Spec->modifierType = MODIFIER_NONE;
1050 Spec->modifierBase = opcodeToSet;
1058 #define TYPE(str, type) if (s == str) return type;
1059 OperandType RecognizableInstr::typeFromString(const std::string &s,
1061 bool hasREX_WPrefix,
1062 bool hasOpSizePrefix) {
1064 // For SSE instructions, we ignore the OpSize prefix and force operand
1066 TYPE("GR16", TYPE_R16)
1067 TYPE("GR32", TYPE_R32)
1068 TYPE("GR64", TYPE_R64)
1070 if(hasREX_WPrefix) {
1071 // For instructions with a REX_W prefix, a declared 32-bit register encoding
1073 TYPE("GR32", TYPE_R32)
1075 if(!hasOpSizePrefix) {
1076 // For instructions without an OpSize prefix, a declared 16-bit register or
1077 // immediate encoding is special.
1078 TYPE("GR16", TYPE_R16)
1079 TYPE("i16imm", TYPE_IMM16)
1081 TYPE("i16mem", TYPE_Mv)
1082 TYPE("i16imm", TYPE_IMMv)
1083 TYPE("i16i8imm", TYPE_IMMv)
1084 TYPE("GR16", TYPE_Rv)
1085 TYPE("i32mem", TYPE_Mv)
1086 TYPE("i32imm", TYPE_IMMv)
1087 TYPE("i32i8imm", TYPE_IMM32)
1088 TYPE("u32u8imm", TYPE_IMM32)
1089 TYPE("GR32", TYPE_Rv)
1090 TYPE("i64mem", TYPE_Mv)
1091 TYPE("i64i32imm", TYPE_IMM64)
1092 TYPE("i64i8imm", TYPE_IMM64)
1093 TYPE("GR64", TYPE_R64)
1094 TYPE("i8mem", TYPE_M8)
1095 TYPE("i8imm", TYPE_IMM8)
1096 TYPE("GR8", TYPE_R8)
1097 TYPE("VR128", TYPE_XMM128)
1098 TYPE("f128mem", TYPE_M128)
1099 TYPE("f256mem", TYPE_M256)
1100 TYPE("FR64", TYPE_XMM64)
1101 TYPE("f64mem", TYPE_M64FP)
1102 TYPE("sdmem", TYPE_M64FP)
1103 TYPE("FR32", TYPE_XMM32)
1104 TYPE("f32mem", TYPE_M32FP)
1105 TYPE("ssmem", TYPE_M32FP)
1106 TYPE("RST", TYPE_ST)
1107 TYPE("i128mem", TYPE_M128)
1108 TYPE("i256mem", TYPE_M256)
1109 TYPE("i64i32imm_pcrel", TYPE_REL64)
1110 TYPE("i16imm_pcrel", TYPE_REL16)
1111 TYPE("i32imm_pcrel", TYPE_REL32)
1112 TYPE("SSECC", TYPE_IMM3)
1113 TYPE("brtarget", TYPE_RELv)
1114 TYPE("uncondbrtarget", TYPE_RELv)
1115 TYPE("brtarget8", TYPE_REL8)
1116 TYPE("f80mem", TYPE_M80FP)
1117 TYPE("lea32mem", TYPE_LEA)
1118 TYPE("lea64_32mem", TYPE_LEA)
1119 TYPE("lea64mem", TYPE_LEA)
1120 TYPE("VR64", TYPE_MM64)
1121 TYPE("i64imm", TYPE_IMMv)
1122 TYPE("opaque32mem", TYPE_M1616)
1123 TYPE("opaque48mem", TYPE_M1632)
1124 TYPE("opaque80mem", TYPE_M1664)
1125 TYPE("opaque512mem", TYPE_M512)
1126 TYPE("SEGMENT_REG", TYPE_SEGMENTREG)
1127 TYPE("DEBUG_REG", TYPE_DEBUGREG)
1128 TYPE("CONTROL_REG", TYPE_CONTROLREG)
1129 TYPE("offset8", TYPE_MOFFS8)
1130 TYPE("offset16", TYPE_MOFFS16)
1131 TYPE("offset32", TYPE_MOFFS32)
1132 TYPE("offset64", TYPE_MOFFS64)
1133 TYPE("VR256", TYPE_XMM256)
1134 TYPE("GR16_NOAX", TYPE_Rv)
1135 TYPE("GR32_NOAX", TYPE_Rv)
1136 TYPE("GR64_NOAX", TYPE_R64)
1137 errs() << "Unhandled type string " << s << "\n";
1138 llvm_unreachable("Unhandled type string");
1142 #define ENCODING(str, encoding) if (s == str) return encoding;
1143 OperandEncoding RecognizableInstr::immediateEncodingFromString
1144 (const std::string &s,
1145 bool hasOpSizePrefix) {
1146 if(!hasOpSizePrefix) {
1147 // For instructions without an OpSize prefix, a declared 16-bit register or
1148 // immediate encoding is special.
1149 ENCODING("i16imm", ENCODING_IW)
1151 ENCODING("i32i8imm", ENCODING_IB)
1152 ENCODING("u32u8imm", ENCODING_IB)
1153 ENCODING("SSECC", ENCODING_IB)
1154 ENCODING("i16imm", ENCODING_Iv)
1155 ENCODING("i16i8imm", ENCODING_IB)
1156 ENCODING("i32imm", ENCODING_Iv)
1157 ENCODING("i64i32imm", ENCODING_ID)
1158 ENCODING("i64i8imm", ENCODING_IB)
1159 ENCODING("i8imm", ENCODING_IB)
1160 // This is not a typo. Instructions like BLENDVPD put
1161 // register IDs in 8-bit immediates nowadays.
1162 ENCODING("VR256", ENCODING_IB)
1163 ENCODING("VR128", ENCODING_IB)
1164 errs() << "Unhandled immediate encoding " << s << "\n";
1165 llvm_unreachable("Unhandled immediate encoding");
1168 OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1169 (const std::string &s,
1170 bool hasOpSizePrefix) {
1171 ENCODING("GR16", ENCODING_RM)
1172 ENCODING("GR32", ENCODING_RM)
1173 ENCODING("GR64", ENCODING_RM)
1174 ENCODING("GR8", ENCODING_RM)
1175 ENCODING("VR128", ENCODING_RM)
1176 ENCODING("FR64", ENCODING_RM)
1177 ENCODING("FR32", ENCODING_RM)
1178 ENCODING("VR64", ENCODING_RM)
1179 ENCODING("VR256", ENCODING_RM)
1180 errs() << "Unhandled R/M register encoding " << s << "\n";
1181 llvm_unreachable("Unhandled R/M register encoding");
1184 OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1185 (const std::string &s,
1186 bool hasOpSizePrefix) {
1187 ENCODING("GR16", ENCODING_REG)
1188 ENCODING("GR32", ENCODING_REG)
1189 ENCODING("GR64", ENCODING_REG)
1190 ENCODING("GR8", ENCODING_REG)
1191 ENCODING("VR128", ENCODING_REG)
1192 ENCODING("FR64", ENCODING_REG)
1193 ENCODING("FR32", ENCODING_REG)
1194 ENCODING("VR64", ENCODING_REG)
1195 ENCODING("SEGMENT_REG", ENCODING_REG)
1196 ENCODING("DEBUG_REG", ENCODING_REG)
1197 ENCODING("CONTROL_REG", ENCODING_REG)
1198 ENCODING("VR256", ENCODING_REG)
1199 errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1200 llvm_unreachable("Unhandled reg/opcode register encoding");
1203 OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1204 (const std::string &s,
1205 bool hasOpSizePrefix) {
1206 ENCODING("GR32", ENCODING_VVVV)
1207 ENCODING("GR64", ENCODING_VVVV)
1208 ENCODING("FR32", ENCODING_VVVV)
1209 ENCODING("FR64", ENCODING_VVVV)
1210 ENCODING("VR128", ENCODING_VVVV)
1211 ENCODING("VR256", ENCODING_VVVV)
1212 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1213 llvm_unreachable("Unhandled VEX.vvvv register encoding");
1216 OperandEncoding RecognizableInstr::memoryEncodingFromString
1217 (const std::string &s,
1218 bool hasOpSizePrefix) {
1219 ENCODING("i16mem", ENCODING_RM)
1220 ENCODING("i32mem", ENCODING_RM)
1221 ENCODING("i64mem", ENCODING_RM)
1222 ENCODING("i8mem", ENCODING_RM)
1223 ENCODING("ssmem", ENCODING_RM)
1224 ENCODING("sdmem", ENCODING_RM)
1225 ENCODING("f128mem", ENCODING_RM)
1226 ENCODING("f256mem", ENCODING_RM)
1227 ENCODING("f64mem", ENCODING_RM)
1228 ENCODING("f32mem", ENCODING_RM)
1229 ENCODING("i128mem", ENCODING_RM)
1230 ENCODING("i256mem", ENCODING_RM)
1231 ENCODING("f80mem", ENCODING_RM)
1232 ENCODING("lea32mem", ENCODING_RM)
1233 ENCODING("lea64_32mem", ENCODING_RM)
1234 ENCODING("lea64mem", ENCODING_RM)
1235 ENCODING("opaque32mem", ENCODING_RM)
1236 ENCODING("opaque48mem", ENCODING_RM)
1237 ENCODING("opaque80mem", ENCODING_RM)
1238 ENCODING("opaque512mem", ENCODING_RM)
1239 errs() << "Unhandled memory encoding " << s << "\n";
1240 llvm_unreachable("Unhandled memory encoding");
1243 OperandEncoding RecognizableInstr::relocationEncodingFromString
1244 (const std::string &s,
1245 bool hasOpSizePrefix) {
1246 if(!hasOpSizePrefix) {
1247 // For instructions without an OpSize prefix, a declared 16-bit register or
1248 // immediate encoding is special.
1249 ENCODING("i16imm", ENCODING_IW)
1251 ENCODING("i16imm", ENCODING_Iv)
1252 ENCODING("i16i8imm", ENCODING_IB)
1253 ENCODING("i32imm", ENCODING_Iv)
1254 ENCODING("i32i8imm", ENCODING_IB)
1255 ENCODING("i64i32imm", ENCODING_ID)
1256 ENCODING("i64i8imm", ENCODING_IB)
1257 ENCODING("i8imm", ENCODING_IB)
1258 ENCODING("i64i32imm_pcrel", ENCODING_ID)
1259 ENCODING("i16imm_pcrel", ENCODING_IW)
1260 ENCODING("i32imm_pcrel", ENCODING_ID)
1261 ENCODING("brtarget", ENCODING_Iv)
1262 ENCODING("brtarget8", ENCODING_IB)
1263 ENCODING("i64imm", ENCODING_IO)
1264 ENCODING("offset8", ENCODING_Ia)
1265 ENCODING("offset16", ENCODING_Ia)
1266 ENCODING("offset32", ENCODING_Ia)
1267 ENCODING("offset64", ENCODING_Ia)
1268 errs() << "Unhandled relocation encoding " << s << "\n";
1269 llvm_unreachable("Unhandled relocation encoding");
1272 OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1273 (const std::string &s,
1274 bool hasOpSizePrefix) {
1275 ENCODING("RST", ENCODING_I)
1276 ENCODING("GR32", ENCODING_Rv)
1277 ENCODING("GR64", ENCODING_RO)
1278 ENCODING("GR16", ENCODING_Rv)
1279 ENCODING("GR8", ENCODING_RB)
1280 ENCODING("GR16_NOAX", ENCODING_Rv)
1281 ENCODING("GR32_NOAX", ENCODING_Rv)
1282 ENCODING("GR64_NOAX", ENCODING_RO)
1283 errs() << "Unhandled opcode modifier encoding " << s << "\n";
1284 llvm_unreachable("Unhandled opcode modifier encoding");